IR HiRel Space Product update

Transcription

1 IR HiRel Space Product update MEWS26 October 24, 2013 Tiva Bussarakons Max Zafrani

2 International Rectifier Globally 8 Manufacturing Centers, 11 Design Centers Global Service and Technical Assistance Centers Newport, Wales, UK TS16949 ISO14001 ISO9001 Reigate, U.K. Frankfurt, Germany Skovlunde, Denmark Shenzen, China San Jose, CA ISO9001 MILPRF38534 Japan St Paul, MN Leominster, MA ISO14001 ISO9001 MILPRF38534 MILPRF19500 JANS Provence, France Shanghai, China Rhode Island Durham, NC Irvine, CA Pavia, Italy Singapore El Segundo, CA TS16949, ISO9001, JANS, ISO14001 Temecula, CA Mesa, AZ TS16949 TS16949 JANS ISO9001 ISO14001 ISO14001 Tijuana, Mexico TS16949, ISO9001 ISO

3 HiRel Product Technologies DC/DC converters o 5W to >250W output power, higher power with parallel operations o Converter efficiency of up to 92% o PCB assembly style and enclosed aluminum housing available o DSCC class H and K SMDs o Single, dual, triple, and quad outputs Hybrids/Modules o Application specific hybrids ie: Solid State Relays, AC Switches, etc o Custom packaging ie: hermetic and near hermetic o Extended temperature range, extensive screening operation o Rad Hard Low Drop Out Regulators o Half bridges o H-bridges o 3-Phase bridges Discrete Semiconductors o RAD-Hard MOSFETs and MOSFET Drivers o Logic Level RAD-Hard MOSFETs o Hermetic MOSFETs and IGBTs o Schottky Rectifiers 3

4 Development History of IR s Rad-Hard MOSFETs st generation radhard MOSFETs with excellent total dose performance N: 100 to 500V P: 60 to 200V Hexagon cells 5 µm feature size 2 nd generation Reduced RDS(on) Reduced QG Improved SEGR/SEB N: 30V to 250V P: 60 to 200V Stripe planar technology 1.5 µm feature size 3 rd generation Best in class RDS(on) Improved SEE SOA Shape die to better fit packages for optimum RDS(on)/QG performance 1 st logic level gate drive Developed specifically for POL buck regulators and synchronous rectification to improve efficiency Comparable TID/SEE to R6 N: 100 to 600V N: 60 to 250V P: 60V Stripe planar technology 0.6 µm feature size R5, R6 AND R7 TECHNOLOGY (Stripe planar technology) R7 Stripe planar technology 0.6 µm feature size Logic level gate drive Developed with further reduction in RDS(on) and gate charge for low voltage POL and synchronous rectification designs with comparable TID and SEE performance to R6 N: 20V to 60V R8 Trench technology 0.5 µm feature size 5 µm 1.5 µm 0.6 µm 0.5 µm 4

5 Rad-Hard MOSFET Voltage vs Generation BVDSS N-Channel BVDSS P-Channel 600V 500V 400V Gen4 R6-200V Gen4 R5 250V 100V 60V 30V R5 R7 89 >> R8-100V - 60V - 30V R7 89 >> Gen4 30V to 500V 100K to 1000K Rads R5 30V to 250V 100K to 1000K Rads R6 100V to 600V 100K to 300K Rads R7 Logic Level 60V to 250V 100K to 300K Rads R8 Trench 20V to 60V 100K to 300K Rads Gen4-60V to -200V 100K to 1000K Rads R5-30V to -200V 100K to 1000K Rads R6 (Dev) -60V to -200V 100K to 300K Rads R7 Logic Level -60V to -100V 100K to 300K Rads 5

6 Radiation Hardened MOSFETs Three New Discrete Products from IR R8 - New Rad-Hard MOSFETs SMD New Low Power Package SupIR SMD-2 - New High Power Package Extended Performance Characterization Extended SOA curves for linear applications 6

7 R8 New Rad-Hard MOSFET for POL Applications Rad-Hard N Channel MOSFET Trench Technology FEATURES: 20 V BVDSS ±12V BVGSS 100 Krads to 300 Krads TID SEE immune with LET of 81 MeV-cm 2 /mg Logic level gate drive similar to R7 RDS(on) mω typ./15 mω max. QG nc typ./24 nc max. Available in SMD 0.2, the industry s smallest surface-mount power package and TO-39 o IRHLNM87Y20 o IRHLF87Y20 Part Number TID Package BVDSS ID RDS(on) max QG max ƟJC IRHNM87Y20SCS 100Krads SMD V 17A 15 mω 24 nc 3.5 C/W IRHNM83Y20SCS 300Krads SMD V 17A 15 mω 24 nc 3.5 C/W IRHLF87Y20SCS 100Krads TO-39 20V 12A 32 mω 27 nc 8.0 C/W IRHLF83Y20SCS 300Krads TO-39 20V 12A 32 mω 27 nc 8.0 C/W 7

8 VDS (V) R8 Typical Single Event Effects (SEE) Performance Tests performed at Brookhaven National Laboratory ION LET Energy Range VDS (V) MeV/(mg/ cm2) MeV µm VGS = 0V VGS = -1V VGS = -3V VGS = -5V VGS =-10V Br I Au IRHLC87Y20 Typical SEE SOA BR I AU VGS (V) 8

9 R8 Typical POL Application Designed for Point of Load (POL) voltage regulators, general purpose switching and linear voltage regulator applications 9

10 R8 Increases Efficiency Performance, R8 vs. R5 R8 offers efficiency improvement over R5 (refer to efficiency plots below) o 1.2V output: 3.9 to 6.0% o 3.3V output: 1.5 to 3.1% R5: IRHNJ57Z30, 30V - RDS(on) = 20 mω max, QG = 65 nc max R8: IRHNM87Y20, 20V - RDS(on) = 15 mω max, QG = 24 nc max 3.1% 1.5% 3.9% 6.0% 10

11 Selection of Hermetic Packages Low Power: 0.6W to 29W NEW TO-39 MO-036 UB LCC-6 SMD-0.2 LCC-18 LCC-28 (NM/U8) High Power: 75W to 300W NEW SMD-0.5 TO-257 Also: Low Ohmic/Tab-less SMD-1 TO-254 Also: Low Ohmic/Tab-less SMD-2 SupIR SMD-2 (NX) 11

12 New SMD 0.2 Package for Low Power MOSFETs A space qualified compact surface mount package only from IR for low power applications Industry s smallest surface mount power package 50% smaller than SMD % lighter (only 0.25 g) Aluminum nitride (AlN) case R5 and R7 250V devices are in qualification Patented design (U.S. Patent No. 7,508,506 B2) 0.25g 0.2 (5 mm) NEW SMD (8 mm) 1.0 g 0.3 (8 mm) SMD (10 mm) DLA JANS Qualified Devices JANSR2N7503U8 (IRHNM57110SCS), R5, 100V, N Channel JANSR2N7506U8 (IRHNM597110SCS), R5, 100V, P Channel IRHNM77110SCS (JANSR2N7609U8), R7, 100V, N Channel in process 12

13 New SMD 0.2 Package Construction Lid Kovar or ceramic O-Ring - Kovar Cu Metalization Top View Wall/Bottom - AlN Internal View Bottom View L x0.21 W x 0.10 H 13

14 NEW New SupIR SMD-2 Package SMD SupIR SMD-2 + Carrier = (37%) 37% Foot Print Reduction SupIR SMD-2 - Latest packaging Innovation from International Rectifier for Space Grade Rad-Hard Power MOSFETs and Power Rectifiers FEATURES: JANS qualified IAW MIL-PRF Improved performances compared to the nearest packaging solutions, SMD-2 package with a carrier SMD-2 with Carrier 35% smaller, in 2 vs in 2 45% lighter. 2.8 g vs. 5.1 g Lower thermal resistance by 0.25 C/W Lower package resistances by 30%, 0.68 Ω vs Ω Lower parasitic inductance by 76%, 0.52 µh vs µh Yield a higher current rating, 82A vs. 56A Facilitates assembly design and reduces costs Accommodates the largest IR s size 6 die 14

15 SupIR SMD-2 - Package Construction/Qualification Lead OFHC Cu Lid - Kovar Frame Alumina, 94% Seal Ring - Kovar Base 85% W/ 15% Cu Products Qualification HFB60HNX20SCS, 35ns, 200V, 60A -- released IRHNX67160SCS, R6, 100V in process IRHNX67164SCS, R6, 150V in process IRHNX67260SCS, R6, 200V in process IRHNX67264SCS, R6, 250V in process JANS Qualified IAW MIL-PRF X-ray, Wire Bond Pull, Die shear, Leak testing PIND RGA Salt atmosphere 300C bake Barometric pressure 33 Torr) 500 temperature cycles (-55C to 150C, air to air) Solderability Thermal shock 15 cycle (-55C to 125C, liquid to liquid) Terminal strength Moisture resistance Shock, vibration, constant acceleration Resistance to soldering heat S level qualified HFB60HNX20SCS Available soon 15

16 SupIR SMD-2 In-Circuit Benefits Example IR DC-DC converter EGA Series High efficiency 300W EPC for GaN SSPA SupIR-SMD-2 Primary H-bridge with four MOSFETs and a secondary Hy-Bridge (current doubler) stage with two MOSFETs for synchronous rectification SMD-2 with leads can only dissipate about 2W SMD-2 would require parallelling MOSFETs which has a penalty in switching losses and in the snubber size needed to dampen the energy from the stray inductance of the transformer that may cause excess stress to the MOSFET due to their output capacitance SupIR SMD-2 can dissipate 4W, no need for parallel: 6 MOSFETs instead of 12 16

17 Benefits of SupIR SMD-2 SupIR SMD-2 vs. SMD 2 with Leads Benefits of SupIR SMD-2 2x power dissipation 6 MOSFETs instead of % increase in efficiency lower cost 18 cm² smaller 40 g lighter PCB-area less circuit complexity higher reliability Efficiency 95.0% 90.0% 85.0% 80.0% EGA Efficiency (Vin 50V, V1=50V) +25 C -40 C -20 C +75 C 75.0% V1 Current [A] Load condition: V1: 50V, V2: +8V 0A, V3: -8V 0A 17

18 Systems GIDEP SYSTEM CENTRAL DATABASE for Information and Data Exchange GIDEP DATABASE STRUCTURE Failure Experience Data (FED) Diminishing Manufacturing Sources & Material Shortages (DMSMS) Product Information Data - Product Alert - Product Advisory - EOL - Last Time Buy - Product Change Notice - Process Change Notice 18

19 Systems GIDEP SYSTEM Issued GIDEP INFORMATION AND DATA records are posted and accessible on IR Web Site: 19

20 SOA Curve and Linear Mode Operation Where is it safe to operate the MOSFET in the Id, Vds and pulse width domain? The straight SOA lines assume that power dissipation is uniform under all power conditions However power dissipation is not uniform in the MOSFET under all power conditions Local thermal runaway in the MOSFET s linear mode of operation limits the SOA 20

21 How is the new method done? Better method of assigning SOA Dr. P. Spirito [1] et. Al. suggest As transconductance increases (e.g. in shorter channel lengths, from planar to trench devices [2] ): 1. the drain current temperature dependence can become positive like power BJTs 2. the likelihood of hot spots (thermal instability) increases 3. and the SOA degrades 21

22 Transfer Curves Per Generation Shorter Channel Length Stronger Temperature Dependence of Drain Current Greater Propensity for Severe Thermal Instability 22

23 R5 200V P-Channel Spirito versus Actual (new DC curves) Measured Curve Spirito Curve 23

24 Preventing Linear Mode failure Use older generation MOSFETs with lower gain when possible Select devices with low ZTC point Make sure that the MOSFET Zero Temperature Coefficient (ZTC) point is low or operate above it Avoid operation near the SOA boundary Choose smaller of two devices as it will be less sensitive to thermal current focusing Un-Safe Safe ZTC 24