Chapter 3 The Field-Effect ( 場效 ) Transistor

Transcription

1 Chapter 3 The Field-Effect ( 場效 ) Transistor 1 In this chapter, we introduce a major type of transistor, the Metal-Oxide ( 氧化物 )-Semiconductor Field-Effect Transistor (MOSFET). The MOSFET led to the electronics revolution ( 革命 ) of the 1970s and 1980s, in which the microprocessor ( 微處理器 ) made possible powerful ( 強而有力的 ) desktop ( 桌上 ) computers, laptop ( 膝上 ) computers, and sophisticated ( 多功能的 ) handheld ( 手持的 ) calculators. Because the MOSFET can be made very small, so high-density ( 密度 ) Very Large Scale Integration (VLSI) circuits and high-density memories ( 記憶體 ) are possible. There are two complementary ( 互補的 ) MOSFET devices, the n-channel MOSFET (NMOS) and the p-channel MOSFET (PMOS). Each device is equally important and allows a high degree of flexibility ( 彈性, 適應性 ) in electronics circuit design. Another type of Field-Effect Transistor is the junction FET. There are two general categories ( 種類 ) of junction field-effect transistors (JFETs) the pn junction FET (pn JFET) and the metal-semiconductor field-effect transistor (MESFET), which is fabricated with a Schottky barrier junction. JFETs were developed before MOSFETs, but the applications and uses of MOSFETs have far surpassed ( 遠超越 ) those of the JFET. However, we will consider a few JFET circuits in this chapter.

2 Preview: In this chapter, we will: Study and understand the operation and characteristics of the various types of MOSFETs. Understand and become familiar with the dc analysis and design techniques of MOSFET circuits. Examine three applications of MOSFET circuits. Investigate current source ( 電流電源 ) biasing of MOSFET circuits, such as those used in integrated circuits. Analyze the dc biasing of multistage or multitransistor circuits. Understand the operation and characteristics of the junction field-effect transistor, and analyze the dc response of JFET circuits. Incorporate ( 嵌入 ) a MOS transistor in a design application that enhances ( 加強 ) the simple electronic thermometer design using a diode discussed in Chapter 1. (Skip) 3.1 MOS Field-Effect Transistor Objective: Understand the operation and characteristics of the various ( 各式各樣的 ) types of metal-oxide semiconductor field-effect transistors (MOSFETs). As mentioned above, the metal oxide - semiconductor field - effect transistor (MOSFET) became a practical reality in the 1970s. As compared to BJTs (Bipolar Junction Transistor), the MOSFET can be made very small [that is, it occupies ( 佔用 ) a very small area on an IC chip]. It is known that digital circuits can be designed using only MOSFETs, with essentially ( 基本地 ) no resistors or diodes 2

3 required. Thus, high-density ( 密度 ) MOSFET VLSI circuits, including microprocessors and memories, can be fabricated ( 製造 ). This has made possible the handheld calculator, the powerful personal computer, and the laptop computer. Besides, MOSFETs can also be used in analog circuits, as we will see in the next chapter. In the MOSFET, the current is controlled by an electric field applied perpendicular-to ( 垂直 ) both the semiconductor surface and to the direction of current. The phenomenon ( 現象 ) used to modulate ( 調變 ) the conductance ( 電導 ) of a semiconductor, or control the current in a semiconductor, by applying an electric field perpendicular to the surface is called the field effect. The basic transistor principle ( 原則 ) is that the voltage between two terminals controls the current through the third terminal. In the following two sections, we will discuss various types of MOSFETs, develop the i v characteristics, and then consider the dc biasing of various MOSFET circuit configurations Two-Terminal MOS Structure The heart of the MOSFET is the metal-oxide-semiconductor capacitor shown in Figure 3.l. The metal may be aluminum ( 鋁 ) or some other type of metal. ( 畫圖 ) 3

4 4 In the figure, the parameter t ox is the thickness ( 厚度 ) of the oxide ( 氧化物 ) and ox is the oxide permittivity ( 介電係數 ). The physics of the MOS structure can be explained with the aid ( 幫助 ) of a simple parallel ( 平行的 )-plate ( 板 ) capacitor. The capacitance of a parallel plate capacitor, neglecting ( 忽略 ) fringing ( 邊緣的 ) fields, is C = A/d, where A is the area of one plate, d is the distance between plates, and is the permittivity of the medium ( 介質 ) between the plates. It is noted that in most cases, the metal is replaced by a high-conductivity polycrystalline ( 多晶 ) silicon layer deposited ( 使沉澱, 堆積 ) on the oxide. However, the term metal is usually still ( 仍然地 ) used in referring to MOSFETs. Figure 3.2(a) shows a parallel-plate capacitor with the top plate at a negative voltage with respect to the bottom plate. An insulator ( 絕緣 ) material separates ( 分開 ) the two plates. With this bias, a negative charge exists on the top plate, a positive charge exists on the bottom plate, and an electric field

5 is induced ( 感應 ) between the two plates, as shown. Let us look at an MOS capacitor with a p-type semiconductor substrate ( 基座 ) as shown in Figure 3.2(b). ( 畫圖 ) The top metal terminal, also called the gate, is at a negative voltage with respect to ( 相對於 ) the semiconductor substrate. 5 From the concept of the parallel-plate capacitor, a negative charge will exist on the top metal plate and an electric field will be induced in the direction shown in the figure. If the electric field penetrates ( 穿透 ) the semiconductor, the holes in the p-type semiconductor will experience ( 承受 ) a force toward the oxide-semiconductor interface ( 介面 ). The equilibrium distribution of charge in the MOS capacitor

6 with this particular applied voltage is shown in Figure 3.2(c). An accumulation ( 堆積 ) layer ( 層 ) of positively charged holes at the oxide-semiconductor interface ( 界面 ) corresponds to ( 相當於 ) the positive charge on the bottom plate of the MOS capacitor. When the polarity of the applied voltage is reversed ( 相反的 ), the MOS capacitor is in Figure 3.3(a). ( 畫圖 ) 6 Figure 3.3(a) Positive gate bias In this case, a positive charge now exists on the top metal plate and the induced electric field is in the opposite direction, as shown. Now if the electric field penetrates the semiconductor, holes in the p-type material will experience ( 遭受 ) a force away from the oxide-semiconductor interface. As the holes are pushed away ( 推開 ) from the interface, a negative space-charge region is created, because of the fixed acceptor impurity atoms. The negative charge in the induced depletion region corresponds to the negative charge on the bottom plate of the MOS capacitor. Figure 3.3(b) shows the equilibrium distribution of charge in the MOS capacitor with this applied voltage. ( 畫圖 )

7 When a larger positive voltage is applied to the gate, the magnitude of the induced electric field increases. Consequently, minority carrier electrons are attracted ( 吸引 ) to the oxide-semiconductor interface, as shown in Figure 3.3(c). This region of minority carrier electrons is called an electron inversion ( 逆轉 ) layer. The magnitude of the charge in the inversion layer is a function of the applied gate voltage. The same basic charge distributions can be obtained in a MOS capacitor with an n-type semiconductor substrate. 102/12/10 甲, 乙 Figure 3.4(a) shows this MOS capacitor structure, with a positive voltage applied to the top gate terminal. ( 畫圖 ) 7

8 8. Figure 3.4(a). Positive gate bias and the electron accumulation layer A positive charge is created on the top gate and an electric field is induced in the direction shown. In this situation, an accumulation layer of electrons is induced in the n-type semiconductor. Figure 3.4(b) shows the case when a negative voltage is applied to the gate terminal. ( 畫圖 ) In this case, a positive space-charge region is induced in the n-type substrate by the induced electric field.

9 9 When a larger negative voltage is applied, a region of positive charge is created at the oxide-semiconductor interface, as shown in Figure 3.4(c). This region of minority carrier holes is called a hole inversion layer. The magnitude of the positive charge in the inversion layer is a function of the applied gate voltage. An MOSFET in which a voltage must be applied to the gate to create an inversion layer is called enhancement ( 加強 ) mode [another mode to be discussed later is called depletion ( 空乏 ) mode]. Thus, for the MOS capacitor with a p-type substrate, a positive gate voltage must be applied to create the electron inversion layer; for the MOS capacitor with an n-type substrate, a negative gate voltage must be applied to create the hole inversion layer. 100/12/6 二甲, 乙 101/11/27 二甲, 乙 n-channel Enhancement-Mode MOSFET We apply the concepts of an inversion layer charge in a MOS capacitor to create a transistor. Transistor Structure Figure 3.5(a) shows a simplified cross section of an n-channel Enhancement-Mode MOS field-effect transistor.

10 10 It is seen that the gate, oxide, and p-type substrate regions are the same as those of an MOS capacitor. In addition, there are two n-regions, called the source ( 源級 ) terminal and drain ( 洩級 ) terminal. The current in a MOSFET is the result of the flow of charge in the inversion layer, also called the channel region, adjacent ( 臨近 ) to the oxide semiconductor interface. The channel length L and channel width W are defined on the figure. The channel length of a typical integrated circuit MOSFET is 6 less than 1 µm ( 10 m) ( 現在技術大概 20~30 奈米 ), which means that MOSFETs are small devices. The oxide thickness t ox is typically on the order of angstroms ( 10 m), or less. The diagram in Figure 3.5(a) is a simplified sketch of the basic structure of the transistor.

11 11 Figure 3.5(b) shows a more detailed ( 詳細的 ) cross section of a MOSFET fabricated into an integrated circuit configuration. A thick ( 厚的 ) oxide, called the field oxide, is deposited ( 放置 ) outside the area in which the metal interconnect lines are formed. As mentioned before, the gate material is usually heavily doped polysilicon. Even though ( 即使 ) the actual structure of a MOSFET may be fairly ( 相當地 ) complex ( 複雜的 ), the simplified diagram may be used to develop the basic transistor characteristics. Basic Transistor Operation 104/04/30 二甲, 乙 With zero bias applied to the gate ( 柵級 ), the source ( 源級 ) and drain ( 洩級 ) terminals are separated by the p-region, as shown in Figure 3.6(a). ( 畫圖 )

12 This is equivalent to ( 等同於 ) two back-to-back diodes, as shown in Figure 3.6(b). The current in this case is essentially zero. If a large enough positive gate voltage is applied, an electron inversion layer is created at the oxide-semiconductor interface and this layer connects the n-source to the n-drain, as shown in Figure 3.6(c). A current can then be generated between the source and drain terminals. 12

13 13 Since a voltage must be applied to the gate to create the inversion charge, this transistor is called an enhancement -mode MOSFET. Also, since the carriers in the inversion layer are electrons, this device is also called an n-channel MOSFET (NMOS). The source terminal supplies ( 提供 ) carriers that flow through the channel, and the drain terminal allows the carriers to drain ( 排出 ) from the channel. For the n-channel MOSFET, electrons flow from the source to the drain with an applied drain-to-source voltage. This means that the conventional current enters the drain and leaves ( 離開 ) the source. The magnitude of the current is a function of the amount ( 數量 ) of charge in the inversion layer, which in turn ( 依次 ) is a function of the applied gate voltage. It is noted that since the gate terminal is separated from the channel by an oxide or insulator, there is no gate current. Similarly, since the channel and substrate are separated by a space-charge region, there is essentially no current through the substrate Ideal MOSFET Current Voltage Characteristics NMOS Device An important parameter of the n-channel MOSFET is the threshold ( 門檻, 起始 ) voltage denoted as V TN. V TN is defined as the applied gate voltage required to create an inversion charge with the density equaling to the concentration of majority carriers in the semiconductor substrate. 102/12/17 甲乙

14 14 In simple terms, we can think of the threshold voltage as the gate voltage required to turn on the transistor. Note that the usual ( 通常的 ) notation for threshold voltage is V T. However, since we have ever defined the thermal voltage as V T = kt/q, we will use V TN for the threshold voltage of the n-channel device. For the n-channel enhancement-mode MOSFET, the threshold voltage is positive ( 加到 Gate), because a positive gate voltage is required to create the inversion charge in the p substrate. If the gate voltage is less than the V TN, no inversion layer electron can be formed in the channel, and the current in the device is essentially zero. On the other hand, if the gate voltage is greater than the threshold voltage, applying a drain-to-source voltage will generate a drain-to-source current. The gate and drain voltages are measured with respect to ( 相對的 ) the source. Figure 3.7(a) shows an n-channel enhancement-mode MOSFET with the source and substrate terminals connected to ground. ( 畫圖 )

15 15 The figure shows that the gate-to-source voltage is less than the threshold voltage, and there is a small drain-to-source voltage. With this bias configuration, there is no electron inversion layer, the drain-to-substrate pn junction is reverse biased, and the drain current is zero [neglecting pn junction leakage ( 漏 ) currents]. Figure 3.7(b) shows the same MOSFET with an applied gate voltage greater than the threshold voltage. In this situation ( 狀況 ), an electron inversion layer is created and, when a small drain voltage is applied, electrons in the inversion layer flow from the source to the positive drain terminal. The conventional current enters the drain terminal and leaves the source terminal. Note that a positive drain voltage creates ( 產生 ) a reverse-biased drain-to-substrate pn junction, so current flows through the channel region and not through a pn junction.

16 The i D versus v DS characteristics for small values of v DS at three v GS voltages are shown in Figure Note that the voltage notation v DS and v GS, with the dual ( 二重的 ) subscript ( 下標 ), denotes the voltage between the drain (D) and source (S) and between the gate (G) and source (S), respectively. Usually, implicit ( 隱含 ) in the notation is that the first subscript is positive with respect to the second subscript. It can be seen from Figure 3.8 that when v GS < V TN, the drain current is zero. On the other hand, when v GS is greater than V TN, the channel inversion charge is formed and the drain current increases with v DS. Furthermore ( 而且 ), when a larger gate voltage is applied, a larger inversion charge density will be created, and the drain current will be greater for a given value of v DS. ( 濃度大則導電性較好 ) Figure 3.9(a) shows the basic NMOS structure for v GS > V TN

17 and a small applied v DS. ( 畫圖 ) In this figure, the thickness of the inversion channel layer qualitatively ( 定性地 ) indicates the relative charge density, which for this case is essentially constant along the entire ( 整個的 ) channel length. 100/12/13 甲, 乙 17

18 18 The corresponding i D versus v DS curve is also shown in the figure. 101/12/04 二甲, 乙 Figure 3.9(b) shows the situation when v DS increases. It is seen that as the drain voltage v DS increases, the voltage drop across the oxide near the drain terminal decreases (hence the gate to substrate voltage near the drain decreases), which means that the induced inversion charge density near the drain also decreases. This makes the incremental conductance of the channel at the drain side decreases, which causes the slope of the i D versus v curve to decrease. DS This effect is shown in the i D versus v DS curve in the figure. As v DS increases to the point where the potential difference, ( v GS - v DS ), across the oxide at the drain terminal is equal to V TN, the induced inversion charge density at the drain terminal is zero. This effect is shown schematically ( 綱要的 ) in Figure 3.9(c). For this condition, the incremental channel conductance at the drain is zero, which means that the slope of the i D versus v DS curve is zero. The drain-to-source voltage that produces zero inversion charge density at the drain terminal is denoted as v (sat). We can write DS

19 or 19 When v DS becomes larger than v DS (sat), the point in the channel at which the inversion charge is zero moves from the drain toward the source terminal. In this case, electrons enter the channel at the source, travel through the channel toward the drain, and then, at the point where the charge goes to zero, are injected ( 射 ) into the space-charge region, where they are swept by the E-field to the drain contact. In the ideal MOSFET, the drain current is constant for v DS > v (sat). 102/12/24 二甲, 乙 DS This region of the i D versus v DS characteristic is referred to as the saturation ( 飽和 ) region, which is shown in Figure 3.9(d). As the applied gate-to-source voltage changes, the i D versus v curve changes, as shown previously in Figure 3.8. DS Figure 3.8 It is observed that the initial slope of i D versus v DS increases as v increases. GS Also, Equation (3.1(b)) shows that v (sat) is a function of DS

20 v GS. 104/05/05 二甲, 乙 Therefore, we can generate the family of curves for this n - channel enhancement mode MOSFET as shown in Figure Although the derivation ( 推導 ) of the current voltage characteristics of the MOSFET is beyond ( 超越 ) the scope ( 範疇 ) of this text, we can define the relationships. The region for which v DS < v DS (sat) is known as the nonsaturation ( 非飽和 ) or triode ( 三極 ) region. In this region, the ideal current voltage characteristics are described by the equation

21 21 In the saturation region, the ideal current voltage characteristics for v GS V are described by the equation > TN Furthermore, in the saturation region, since the ideal drain current is independent of ( 無關於 ) the drain to source voltage ( v DS ), the incremental or small-signal resistance is infinite. That is, The parameter K n is sometimes called the transconduction ( 轉導 ) parameter for the n-channel device. However, this term is not to be confused ( 疑惑 ) with the small-signal transconductance parameter introduced in the next chapter. For simplicity, we will refer to this parameter as the conduction ( 傳導 ) parameter, which for an n-channel device is given by where C ox is the oxide capacitance per unit area, given by and t ox is oxide thickness and ox is the oxide permittivity. 14 For silicon devices, ox = (3.9)( ) F/cm. The parameter n is the mobility of the electrons in the inversion laye, the channel width W and channel length L were shown previously in Figure 3.5(a). As Equation (3.3(a)) indicates, the conduction parameter is a

22 function of both electrical and geometric parameters. Generally, the oxide capacitance and carrier mobility are essentially constants for a given fabrication technology. But the geometry, or width-to-length ratio W/L, is a variable in the design of MOSFETs that is used to produce specific current voltage characteristics in MOSFET circuits. We can rewrite the conduction parameter in the form 22 ' where Kn n Cox and is called the process ( 製程, 處理 ) conduction parameter. ' Normally, K n is considered to be a constant for a given fabrication technology, so the width-to-length ratio W/L is the transistor design variable, as indicated in Equation (3.3(b)). 100/12/20 甲, 乙 101/12/11 二甲, 乙

23 The p-channel Enhancement-Mode MOSFET The complementary ( 互補的 ) device of the n-channel enhancement-mode MOSFET is the p-channel enhancement -Mode MOSFET. Transistor Structure Fig shows a simplified cross section of the p-channel enhancement-mode transistor. ( 畫圖 )

24 24 The substarte is now n-type and the source and drain areas are p-type. The channel length, channel width, and oxide thickness parameter definitions are the same as those for the NMOS device shown in Figure 3.5(a). Basic Transistor Operation The operation of the p-channel device is the same as that of the n-channel device, except the hole is the charge carrier rather than ( 而不是 ) the electron. A negative gate bias is required to induce an inversion layer of holes in the channel region directly under the oxide. The threshold voltage for the p-channel device is denoted as V. TP Since the threshold voltage is defined as the gate voltage required to induce the inversion layer, then V TP < 0 for the p-channel enhancement-mode device. Once the inversion layer has been created, the p-type source region is the source of the charge carrier so that holes flow from the source to the drain. A negative drain voltage is therefore required to induce an electric field in the channel forcing the holes to move from the source to the drain. The conventional current direction, then, for the PMOS transistor is into the source and out of the drain. That is, the conventional current direction and voltage polarity for the PMOS device are reversed compared to the

25 NMOS device. Note in Figure 3.11 the reversal ( 相反 ) of the voltage subscripts. For v SG> 0, the gate voltage is negative with respect to that at the source. Similarly, for v SD > 0, the drain voltage is negative with respect to that at the source Ideal MOSFET Current Voltage Characteristics PMOS Device The ideal current voltage characteristics of the p-channel enhancement-mode device are essentially the same as those shown in Figure 3.10, noting that the drain current is out of the drain and v DS is replaced by v SD. The saturation point is given by vsd (sat) vsg VTP. For the p-channel device biased in the nonsaturation (triode) region, the current is given by 25 In the saturation region, the current is given by and the drain current exits ( 走出 ) the drain terminal. The parameter K p is the conduction parameter for the p-channel device, and is given by

26 In the above equation, W, L, and C ox are the channel width, length, and oxide capacitance per unit area, as previously ( 以前地 ) defined. The parameter p is the mobility of holes in the hole inversion layer. Generally, the mobility of hole inversion layer is less than that of the electron inversion layer. We can also rewrite Equation (3.5(a)) in the form 26 ' p where K = p C ox is the process conduction parameter. For a p-channel MOSFET biased in the saturation region, we have

27 Circuit Symbols and Conventions The conventional circuit symbol for the n-channel enhancement -mode MOSFET is shown in Figure 3.12(a). ( 畫圖 ) The vertical solid line ( 實線 ) denotes the gate electrode ( 極 ), the vertical broken line ( 斷線 ) denotes the channel (the broken line indicates the device is enhancement mode), and the separation between the gate line and channel line denotes the oxide that insulates ( 隔絕 ) the gate from the channel. The polarity of the pn junction between the substrate and the channel is indicated by the arrowhead ( 箭頭 ) on the body or substrate terminal. The direction of the arrowhead indicates the type of transistor,

28 which in this case is an n-channel device. This symbol shows the four-terminal structure of the MOSFET device. In most applications in this text, we will implicitly assume that the source and substrate terminals are connected together. Explicitly drawing the substrate terminal for each transistor in a circuit becomes redundant ( 多餘的 ) and makes the circuits appear more complex. Therefore, instead ( 代替 ), we will use the circuit symbol for the n-channel MOSFET shown in Figure 3.12(b). In this symbol, the arrowhead is on the source terminal and it indicates the direction of current, which for the n-channel device is out of the source. By including the arrowhead in the symbol, we do not need to explicitly indicate the source and drain terminals. We will use this circuit symbol throughout the text except in specific applications. In more advanced texts and journal articles, the circuit symbol of the n-channel MOSFET shown in Figure 3.12(c) is generally used. The gate terminal is obvious and it is implicitly understood that the top terminal is the drain and the bottom terminal is the source. The top terminal, in this case the drain, is usually at a more positive voltage than the bottom terminal. Since this is an introductory text, we will use the symbol shown in Figure 3.12(b) for clarity ( 明晰 ). The conventional circuit symbol for the p-channel enhancement - mode MOSFET appears in Figure 3.13(a). 28

29 Note that the arrowhead direction on the substrate terminal is reversed from that in the n-channel enhancement-mode device. This circuit symbol again shows the four terminal structure of the MOSFET device. The circuit symbol for the p-channel enhancement-mode device shown in Figure 3.13(b) will be used in this text. The arrowhead is on the source terminal indicating the direction of the current, which for the p-channel device is into the source terminal. In more advanced texts and journal articles, the circuit symbol of the p-channel MOSFET shown in Figure 3.13(c) is generally used. Again, the gate terminal is obvious ( 顯然的 ) but includes the O symbol to indicate that this is a PMOS device. It is implicitly understood that the top terminal is the source and the bottom terminal is the drain. 101/12/18 甲, 乙 The top terminal, in this case the source, is normally at a higher potential than the bottom terminal. Again, in this text, we will 29

30 use the symbol shown in Figure 3.13(b) for clarity Additional MOSFET Structures and Circuit Symbols In addition to the n-channel and the p-channel enhancement -mode devices, there are two other MOSFET structures device that need to be considered. They are the n-channel and the p-channel depletion ( 空乏 ) -mode MOSFETs. n-channel Depletion-Mode MOSFET Figure 3.14(a) shows the cross section of an n-channel depletion-mode MOSFET for vgs 0. ( 畫圖 ) 30 Figure 3. 14(a) Cross-section of an n-channel depletion mode MOSFE for vgs 0 In this mode, when zero volts are applied to the gate, an n-channel region or inversion layer exists under the oxide as a result, for example, of impurities introduced during device fabrication. Since an n-region that connects the n-source and n-drain exists, even with zero gate voltage applied, a drain-to-source current

31 may be generated if v DS is applied. The term depletion mode means that a channel exists even at zero gate voltage. To turn off the n-channel depletion-mode MOSFET, we must apply a negative gate voltage. Figure 3.14(b) shows the n-channel depletion mode MOSFET with a negative applied gate-to-source voltage. When a negative gate voltage is applied, it will induce a space-charge region under the oxide, thereby reducing ( 減少 ) the thickness of the n-channel region. The reduced thickness will decrease the channel conductance, which in turn will reduce the drain current. 31 When the gate voltage is equal to the threshold voltage, which is negative for this device, the induced space-charge region extends ( 延伸 ) completely through the n-channel region, and the current goes to zero. On the other hand, if a positive gate voltage is applied, an

32 32 electron accumulation layer will be created, as shown in Figure 3.14(c). This electron accumulation layer will increase the drain current. The general i D versus v DS family of curves for the n-channel depletion-mode MOSFET is shown in Figure ( 畫圖 ) The current voltage characteristics defined by Equations (3.2(a)) and (3.2(b)) apply to both enhancement- and depletion-mode n-channel devices. The only difference is that the threshold voltage V TN is positive for the enhancement-mode MOSFET and negative for the depletion-mode MOSFET.

33 33 Even though the current voltage characteristics of enhancement - and depletion-mode devices are described by the same equations, different circuit symbols are used, simply for purposes of clarity ( 清楚 ). The conventional circuit symbol for the n-channel depletion-mode MOSFET is shown in Figure 3.16(a). In this figure, the vertical solid line denoting the channel indicates the device is depletion mode. A comparison of Figures 3.12(a) and 3.16(a) shows that the only difference between the enhancement- and depletion-mode symbols is the broken versus the solid line representing the channel. A simplified symbol for the n-channel depletion-mode MOSFET is shown in Figure 3.16(b). The arrowhead is again on the source terminal and indicates the direction of current, which for the n-channel device is out of the source.

34 34 The heavy solid line represents the depletion-mode channel region. Again, using a different circuit symbol for the depletion-mode device compared to the enhancement-mode device is simply for clarity in a circuit diagram. 102/12/26 二甲, 乙 p-channel Depletion-Mode MOSFET Figure 3.17 shows the cross section of a p-channel depletion -mode MOSFET, as well as the biasing configuration and current direction. In the depletion-mode device, a channel region of holes already exists under the oxide, even with zero gate voltage. To turn the device off, a positive gate voltage is required. Hence the threshold voltage of a p-channel depletion-mode MOSFET is positive ( V TP > 0). The conventional and simplified circuit symbols for the p-channel depletion mode device are shown in Figure 3.18.

35 35 Figure 3.18 The p-channel depletion mode MOSFET: (a) conventional circuit symbol and (b) simplified circuit symbol The heavy solid line in the simplified symbol represents the channel region and denotes the depletion-mode device. The arrowhead is again on the source terminal and it indicates the current direction. Complementary MOSFETs Complementary MOS (CMOS) technology uses both n-channel and p-channel devices in the same circuit. Figure 3.19 shows the cross section of n-channel and p-channel devices fabricated on the same chip.

36 36 CMOS circuits, in general, are more complicated to fabricate than circuits using entirely ( 完全地 ) NMOS or PMOS devices. Yet, as we will see in later chapters, CMOS circuits have great advantages ( 優點 ) over just NMOS or PMOS circuits. In order to fabricate n-channel and p-channel devices that are electrically equivalent, the magnitude of the threshold voltages must be equal, and the n-channel and p-channel conduction parameters must be equal. Since, in general, and are not equal, the design of n p equivalent transistors involves adjusting the width-to-length ratios of the transistors Summary of Transistor Operation We have presented a first-order model of the operation of the MOS transistor. For an n-channel enhancement-mode MOSFET, a positive gate-to-source voltage, greater than the threshold voltage V TN, i.e., v GS > V TN, must be applied to induce an electron inversion layer to turned on the device. For an n-channel depletion-mode device, a channel between the source and drain exists even for v GS =0. In this mode, the threshold voltage is negative, so that a negative value of v GS is required to turn the device off. For a p-channel device, all voltage polarities and current directions are reversed compared to the NMOS device. That is, for the p-channel MOSFET, V TP < 0 for the enhancement-mode, and V TP> 0 for the depletion-mode.

37 37 Table 3.1 lists the first-order equations that describe the i v relationships in MOS devices. We note that K and K are positive values, and that the drain n p current i D is positive when it enters into the drain for the NMOS device; and is positive when it leaves out of the drain for the PMOS device. 104/05/07 甲乙 Short-Channel Effects 99/12/14 99/12/18 第三次考試範圍 (2~4 至此 ) The current voltage relations given by Equations (3.2(a)) and (3.2(b)) for the n-channel device and Equations (3.4(a)) and (3.4(b)) for the p-channel device are the ideal relations for long-channel devices.

38 38 A long-channel device is generally one whose channel length is greater than 2 µm. In this device, the horizontal electric field in the channel induced by the drain voltage and the vertical electric field induced by the gate voltage can be treated independently ( 獨立地 ). However, the channel length of present-day ( 現今的 ) devices is on the order of 0.2 µm or less ( 實際更短 ). For these short-channel devices, there are several effects that will influence ( 影響 ) and change the long-channel current voltage characteristics. One such effect is a variation in threshold voltage. Because the value of threshold voltage is a function of the channel length. This variation must be considered in the design and fabrication of these devices. In addition, as the drain voltage increases, the effective threshold voltage decreases. That is, the threshold voltage ia also a function of the drain voltage. This effect also influences the current voltage characteristics. The other effect of the short channel is on the process conduction parameters, to the carrier mobility. K ' n K and ' n n Cox ' K p, which are directly related Previously, we have assumed that the carrier mobilities and corresponding process conduction parameters are constant. However, the carrier mobility values are functions of the vertical electric field in the inversion layer.

39 39 As the gate voltage and vertical electric field increase, the carrier mobility decreases. This result, again, directly influences the current voltage characteristics of the device. Another effect that occurs in short-channel devices is velocity saturation. As the horizontal electric field increases, the velocity of the carriers reaches a constant value and will no longer increase with an increase in drain voltage. Velocity saturation will lower the v DS (sat) voltage value. Thus, the drain current will reach its saturation value at a smaller v DS voltage. In this situation, it is found that the drain current also becomes approximately a linear function of the gate voltage in the saturation region rather than the quadratic function of gate voltage in the long-channel characteristics. ( 不是二次方 ) Although the analysis of modern MOSFET circuits must take into account these short-channel effects, we will use the long-channel current voltage relations in this introductory text. 97/12/11 只上一節 100/12/22 甲, 乙 Additional Nonideal Current Voltage Characteristics In addition to the short-channel effects described in the last subsection, there are five nonideal effects in the current voltage characteristics of MOS transistors that must be considered. They are the finite output resistance in the saturation region, the body effect, subthreshold conduction, breakdown effects, and temperature effects. 98/12/01

40 Finite output resistance In the ideal case, when a MOSFET is biased in the saturation region, the drain current i D is independent of drain-to-source voltage v DS. That is, the increment resistance is infinite. However, in actual MOSFET i D versus v DS characteristics, a nonzero slope does exist beyond the saturation point. The reason was mentioned before that for v DS > v DS (sat), the actual point in the channel at which the inversion charge goes to zero moves away from the drain terminal (see Figure 3.9(d)). 40 As the effective channel length decreases, a phenomenon ( 事物 ) called channel length modulation will result. An exaggerated ( 誇大的 ) view of the current voltage characteristics is shown in Figure It can be seen that the curves can be extrapolated ( 外插的 ) so that they intercept ( 截切 ) the voltage axis at a point v DS = VA.

41 41 The voltage V A is usually defined as a positive quantity ( 量 ). The slope of the curve in the saturation region can be described by expressing the i D versus v DS characteristic in the form, for an n-channel device, where is a positive quantity called the channel-length modulation parameter. The parameters and V A are related ( 相關的 ). To see this, from Equation (3.7), we find that (1 v DS ) 0 at the extrapolated point where i D =0. At this point, v DS = VA, which means that V A=1/. Because of the similarity ( 相似性 ) with the Early effect in BJTs, the quantity V A or 1/ is usually called Early voltage. The output resistance due to the channel length modulation is defined as

42 42 From Equation (3.7) and (3.8), the output resistance, evaluated at the Q-point, is Since 2 n( GSQ TN ) DQ K V V I, r o can also be written as The output resistance r o is also a factor in the small-signal equivalent circuit of the MOSFET to be discussed in the next chapter. 102/12/31 甲乙 Body Effect Up to this point, we have assumed that the substrate, or body, is connected to the source. In this bias condition, the threshold voltage is a constant. However, in integrated circuits, the p-type substrates of all n-channel MOSFETs are usually common and are tied to the most negative potential in the circuit. An example of two n-channel MOSFETs in series is shown in Figure The p-type substrate is common to the two transistors, and the drain of M 1 is common to the source of M 2.

43 43 When the two transistors are conducting, there is a nonzero drain-to-source voltage on M 1, which means that the source of M is not at the same potential as the substrate. 2 These bias conditions mean that a reverse-bias voltage exists across the source substrate pn junction (of 2 M ). The change in the source substrate junction voltage will change the threshold voltage. This is called the body effect (The same situation exists in p-channel devices). For example, consider the n-channel device shown in Figure 3.22.

44 Figure 3.22 An n-channel enhancement-mode MOSFET with a substrate voltage If a zero- or reverse-biased source substrate pn junction exists, i.e., vsb 0, the threshold voltage for this condition is found to be 44 In Equation (3.10), V TNO is the threshold voltage for vsb 0, is called the bulk threshold or body-effect parameter, and is a semiconductor parameter. is related to device properties, and is typically on the order of 1/2 0.4~0.5 V ; f is a function of the semiconductor doping, typically on the order of 0.35~0.4 V. We see from Equation (3.10) that the threshold voltage in n-channel devices increases due to this body effect. (for p-channel if vsb 0, V TP will decrease due to body effect) The body effect can cause a degradation ( 惡化 ) in circuit performance ( 效能 ) because of the changing threshold voltage. However, we will generally neglect ( 忽略 ) the body effect in our circuit analyses, for simplicity. Subthreshold Conduction (Skip) If we consider the ideal current-voltage relationship for the n-channel MOSFET biased in the saturation region, we have, from Equation (3.2(b)), f Taking the square root of both sides of the equation, we obtain

45 45 From Equation (3.11), we see that v as plotted in Figure GS i D is a linear function of Figure 3.23 Plot of i D versus v GS for a MOSFET biased in the saturation showing subthreshold conduction. Experimentally, a subthreshold current exists even for v GS V TN. Also plotted in Figure 3.23 are experimental results, which show that when v GS is slightly less than V TN, the drain current is not zero. This current is called the subthreshold current. The effect may not be significant ( 重要的 ) for a single device, but if thousands or millions of devices on an integrated circuit are biased just slightly below the threshold voltage, the power supply current will not be zero but may contribute ( 貢獻 ) to significant power dissipation in the integrated circuit. One example of this is the Dynamic ( 動態 ) Random ( 隨機 ) Access ( 存取 ) Memory (DRAM) to be described in Chapter 16. In this text, for simplicity we will not specifically consider the subthreshold current.

46 46 However, when an MOSFET in a circuit is to be turned off, the proper ( 適當的 ) design of the circuit must involve biasing the device at least a few tenths of a volt below the threshold voltage to achieve true cutoff. * Breakdown Effects Several possible breakdown effects may occur in a MOSFET. For instances, the drain-to-substrate pn junction may break down if the applied drain voltage is too high and avalanche multiplication occurs, as described before in Chapter 1. Another breakdown mechanism, called punch-through ( 穿透 ), may become significant as the size of the device becomes smaller. Punch-through occurs when the drain voltage is large enough for the depletion region around the drain to extend completely through the channel to the source terminal. This effect also causes the drain current to increase rapidly with only a small increase in drain voltage. In addition to the above breakdown relating to the drain or source terminal of an MOSFET, the gate terminal may also play a role ( 角色扮演 ) in the breakdown effects. 100/12/27 甲, 乙 This happens if the electric field in the oxide becomes large enough, breakdown can occur in the oxide, which can lead to catastrophic ( 大災禍的 ) failure. In silicon dioxide, the electric field at breakdown is on the 6 order of 6 10 V/cm, which, to a first approximation, is given by E V / t. ox G ox A gate voltage of approximately 30 V would produce breakdown in an oxide with a thickness of t ox =500 A.

47 47 However, a safety margin ( 餘地, 邊 ) of a factor of 3 is common, which means that the maximum safe gate voltage for t ox= 500 A would be 10 V. It is noted that a safety margin ( 餘地 ) is necessary ( 必需的 ) for the design, since there may be defects ( 缺點, 瑕疵 ) in the oxide that lower the breakdown field. 101/12/20 甲, 乙 Temperature Effects Both the threshold voltage and conduction parameter K n are functions of temperature. The magnitude of the threshold voltage V TN decreases with increase of temperature, which means that the drain current increases with temperature at a given V GS. However, the conduction parameter K n is a direct function of the inversion carrier mobility, which decreases as the temperature increases. Since the temperature dependence of mobility is larger than that of the threshold voltage, the net effect of increasing temperature is a decrease in drain current at a given V GS. This particular result provides a negative feedback ( 回授 ) condition in power MOSFETs. A decreasing value of K n inherently ( 與生俱來的 ) limits the channel current and provides stability for a power MOSFET. 99/12/16 只上一節 103/01/ 學年第一學期結束 104/05/12 甲, 乙 3.2 MOSFET DC Circuit Analysis 102 學年第二學期開始 Objective: Understand and become familiar with the dc analysis and design techniques of MOSFET circuits.

48 48 In the last section, we considered the basic MOSFET characteristics and properties. We now analyze and design the dc biasing of MOS transistor circuits. The dc biasing of MOSFETs introduced in this chapter is an important part of the design of amplifiers to be discussed in the next chapter. Note that in most of the circuits presented in this chapter, resistors are used in conjunction ( 共同, 連同 ) with the MOS transistors. However, in a real MOSFET integrated circuit, the resistors are generally replaced ( 取代 ) by other MOSFETs, so the circuit is composed ( 組成 ) entirely ( 完全地 ) of MOS devices. This is because that, in general, a MOSFET device requires a smaller area than a resistor. As we go through ( 審閱 ) the chapter, we will begin to see how this is accomplished ( 完成的 ) and as we finish the text, we will indeed ( 真正地 ) analyze and design circuits containing only MOSFETs. For simplicity, in the dc analysis of MOSFET circuits, we can use the ideal current voltage equations listed in Table 3.l in Section 3.1. That is, K n ' n K W, 2 L ' K n = n C ox; K p ' p K W, 2 L ' p K = p C ox.

49 49 There are various MOSFET configurations, the most basic is the common-source circuit Common-Source Circuit Figure 3.24 shows one example of this type of circuit using an n-channel enhancement-mode MOSFET. ( 畫圖 ) It is seen that the source terminal is at ground potential and is common to ( 共用 ) both the input and output portions ( 部分 ) of the circuit. ( 以 input 與 output 信號的 terminal 來判斷比較適當 ) The coupling ( 交連的 ) capacitor C C acts as an open circuit to dc but it allows the ac signal voltage to be coupled to the gate of the MOSFET. The dc equivalent circuit is shown in Figure 3.25(a). In the following dc analyses, we again use the notation for dc currents and voltages.

50 50 Figure 3.25 (a). The dc equivalent circuit of the NMOS common source circuit Since the gate current into the transistor is zero, the voltage at the gate is given by a voltage divider ( 分壓器 ), which can be written as Assuming that the gate-to-source voltage given by Equation (3.12) is greater than V TN, and that the transistor is biased in the saturation region, the drain current is The drain-to-source voltage is If the result is V DS > V DS (sat) = V GS - V TN, then the transistor is biased in the saturation region, as we initially assumed, and our analysis is correct.

51 On the other hand ( 在另一方面 ), if V DS < V DS (sat), then the transistor is biased in the nonsaturation region, and the drain current is given by the more complicated ( 複雜的 ) characteristic Equ. (3.2(a)). The power dissipated in the transistor, since there is no gate current, is simply given by 51

52 52 Figure 3.26 (a) shows a common-source circuit with a p-channel enhancement-mode MOSFET. ( 畫圖 ) It is seen that the source terminal is tied to ( 連結 )+ V DD, which becomes signal ground in the ac equivalent ciricuit. Thus, the terminology common-source applies to this circuit. Figure 3.26 (a) A PMOS common-source circuit The dc analysis is essentially ( 基本地 ) the same as for the n-channel MOSFET circuit. The gate voltage is

53 53 and the source-to-gate voltage is Assuming that V GS < V TP, or V SG > V TP, and that the device is biased in the saturation region, the drain current is given by and the source-to-drain voltage is If V SD > V SD (sat) = V SG + V TP, then the transistor is indeed biased in the saturation region, as we have assumed. However, if V SD < V SD (sat), the transistor is biased in the nonsaturation region.

54 54

55 55 2 D D D D 2 ID ID I (0.2)[(3.4)(5 7.5 I ) (25 75I I )] (8.9) 4(11.25)(1.6) I D or ma ( 不合 ) V V I R 5 (0.515)(7.5) 1.14 V. SD DD D D

56 56 As Example 3.4 illustrated, we may not know initially whether a transistor is biased in the saturation or nonsaturation region. The approach ( 方法, 步驟 ) involves making an educated guess ( 有所根據的推測 ) and then verifying ( 證明 ) that assumption. If the assumption proves incorrect, we must then change it and reanalyze the circuit. Note that in linear amplifiers containing MOSFETs, the transistors are biased in the saturation region. 97/12/22 98/12/08 98/12/12 第三次考試範圍 101/12/25 甲, 乙

57 Find R S and R D ( 畫圖 ) 57

58 58 VGS ID (4.7 k ) 5, 2 ID (0.25)( VGS 1.2). 2 GS GS 2 GS GS V GS ID (0.25)( VGS 1.2) DSQ D S D V (0.25)( V 1.2) (4.7 k) V 1.82V V, 另一為 negative. V V V I ( R R ) ( ) 3.83 V. (0.25)( ) Using the standard resistor values, we find V GS V, I ma, and V 3.83 V. In this case, the drain DQ DSQ current is within 1.2 percent of the design specifications ( I D 0.5 ma ) and the drain-to-source voltage is within 4.25 percent of the design specification ( V 4 V). DSQ

59 59 Now consider an example of a p-channel device biased with both positive and negative voltages. Specifications: The circuit to be designed is shown in Figure Design the circuit such that IDQ 100 A, VSDQ 3 V, and VRS 0.8 V. Note that V RS is the voltage across the source resistor R S. The value of the larger bias resistor, either R 1 or R 2, is to be 200 k. Find R 1, R 2, R S and R D ( 畫圖 ) available. The conduction parameter may vary by 5 percent.

60 60 Figure 3.29 Circuit configuration for Example 3.6 We may note that the design value of V 3 V > V (sat) V V V SDQ SDQ SGQ TP So that the transistor will be biased in the saturation region.

61 61 Trade-offs: If the conduction parameter K p varies by 5 percent, the quiescent drain current I DQ and the source-to-drain voltage V SDQ will change. Using the resistor values found in the previous design, we find the following: K 95 p 2 V SGQ I DQ V SDQ A/ V 1.416V 98.0 A 3.04V A/ V 1.385V A 2.962V 5% 1.14% 2% 1.33% Comments: We may note that the variation in the Q-point values is smaller than that the variation in K p. Including the resistor R S tends to ( 傾向 ) stabilize the Q-point. 98/12/10 只上一節 103/02/20 甲乙

62 3.2.2 Load Line and Modes of Operation 104/05/12 甲乙 The load line is helpful in visualizing ( 想像, 顯現 ) the region ( 區域 ) in which the MOSFET is biased. Consider again the common-source circuit shown in Figure 3.25(b). ( 畫圖 ) 62 Figure 3.25 (b). The NMOS circuit for Ex. 3.3, showing current and voltage values. Writing a Kirchhoff s voltage law (KVL) equation around the drain-source loop results in the following load line equation (3.14). It is seen that the load line equation shows the linear relationship between the drain current I D and drain-to-source voltage V. DS Figure 3.31 shows the V DS (sat) characteristic for the transistor described in Example 3.3 (Figure 3.25(b)). The load line is given by

63 63 or and is also plotted in the figure. ( 畫圖 ) Figure 3.31 Transistor characteristics, V DS (sat) curve, load line, and Q-point for the NMOS common-source circuit in Figure 3.25(b). The two end points of the load line are determined in the usual ( 通例的 ) manner. That is, if i D = 0, then V DS =5V; if V DS = 0, then i D = 5/20 = 0.25mA. The Q-point of the transistor is given by the dc drain current (0.1 ma) and drain-to-source voltage (3V), and it is always on the load line, as shown in the figure. Also shown in Figure 3.31 are some other transistor characteristics, such as the cutoff ( 切斷 ) point and the

64 transition ( 轉變 ) point. If the gate-to-source voltage V GS is less than V TN, the drain current is zero and the transistor is in cutoff. As the gate-to-source voltage becomes just greater than V TN, the transistor turns on and is biased in the saturation region. As V GS increases, the Q-point moves up the load line. The transition point is the boundary ( 邊界 ) between the saturation and nonsaturation regions and is defined as the point where V DS = V DS (sat) = V GS - V TN As V GS increases above the transition point value, the transistor becomes biased in the nonsaturation region. 64

65 65 Figure 3.25(b). Solving the quadratic ( 二次的 ) equation, we find that V GS - V TN 1.35 V= V DS (Sat) Therefore, V 2.35 V, and GS 2 I (0.1)(2.35 1) ma. ( 看 Fig. 3.31) D Problem-Solving Technique: MOSFET DC Analysis Analyzing the dc response of a MOSFET circuit requires knowing the bias condition (saturation or nonsaturation) of the transistor. In some cases, the bias condition may not be obvious ( 明顯的 ), which means that we have to ( 必須 ) guess the bias condition, then analyze the circuit to determine if we have a solution consistent ( 一致的 ) with our initial guess. To do this, we can: 1. Assume that the transistor is biased in the saturation region, in

66 which case V GS > V TN, i D > 0, and VDS V DS (sat). 2. Analyze the circuit using the saturation current-voltage relations. 3. Evaluate the resulting bias condition of the transistor: If the assumed parameter values in step 1 are valid, then the initial assumption is correct; V < V TN, then the transistor is probably cutoff, and if If GS V DS < DS V (sat), the transistor is likely ( 可能的 ) biased in the nonsaturation region. 4. If the initial assumption is proved incorrect ( 不正確的 ), then a new assumption must be made and the circuit reanalyzed. Step 3 must then be repeated. 97/12/25, 100/12/29 甲, 乙 Additional MOSFET Configurations: DC Analysis In addition to ( 除了 ) the basic common-source circuit just considered, that are biased with the basic four-resistor configuration, there are various ( 各式各樣的 ) other MOSFET circuit configurations. However, MOSFET integrated circuit amplifiers are generally biased with constant current sources. The following example drmonstrates this technique using an ideal current source 66 Specifications: The circuit configuration to be designed is shown in Figure 3.32 (a). Design the circuit such that the quiescent values are I 250 A and V 2.5 V. DQ D

67 67 ' Assume K n varies by 5 percent. Find V GS, V DS and R D ( 畫圖 ) Figure 3.32 (a) NMOS common-source circuit with a constant-current source and (b) equivalent dc circuit. Solution: The dc equivalent circuit is shown in Figure 3.32(b). Since vi 0, the gate is at ground potential and there is no current through R. We have that I I 250 A. G Q DQ

68 68 Trade-offs: Note that even if ' n K changes, the drain current remains ' 2 constant (constant current biasing). For 76 Kn 84 A/V, the variation in V GSQ is V GSQ V and the variation in V DSQ is V DSQ V. The variation in V DSQ is 0.87 percent even with a 5 percent variation in K n. This stability effect is one advantage ( 優點 ) of using constant current biasing. ' 103/02/25 甲乙 n-channel Enhancement-Load Device An enhancement-mode MOSFET connected in a configuration such as that shown in Figure 3.34 can be used as a nonlinear

69 resistor. A transistor with this connection is called an enhancement load device. Since the transistor is an enhancement mode device, V GS > V > 0. TN 69 Figure 3.34 Enhancement-mode NMOS device with the gate connected to the drain Also, for this circuit, V DS = V GS > V DS (sat) = V GS -V TN, ( V TN >0) which means that the transistor is always biased in the saturation region. Thus, the i D versus V DS characteristics can be written as Figure 3.35 shows a plot of Equation (3.21) for the case when K = 1 ma/ V and V TN n 2 =1 V. ( i D versus v DS )

70 70 Figure 3.35 Current-voltage characteristics of an enhancement load device If an enhancement load device is connected in a circuit with another MOSFET in the configuration shown in Figure 3.36, the circuit can be used as an amplifier (Analog circuits) or as an inverter in a digital logic circuit. ( 畫圖 )

71 71 Figure 3.36 Circuit with enhancement-load device and NMOS driver The load device, M L, is always biased in the saturation region, and the transistor M D, called the driver transistor, can be biased in either the saturation or nonsaturation region, depending on the value of the input voltage. We use the following example to address ( 說明 ) the dc analysis of this circuit for dc input voltages applied to the gate of M. 98/12/22 104/05/19 甲乙 Example 3.9 D The transistor in the circuit shown in Figure 3.36 have parameters V = V 1 V, TND 2 TNL KnD 2 50 A / V and KnL 10 A / V. Also assume nd nl 0. (The subscript D applies to the driver transistor and the subscript L applies to the load transistor.) Determine V O for V I =5 V and V I =1.5 V.

72 72

73 73 Computer Simulation: The voltage transfer characteristics of the NMOS inverter with enhancement load shown in Figure 3.36 were obtained by a PSpice analysis. These results are shown in Figure As the input voltage decreases from its high state, the output voltage increases, charging ( 充電 ) and discharging ( 放電 ) capacitances in the transistors. The current in the circuit goes to zero when the driver transistor is cutoff. This occurs when V I VGSD VTN 1 V. At this point, the output voltage is V O=4 V. Since there is no current, the capacitances cease ( 停止 ) charging and discharging so the output voltage can not get to the full V DD=5 V value. The maximum output voltage is V O (max)= VDD VTNL =5-1=4 V. (From Figure 3.35, it is seen that when i 0 V V 1 V.) DL DSL TN is a linear function of input voltage as we will see in Equ 3.24.

74 74 Figure 3.37 Voltage transfer characteristics of NMOS inverter with enhancement load device 100/01/03 甲, 乙 97/12/30 第一學期期末考 (98/01/11) 範圍 101/12/27 甲, 乙 In summary: VI 1V, M D cut off; 1 V I 2.25V, both M L and M D in saturation, V O is a linear function of V I ; 2.25 V I 5V, M L in saturation, M D in nosaturation, V O is a nonlinear function of V I. In the circuit shown in Figure 3.36, we can determine the transition point for the driver transistor M D that separates ( 分開 ) the saturation and nonsaturation regions. The transition point is determined by the equation Since the drain currents in the two transistors are equal, by using the saturation drain current relationship for the driver transistor, we have

75 75 or Again, noting that V GSD= V I and V GSL = V DSL taking the square root, we have = VDD- V O, and At the transition point, we can define the input voltage as V I = V It and the output voltage as V Ot = V DSD (sat) = V It - V TND. K nd ( V It V TND ) ( V DD V Ot V TNL ) K nl K nd ( V It V TND ) ( V DD V It V TND V TNL ) K nl Thus, the input voltage at the transition point is If we apply Equation (3.25) to the previous example, we can show that our initial assumptions were correct (1 50 /10) 4 ( ) V It / n-channel Depletion Load Device An n-channel depletion-mode MOSFET can also be used as a loas device. Consider the depletion-mode MOSFET with the gate and V.

76 76 source connected together shown in Figure 3.38(a). The current voltage characteristics are shown in Figure 3.38(b). Figure 3.38 (a) Depletion-mode NMOS device with the gate connected to the source and (b) current-voltage characteristics The transistor may be biased in either the saturation or nonsaturation regions. The transition point is also shown on the plot. Note that the threshold voltage of the n-channel depletion -mode MOSFET is negative so that V DS (sat) is positive. A depletion load device can be used in conjunction with another MOSFET, as shown in Figure 3.39, to create a circuit that can be used as an amplifier or as an inverter in a digital logic circuit.

77 77 Figure 3.39 Circuit with depletion-load device and NMOS driver In this case, both the load device M L and driver transistor M D may be biased in either the saturation or nonsaturation region, depending on the value of the input voltage. ( 畫圖 ) We will perform the dc analysis of this circuit for a particular dc input voltage to the gate of the driver transistor. 100/01/04 Consider the circuit shown in Figure Let VDD 5 V and assume transistor parameters of : V I high VO VDSD low VDSL VDD VO high. 以前說明過 V DS low or V GS high 則假設 non-saturation; V DS

78 high or V GS low 則假設 saturation. Thus, 78 Circuit with depletion load in Figure 3.39 were obtained using a PSpice analysis. These results are shown in Figure 3.40.

79 For an input voltage less than 1 V, the driver cut off and the output voltage is V V 5 V. ( 與前例 enhancement load 4 V 不同 ) O DD 79 Figure 3.40 Voltage transfer characteristics of NMOS inverter with depletion load device In summary: VI 1 V, both M L and M D are cut off, V O = VDD 5 V; 1 V I 1.9 V, M D in saturation, M L in nosaturation; VI 1.9 V, both M L and M D in saturation, no change in V I can cause great change in V O ; VI 1.9 V, M D in nonsaturation, M L in saturation, V O is low. 104/05/26 甲乙

80 p-channel Enhancement Load Device A p-channel enhancement-mode transistor can also be used as a load device to form a complementary MOS (CMOS) inverter. The term complementary implies that both n-channel and p-channel transistors are used in the same circuit. The CMOS technology is used extensively ( 廣泛地 ) in both analog and digital electronic circuits. Figure 3.41shows one example of a CMOS inverter, in which the NMOS transistor is used as the amplifying device, or the driver, and the PMOS device is the load, which is referred to as an active load. 80 Figure 3.41 Example of CMOS inverter This configuration is typically used in analog applications. In another configuration, the two gates are tied together and form the input. This configuration will be discussed in detail in Chapter 16. As with the previous two NMOS inverters, the two transistors shown in Figure 3.41 may be biased in either the saturation or nonsaturation region, depending on the value of the input

81 voltage. The voltage transfer characteristic is most easily determined from a PSpice analysis. (Skip) 81 For the circuit shown in Figure 3.41, assume transistor parameters of VTN 1 V, VTP 1 V, and Kn KP. Also assume VDD 5 V and VG 3.25 V. Solution: The voltage transfer characteristics are shown in Figure 3.42, In this case Figure 3.42 Voltage transfer characteristics pf CMOS inverter in Fifure 3.41.

82 Comment: In this example, the source-to-gate voltage of the PMOS device is VSG 1.75 V. The effective resistance looking into the drain of the PMOS device is then relatively large. This is a desirable characteristics for an amplifier, as we will see in the next chapter. * 98/2/26 100/1/8 學期末考至此 100/02/24 99 第二學期開始上 98/2/26 101/01/07 第一學期末考至此 101/02/23 99 第二學期開始上 102/01/05 第一學期末考至此 102/02/ 第二學期開始上 3.3 Basic MOSFET Applications: Switch, Digital Logic Gate, and Amplifier Objective: Examine three applications of MOSFET circuits: a switch ( 開闢, 交換 ) circuit, digital logic circuit, and an amplifier circuit. MOSFETs may be used to switch currents, voltages, and power; perform ( 執行 ) digital logic functions; and amplify ( 放大 ) small time-varying signals. In this section, we will examine the switching properties of an NMOS transistor, analyze a simple NMOS transistor digital logic circuit, and discuss how the MOSFET can be used to amplify small signals NMOS Inverter ( 當 switch 用 ) The MOSFET can be used as a switch in a wide variety of ( 廣泛多樣的 ) electronic applications. The transistor switch provides an advantage ( 優點 ) over mechanical ( 機械 ) switches in both speed and reliability ( 可靠度 ). The transistor switch considered in this section is also called an inverter ( 反相器, 逆變器 ). 82

83 83 Figure 3.45 shows the n-channel enhancement-mode MOSFET inverter circuit. ( 畫圖 ) Figure 3.45 NMOS inverter circuit If v I < V TN, the transistor is in cutoff and i D =0. There is no voltage drop across R D, and the output voltage is v O = V DD. Also, since i D = 0, no power is dissipated in the transistor. If vi V TN, the transistor is on and initially ( i D 小 v O 大 ) is biased in the saturation region, since v DS > v GS - V TN. As the input voltage v I increases, i D increases, vds VDD id RD decreases, and the transistor eventually ( 最後 ) becomes biased in the nonsaturation region. When v I = V DD, the transistor is biased in the nonsaturation region, v O reaches a minimum value, and i D reaches a maximum value. The drain current i D and the output voltage v O are given by and i D = K n[ 2( v I V TN ) v O - 2 O v ] (3.26)

84 v = V i R, (3.27) O DD D D where v O = v DS and v I = v GS. 103/02/27 甲乙 84 Design Example 3.12 The load in the inverter circuit Figure 3.45 is a coil ( 線圈 ) of an electromagnetic ( 電磁 ) that Find (W/L) and Specifications. Since V (min) V i R (max) 10 (0.5)(10) 5 V. DS DD D D ( v (max) V i R (min) 10 (0.5)(8) 6 V). DS DD D D

85 Digital Logic Gate 100/1/6 學期結束只上一節 For the above inverter circuit in Figure 3.45, when the input v I is low and approximately zero volts, the transistor is cut off, and the output v O is high and equal to V DD. When the input v I is high and equal to V DD, the transistor is biased in the nonsaturation region and the output v O reaches a low value. Since the input voltages v I will be either high or low, we can analyze the circuit in terms of dc parameters. Now consider the case when a second transistor is connected in parallel, and two inputs, V 1 and V 2, are applied as shown in Figure ( 畫圖 ) Figure 3.46 A two-input NMOS NOR logic gate

86 If the two inputs are zero (low), both M 1 and M 2 are cut off, and V O =5V (high). When V 1 = 5V and V 2 = 0, the transistor M 1 turns on, and M 2 is still cut off, Transistor M 1 is biased in the nonsaturation region, and V O reaches a low value. If we reverse ( 顛倒 ) the input voltages such that V 1 = 0 and V 2 = 5V, then M 1 is cut off and M 2 is biased in the nonsaturation region. Again, V O is at a low value. If both inputs are high, at V 1 = V 2 = 5V, then both transistors are biased in the nonsaturation region and V O is low. Table 3.2 shows these various conditions for the circuit in Figure In a positive-logic system, these results indicate that this circuit performs the NOR logic function, and, it is therefore called a two-input NOR logic circuit. 86 It is noted that in actual NMOS logic circuits, the resistor D R is replaced by another NMOS transistor.

87 87 Consider the circuit shown in Figure 3.46 with circuit and transistor parameters 5 V 2 O 0.1[2(5 0.8) VO VO] 20 2 VO VO VO 2 O VO 5 2[8.4 ] 2V (17.8) 40 V O 4 2 ( 另一解為 8,61 V 不符 )

88 88 and ID1 ID2 IR / ma. ( V (sat) V V V. DS GS TN VDS VO VDS (sat) ) This example and discussion illustrates ( 説明 ) that MOS transistors can be configured ( 型塑 ) in a circuit to perform logic functions. It will be seen in Chapter 16 that most MOS logic gate circuits are fabricated ( 製造 ) by using CMOS, which means designing circuits with both n-channel and p-channel transistors and no resistors. 98/12/ MOSFET Small-Signal Amplifier The MOSFET, in conjunction with ( 結合 ) other circuit elements, can amplify small time varying signals. Figure 3.47(a) shows the MOSFET small-signal amplifier, which is a common-source circuit in which a time-varying signal is coupled to the gate through a coupling capacitor. ( 畫圖 ) Figure 3.47(b) shows the transistor characteristics and the load line. ( 畫圖 ) Note that the load line, vds VDD id RD, is determined for v = 0. (dc load line) i

89 89 Figure 3.47 (a) An NMOS common-source circuit with a time-varying signal coupled to the gate and (b) transistor characteristics, load line, and superimposed sinusoidal signals We can establish a particular Q-point on the load line by designing the ratio of the bias resistors R 1 and R 2. If we assume that v i = Vi sin t, the gate-to-source voltage v GS

90 will have a sinusoidal signal superimposed ( 置於.. 之上 ) on the dc quiescent value V GSQ. As the gate-to-source voltage v GS changes over time, the Q-point will move up and down the line, as indicated in the figure. Moving up and down the load line translates into ( 轉變為 ) a sinusoidal variation ( 變化 ) in the drain current i D and in the drain-to-source voltage v DS, i.e., v O. ( v GS 變化 i D 與 v DS v 的變化 ) = O The variation in output voltage v O can be larger than the input signal voltage v i, which means the input signal is amplified. The actual signal gain depends on both the transistor parameters and the circuit element values. In the next chapter, we will develop an equivalent circuit for the transistor used to determine the time-varying small-signal gain and other characteristics of the circuit. 103/03/04 甲乙 3.4 Constant-Current Biasing 104/06/02 甲乙 Objective: Investigate current biasing of MOSFET devices. As was described before and shown in Figure 3.32, a MOSFET can be biased with a constant-current source I Q. 90

91 91 Figure 3.32(a) Bias with a constant current source The gate-to-source voltage of the transistor in this circuit can then adjust itself to correspond to ( 對應 ) the current I Q. ( 使 operating 穩定不會受 parameter 變化影響太大 ) We can implement the constant current source by using MOSFET devices. The circuits shown in Figures 3.49(a) and 3.49(b) are a first step toward this design. ( 畫圖 ) [3.49(a) 用 NMOS, 3.49(b) 用 PMOS]

92 92 Figure 3.49 (a) NMOS current mirror and (b) PMOS current mirror In Figure 3.49(a), the transistors M 2 and M 3 form a constant current source, called current mirror ( 鏡子 ), and are used to bias the NMOS transistor M 1. Similarly, the transistors M B and M C in Figure 3.49(b) form a current mirror and are used to bias the PMOS transistor M. The operation and characteristics of these circuits are demonstrated ( 證明 ) in the following two examples. A

93 93 Objective: Analyze the circuit shown in Figure 3.49 (a). Determine the bias current I Q1, the gate-to-source voltages of the transistors, V, VGS 2 VGS 3 M. ( GS1 ), and the drain-to-source voltage of 1 ( VGS 3 VDS 3 VDS 3(sat) VGS 3 VTN 3 ) (Assume M 2 is in saturation) ( 可見 IQ1 IREF1)

94 94 ( V 1 V V) S GS ( VDS1 VGS1 VTN 1 (sat) V. V (sat) V V V. DS 2 GS 2 TN 2 VDS 2 VS1 V 1.29 ( 2.5) 1.21 V. VDS 2 VDS 2 (sat) M 2 is in saturation. We now consider a current mirror in which the bias current and reference current are not equal. 98/03/02 100/02/24 Objective: Design the circuit shown in Figure 3.49 (b) to provide a bias current of I A. (Find VSGC V V V ) SDC SGC Q SGB, V SGA, ( / ) B W L, V SDA, V SDB,

95 95 ( RD 8 k ) V (sat) V V, but V 0, Thus SDC SGC TPC SDC SGC SDC (sat) V V V So, C TPC M is always biases in saturation (Assume M B is in saturation) ' k p W DB Q B SGB TPB I I 2 ( ) ( V V ) 2 L 2

96 96 Assume M A is in saturation V V V. SA SGA VSDA VSA IQ2RD V (0.15)(8) ( 3) 2.95 V. Since V (sat) V V V, A SDA SGA TPA M is indeed in saturation V (sat) V V V. SDB SGB TPB

97 V V V V. SDB B SA M is also in saturation 97 The constant-current source ( 前例的 I REF ) can also be implemented ( 實現 ) by using MOSFETs as shown in Figure ( 畫圖 ) Figure 3.50 Implementation of a MOSFET constant-current source The three transistors M 2, M 3, and M 4 form the current source. The transistors M 3 and M 4 are each connected in a diode-type configuration ( 外形 ), and they establish a reference current. We noted in the last section that this diode-type connection

98 98 implies that the transistor is always biased in the saturation region. Therefore, transistors M 3 and M 4 are biased in the saturation region, and M 2 is assumed to be biased in the saturation region. In this configuratopn, the resulting gate-to-source voltage on M 3 is applied to M 2, i.e., VGS 2 VGS 3, and V GS2 establishes the bias current I Q. Since the reference current is the same in transistors M 3 and M, we can write 4 We also know that Solving Equation (3.29) for V GS 4 and substituting ( 代替 ) the result into Equation (3.28) yields GS 4 GS3 2 2 n3( GS3 TN3) n4( GS3 TN 4) 2 n4 ( GS3 TN3) 2 n3 ( GS3 TN 4) V V V k V V k V V V k V V k V V V k V V ( V V V ) n4 GS3 TN3 GS3 TN 4 kn3 k k V (1 ) V ( V V ) n4 n4 GS3 TN3 TN 4 kn3 kn3

99 99 Since V GS3 = V GS 2, the bias current is 102/02/21 甲, 乙 101/02/23 甲, 乙 For the circuit shown in Figure 3. 50, the transistor parameters are 2 2 Kn1 0.2 ma/v, Kn2 Kn3 Kn4 0.1 ma/v, and TN1 V VTN 2 VTN3 VTN 4 1V. V, VGS 3 VGS 2, V GS1, Q DS (Find GS4 V V V.) DS 4 DS3 GS 4 求 V DS1需要 R D, let I, V 2, V DS1, R 20 k. ( 課本沒有 ) D V 0 V V 2.5 ( 5) 2.5 V. GS 4 GS3 Since M 3 and M 4 are identical transistors, V GS3 should be one-half of the bias voltage. That is V V V V. GS 2 GS3 GS 4 2.5

100 Assume M 2 is in saturation Q n2 GS 2 TN I k ( V V ) (0.1)(2.5 1) ma. Assume M 1 is in saturation 100 V V 2.06 V V S1 GS1 D2 The drain-to- source voltage on M 2 is VDS 2 VS1 V V V (sat) V V V. DS1 GS1 TN1 DS Q D S V 1 V I R V 1 5 (0.2)(20) ( 2.06) 2.56 V. Therefore, M 1 is also in saturation.

101 3.5 Multistage MOSFET Circuits Objective: Consider the dc biasing of multistage or multitransistor circuits. For an amplifier, the general parameters of interest are amplification factor for current, voltage or power, input resistance, and output resistance. In most applications, a single-transistor amplifier will not be able to meet ( 符合 ) the combined ( 結合的 ) specifications of the above parameters. For example, the voltage gain we require may exceed ( 超過 ) that which can be obtained by a single-transistor circuit. For this purpose, we can use multistage ( 多階級 ) amplifiers by connecting single-transistor amplifier circuits in series, or cascade ( 串接 ), as shown in Figure ( 說明 ) 101 Figure 3.51 Generalized two-stage amplifier By doing this, we may either increase the overall ( 全部的 ) small-signal voltage gain, or provide an overall voltage gain greater than 1, with a very low output resistance. It is noted that the overall voltage gain may not simply be the product ( 積 ) of the individual ( 個別的 ) amplification factors. Loading effects ( 負載效應 ), in general, need to be taken into account ( 考慮 ). There are many possible multistage configurations; we will

102 102 examine ( 檢視 ) two types to understand the analysis required Multitransistor Circuit: Cascade Configuration The circuit shown in Figure 3.52 is a cascade of a common-source amplifier followed by a source-follower (Common-drain) amplifier. We will show in the next chapter that the common-source amplifier provides a small-signal voltage gain and the source-follower has a low output impedance. ( 畫圖 ) Figure 3.52 Common-source amplifier in cascade with source follower Consider the circuit shown in Figure 3.52 with transistor parameters

103 (Find R 1, 2 Sol: 先求 R S2 R, R S1, R D1, S2 R ) VS 2 V VDSQ V. S2 S2 DQ2 R ( V V ) / I ( 1 5) / k. Assume transistors are biased in the saturation region V 求 GS2 I K ( V V ) DQ2 n2 GS 2 TN ( V GS 2 1.2) VG 2 VGS 2 VS V. R 求 D1 R D1 V VG k I 0.2 DQ1 VS1 VD1 VDSQ V. 求 R S1 R S1 VS1 V k. I 0.2 DQ1 To find R 1 and R 2, note that RR R 1 2 i R1 R2 100 k R R. 1 2

104 Assume M 1 is in saturation 求 V GS1 104 V V V GS1 G1 S1 VG1 VGS1 VS V. V V G R1 R2 V V I R V R R 5 R R R R R R R k R k DS1 GS1 TN1 R R ( 1 2) 2 V (sat) V V V. V (sat) V V V. DS 2 GS 2 TN 2 So, both M 1 and M 2 are in saturation Multitransistor Circuit: Cascode ( 疊接 ) Configuration 100/03/01, 98/03/05 103/03/06 Figure 3.53 shows a cascode circuit with n-channel MOSFETs.

105 In this configuration, transistor M 1 is connected in a common-source configuration and M 2 is connected in a common-gate configuration. ( 畫圖 ) The advantage of this type of circuit is a higher frequency response, which is discussed in a later chapter. 105 Figure 3.53 NMOS Cascode circuit 102/2/26 二甲, 乙 For the circuit shown in Figure 3.53, the transistor parameters are VTN1 (Find R 1, R 2, R 3, R D ) Note that the current through R 1, R 2, and 3 R is

106 I 1 V R R R ma. 106 VS1 IDQRS V (0.4)(10) 5 1 V. VGS 2 VGS V. Then, VG1 VGS 1 VS V. V I R But G1 1 3 V R G 1 3 I (300) 54.4 k 5 The voltage at the source of 2 M, V S2, is Then, VG 2 VGS 2 VS V. But VG 2 V I1R1 V V R G 2 1 I1 ( )(300) 95.6 k 5 R2 300 R1 R k To find R D, the voltage at the drain of M 2, V D2, is

107 107 V (sat) V V V. DS GS TN We will encounter ( 面對 ) many more examples of multitransistor and multistage amplifiers in later chapters, such as the differential and operational amplifier in Chapter 11 and 13, respectively. 3.6 Junction Field-Effect Transistor (JFET) Objective: Understand the operation and characteristics of the pn junction FET (JFET) and the Schottky barrier junction FET (MESFET, Skip), and understand the dc analysis techniques of JFET and MESFET circuits. The two general categories ( 類型 ) of junction field-effect transistor (JFET) are the pn junction FET, or pn JFET, and the metal-semiconductor field-effect transistor (MESFET), which is fabricated with a Schottky barrier junction. The current in a JFET is through a semiconductor region known as the channel, with ohmic contacts at each end. The basic transistor action is the modulation ( 調變 ) of the channel conductance by an electric field perpendicular to the channel. Since the modulating electric field is induced ( 感應 ) in the space-charge region of a reverse-biased pn junction or

108 108 Schottky barrier junction, the field is a function of the gate voltage. Modulation of the channel conductance by the gate voltage modulates the channel current. JFETs were developed before MOSFETs, but the applications and uses of the MOSFET have far surpassed ( 超越 ) those of the JFET. One reason is that the voltages applied to the gate and drain of a MOSFET are the same polarity (both positive or both negative), whereas the voltages applied to the gate and drain of most JFETs must have opposite polarities. Since the JFET is used only in specialized ( 特殊的 ) applications, our discussion will be brief ( 簡短的 ) pn JFET and MESFET Operation 104/06/04 甲乙 pn JFET A simplified cross section of a symmetrical n-channel pn JFET is shown in Figure ( 畫圖 ) Figure 3.54 Cross section of a symmetrical n-channel pn junction field-effect transistor

109 109 When the voltages are applied as shown, in the n-region channel between the two p-regions, majority carrier electrons flow from the source to the drain terminal; thus, the JFET is called a majority-carrier device. The two gate terminals shown in Figure 3.54 are connected to form a single gate. In a p-channel JFET, the p- and n-regions are reversed from those of the n channel device, and holes flow in the channel from the source to the drain. The current direction and voltage polarities in the p-channel JFET are reversed from those in the n-channel device. Also, the p-channel JFET is generally a lower frequency device than the n-channel JFET, because hole mobility is lower than electron mobility. Figure 3.55(a) shows an n-channel JFET with zero volts applied to the gate. ( 畫圖 )

110 110

111 111 Figure 3.55 Gate-to-channel space-charge regions and current-voltage characteristics for small drain-to-source voltages and for: (a) zero gate voltage, (b) small reverse-biased gate voltage, and (c) a gate voltage that achieves pinchoff It is seen that if the source is at ground potential, and if a small positive drain voltage is applied, a drain current i D is produced between the source and drain terminals. 所以 n-channel 是正電壓 ( vds 0), 而 p-gate 是零電壓, 因此 pn is reverse biased, 所以有 space charge region ( 紅色區域 ). Since the n-channel acts essentially ( 基本上 ) as a resistance, the i D versus v DS characteristic for small v DS values is approximately linear, as shown in the figure. Now if a voltage is applied to the gate of a pn JFET, the channel conductance changes. Consider the case that a negative gate voltage is applied to the n-channel pn JFET in Figure 3.55, the gate-to-channel pn junction becomes more reverse biased ( 比 vgs 0). The space-charge region widens ( 變寬 ), the channel region narrows ( 變窄 ), the resistance of the n-channel increases, and the slope of the i D versus v DS curve, for small v DS, decreases, as shown in Figure 3.55(b).

112 112 If a larger negative gate voltage is applied, the reverse-biased gate-to-channel space-charge region completely ( 完全地 ) fills the channel region, as shown in Figure 3.55 (c). This condition is known as pinchoff ( 緊閉 ). Since the depletion region isolates ( 隔離 ) the source and drain terminals, the drain current at pinchoff is essentially zero, as shown in the i D versus v DS curves of Figure 3.55(c) Thus, the current in the channel is controlled by the gate voltage. This mechanism ( 機械裝置 ) in which the current in one part of the device is controlled by a voltage in another part of the device is the basic transistor action. 102/03/05 甲 乙 We now study the drain current i D versus the drain-source voltage v DS characteristics of the pn JFET for a fixed ( 固定的 ) gate voltage v GS ( 前面考慮 v GS 變化 ). Note that the pn JFET is a normally on, or depletion mode, device, i.e., a voltage must be applied to the gate terminal to turn the device off. Consider the situation in which the gate voltage v GS =0, and the drain voltage v DS changes, as shown in Figure 3.56(a), the red area is the depletion region. ( 畫圖 )

113 113 As the drain voltage increases (positive), the gate-to-channel pn junction becomes more reverse biased near the drain terminal, and the space-charge region widens, extending ( 延伸 ) farther into the channel. The channel acts essentially ( 基本地 ) as a resistor, and the effective ( 有效的 ) channel resistance increases as the space-charge region widens. Thus, the slope of the i D versus v DS characteristic decreases, as shown in Figure 3.56(b). ( 畫圖 )

114 114 The effective channel resistance now varies along the channel, and, since the channel current must be constant, the voltage drop through the channel becomes dependent on position. ( 每個位置的 conductance 不一樣, 所以斜率不一樣 ) If the drain voltage increases further, the condition shown in Figure 3.56(c) can result ( 產生 ). ( 畫圖 )

115 115 Figure 3.56 Gate-to-channel space-charge regions and current-voltage characteristics for zero-gate voltage and for: (a) a small drain voltage, (b) a large drain voltage, and (c) a drain voltage that achieves pinchoff at drain voltage In this case, the channel is pinched off at the drain terminal. Any further increase in drain voltage will not increase the drain current, as the i D v DS characteristic shown in this figure. The drain voltage at pinch off is v DS (sat). For v DS > v DS (sat), the JFET is biased in the saturation region, and the drain current for this ideal case is independent of v DS. MESFET 101/03/01 甲, 乙 103/03/11 甲, 乙 In the MESFET, the gate junction is a Schottky barrier junction, instead of a pn junction. Although MESFETs can be fabricated in silicon, they are usually associated with ( 與.. 相關 ) gallium arsenide or other compound semiconductor materials. A simplified cross section of a GaAs MESFET is shown in Figure ( 畫圖 ) (Skip to pp. 118 end)

116 116 Figure 3.57 Cross section of an n-channel MESFET with a semi-insulating substrate In this figure, a thin ( 薄的 ), epitaxial layer of GaAs is used for the active region; the substrate is a very high resistivity GaAs material, referred to as a semi-insulating substrate. The advantages of these devices include: higher electron mobility in GaAs, hence smaller transit ( 通過 ) time and faster response ( 反應 ); decreased parasitic ( 寄生的 ) capacitance ( 電容會影響元件反應速度 ) and a simplified fabrication process, resulting from the semi-insulating GaAs substrate. In the MESFET in Figure 3.57, a reverse-bias gate-to-source voltage (negative for the gate) induces a space-charge region under the metal gate, which modulates the channel conductance, as in the case of the pn JFET. If a negative applied gate voltage is sufficiently large, the space-charge region will eventually ( 最後地 ) reach the substrate. Again, pinchoff will occur. Also, the device shown in the figure is a depletion mode device, since a gate voltage must be applied to pinch off the channel,

117 that is, to turn the device off. There is another type of MESFET, in which the channel is pinched off even at v GS =0, as shown in Figure 3.58(a). ( 畫圖 ) For this MESFET, the channel thickness is smaller than the zero-biased space-charge width. 117

118 Figure 3.58 Channel space-charge region for an enhancement-mode MESFET for (a) v GS =0, (b) v GS V TN, and (c) v V GS TN To open a channel, the depletion region must be reduced; that is, a forward-biased voltage must be applied to the gate semiconductor junction. When a slightly ( 稍微的 ) forward-bias voltage is applied, the depletion region extends just to the width of the channel as shown in Figure 3.58(b). The threshold voltage is the gate-to-source voltage required to create ( 打開 ) the pinchoff condition. The threshold voltage for this n-channel MESFET is positive, in contrast to ( 對比於 ) the negative threshold voltage of the n-channel depletion-mode device. If a larger forward-bias voltage is applied, the channel region opens, as shown in Figure 3.58(c). The applied forward-bias gate voltage is limited to a few tenths of a volt before a significant ( 重要的 ) gate current occurs. This device is an n-channel enhancement-mode MESFET. Enhancement-mode p-channel MESFETs and enhancement -mode pn JFETs have also been fabricated. The advantage of enhancement-mode MESFETs is that circuits can be designed in which the voltage polarities on the gate and drain are the same. However, the output voltage swing ( 擺動 ) of these devices is quite small. * Current Voltage Characteristics 98/12/31 100/03/03 The circuit symbols for the n-channel and p-channel JFETs are 118

119 119 shown in Figure 3.59, along with the gate-to-source voltages and current directions. ( 畫圖 ) Figure 3.59 Circuit symbols for: (a) n-channel JFET and (b) p- channel JFET The ideal current voltage characteristics, when the transistor is biased in the saturation region, are described by where I DSS is the saturation current when v GS =0, and V P is the pinchoff voltage. Non saturation region 的電流公式複雜且與製造參數有關. The current voltage characteristics, i.e., i D versus v DS for n-channel and i D versus v SD for p-channel JFETs, are shown in Figures 3.60(a) and 3.60(b), respectively. (Depletion mode) ( 畫圖 )

120 120 Figure 3.60 Current-voltage characteristics for: (a) n-channel JFET and (n) p-channel JFET Note that the pinchoff voltage V P for the n-channel JFET is negative and the gate-to-source voltage v GS is usually negative (Depletion mode); therefore, the ratio v GS / V P is positive.

121 Similarly, the pinchoff voltage V P for the p-channel JFET is positive and the gate-to-source voltage v GS must be positive, and therefore the ratio v GS / V P is positive. For the n-channel device, the saturation region occurs when v v (sat), where DS DS v DS (sat) = v GS -V P (3.33) [ V P 為負 ( 大負 ), v GS 為負 ( 小負 ) v DS (sat) 為正 ] For the p-channel device, the saturation region occurs when v v (sat), where SD SD v SD (sat) = v SG [ P + V P = VP- v GS (3.34) V 為正 ( 大正 ), v SG 為負 ( 小負 ) 或 v GS 正 ( 小正 ) v SD (sat) 為正 ] The transfer characteristics of i D versus v GS (Equation 3.32), when the transistor is biased in the saturation region, for the n-channel and p-channel JFET are shown in the following figure (a) and (b), respectively. ( 課本沒有 ) 121 Figure Drain current versus gate-to-source voltage characteristics

122 for the transistor biased in the saturation region (a) n-channel JFET and (b) p-channel JFET 122 As in the case of the MOSFET, the i D versus v DS characteristic for the JFET may have a nonzero slope beyond the saturation point (finite output resistance). This nonzero slope can be described through the following equation: The output resistance r o is defined as

123 123 Using Equation (3.35), we find that or This finite output resistance will be considered again when we discuss the small-signal equivalent circuit of the JFET in the next chapter. Enhancement-mode GaAs MESFETs can be fabricated with current versus voltage characteristics much like those of the enhancement-mode MOSFET. That is, the ideal drain current i D for enhancement-mode MESFET biased in the saturation region and nonsaturation region are desccribed by the following Equations (3.38(a)) and (3.38(b)), respectively. (Skip) In the above two equations, K n is the conduction parameter and V TN is the threshold voltage, which in this case is equivalent to the pinchoff voltage. Note that for an n-channel enhancement-mode MESFET, the threshold voltage is positive. 101/03/06 甲, 乙

124 3.6.3 Common JFET Configurations: dc Analysis There are several common JFET circuit configurations. We will look at a few of these and illustrate the dc analysis and design of such circuits by using examples. 104/06/09 甲, 乙 124 Consider the circuit shown in Figure 3.61(a) with transistor parameters ( 畫圖 ) (Find R 1, R 2, R S and R D ) Figure 3.61 (a) An n-channel JFET circuit with voltage divider biasing and (b) the n-channel JFET circuit for Example 3.20

125 125 From Figure 3.61(b), the voltage at the source terminal is V S I R 5 5(0.5) V. D S Assume IG 0 ( 因為 Gate 是 reverse bias, 此和 MOS 的 Gate 是 insulator 狀況不一樣 ) I 1 V V ma. R R V I R ( 5) (0.1) R V. G 1 2 2

126 To find R D 126 V IDRD VDS VS V VDS VS RD 0.5 k. I 5 D The parameters of the transistor in the circuit shown in Figure 3.63 are IDSS 2.5 ma, VP 2.5 V, and 0, the transistor is biased with a constant current source. ( 畫圖 ) (Find V SD, ID IQ)

127 127 Figure 3.63 A p-channel JFET circuit biased with a constant-current source Solution: From Figure 3.63 we can write the dc drain current as Then, V 1 V 1 V S SG GS

128 3.22 (Skip) 128 Consider the circuit shown in Figure 3.65(a). The transistor parameters are: (Find R 1, R 2, and R S ) ( 畫圖 ) Figure 3.65 (a) An n-channel enhancement-mode MESFET circuit and (b) the n-channel MESFET circuit for Example 3.22 From Figure 3.65(b), the voltage at the drain is

129 (Gate current =0 是假設 ) 129

130 Design Application: Diode Thermometer with an MOS Transistor (Skip) Objective: Incorporate ( 編入 ) an MOS transistor in a design application that enhances ( 加強 ) the simple diode thermometer design discussed in Chapter 1. Figure 1.47 Circuit of diode thermometer Specifications: The electronic thermometer is to operate over a temperature range of 0 to 100 F. Design Approach: The output diode voltage developed in the diode thermometer in Figure 1.47 is to be applied between the gate source terminals of an NMOS transistor to enhance the voltage over the temperature range. The NMOS transistor is to be held at a constant temperature. Choices: Assume an n-channel, depletion-mode MOSFET is available with the parameters V 1 V. TN ' K n =80 A/ V 2, W/L = 10, and Solution: From the design in Chapter 1, the diode voltage for T 1

131 and T 2, V D1 and V D2 are related by 131 For T 1 =300, it was found that V D1= V, replacing T 2 by T and V D2 by V D, we have where T is in kelvins. Consider the circuit shown in Figure 3.69 ( 畫圖 ). We assume that the diode is in a variable temperature environment ( 環境 ) while the rest ( 其餘的 ) of the circuit is held at room temperature. Figure 3.69 Design application circuit to measure output voltage of diode versus temperature From the circuit, we see that V GS V, where V D is the diode = D

132 132 voltage and not the drain voltage. We want the MOSFET biased in the saturation region, so Then the output voltage V O can be expressed as ' Kn W O D D D D TN V V I R 15. R ( V V ) 2 L By using the above two equations, the diode current and output voltage can be written as 2 and O D D D V V I R 15 4( V 1) (V) From Chapter 1, we have the following data and the corresponding circuit response shown below. 2 Substituting the values of V D in the above table into the formulae of I D and V O expressied above, we obtain the circuit response shown below:

133 133 Comment: Figure 3.70(a) shows the diode voltage V D versus temperature and Figure 3.70(b) now shows the output voltage V versus temperature from the MOSFET circuit. O