Design of 14 GHz Frequency Synthesizer using Dielectric Resonator Oscillator. spring Microwave and MM-wave Lab.

Transcription

1 Design of 14 GHz Frequency Synthesizer using Dielectric Resonator Oscillator spring 2015 Microwave and MM-wave Lab. Sogang University

2 Outline 1. Dielectric resonator 2. Design of VCO 3. Theoretical and experimental results

3 1. Dielectric Resonator - Disc type general characteristics - low loss, high Q, high dielectric constant, and excellent temperature characteristics - the resonant mode of disc resonator ; mode Fig 1. E- and H-field distributions.

4 coupling to the microstrip line - magnetic coupling in nature Zo d Zo q q Zo P Fig. 2. DR coupled to a line. Fig 3. Equivalent circuit of Fig. 2. Characterization using lumped element circuit is more convenient.

5 Derivation of lumped element equivalent circuit ; Cr Rr Zo i 2 i 1 V Lr + V 1 - Lm Zo Fig. 4. lumped element equivalent circuit of DR coupled to a line. L r ; equivalent inductance C r ; equivalent capacitance L m ; equivalent mutual inductance R r ; equivalent resistance

6 unloaded Q of the dielectric resonator(dr) ω (1) Derivation of the input impedance of the DR loaded to a line : use KVL ; ω ω (2) rearrange (3) as ω ω ω (3) ω ω ω (4)

7 from (2) and (4) ω ω ω ω ω ω ω (5) near the resonant frequency (5) reduces to ω ω ω (6) since ω, the denominator of (6) is modified as ω ω ω ω ω ω (7)

8 near the resonant frequency, ω ω Δω for small Δω ; (8) (7) ; ω ω ωω ωω Δωω Δωω Δω (8) Δω finally (6) becomes ω ω Δω ω Δω ω Δω ω (9) ω Δω ω ω ω Δωω (10)

9 define Δωω, then (10) becomes ω (11) at the resonant frequency the impedance is derived as ω (12)

10 based on the (12) the equivalent circuit is simplified as R C Z o L Z o Fig. 5. the final equivalent circuit the values of equivalent circuit parameters are calculated from ω ω (13)

11 2. Design of VCO - circuit having negative resistance characteristics positive feedback required ; 1) transistors having high transconductance and low flicker noise characteristics 2) series feedback with stub : at the source & drain terminal Fig. 6. FET as a 3-port device.

12 three port S-parameters are given as and from (14)~(18) ; Γ Γ (14) Γ Γ (15) Γ Γ (16) Γ (17) Γ (18) Γ Γ Γ Γ Γ Γ Γ Γ (19)

13 negative resistance obtained when ; 1) by changing (stub impedance at the gate) 2) by changing (stub impedance at the drain) 3) by changing both and very efficient when FET has low transconductance

14 - design of VCO varactor diode must be used to change the resonant frequency of the resonator(dr + varactor diode) Fig 8. tuning of DR using varactor. Fig 9. equivalent circuit of resonator.

15 the impedance seen at transmission line which is terminated by a varactor diode ; ω (20) is inductive for λ λ ; resulting equivalent circuit as given in Fig. 9. is derived as ω ω (21) when ω ω further approximation leads to ω ω ω (22)

16 change in due to the change in varactor tuning voltage does not affect the value of. adjust the length in such a way that does not change much. narrow tuning range is expected and the phase noise added by the varactor is minimized. change the gap between DR and the coupling line( ) ; for increased the loose coupling resulted. small loading effect ; excellent phase noise characteristics however, narrow tuning range is also expected.

17 3. Theoretical and experimental results - VCO design negative resistance characteristics obtained by inserting stubs at drain as well as source 3-port S-parameters of ATF at 14.2 GHz ; derived input reflection coefficient ; Γ Γ Γ Γ Γ Γ Γ Γ

18 Fig. 9. gain of ATF 36077

19 - Designed DRO at GHz Var VAR Eqn VAR2 w35=2.54 mm w70=0.87 mm l35=4.28 mm l70=4.43 mm Var VAR Eqn VAR1 Zo=50 wo=0.94 mm lo=3.75 mm Var Eqn VAR VAR6 Lo=((2*pi*f)^2*Co)^(-1) Co=Qu/(2*pi*f*Ro) Ro=2*B*Zo B=2.35 f=14.2e9 TL70 Qu=4290 W=wo L=1 mm R R4 R=50 Ohm PRLC PRLC1 R=Ro L=Lo C=Co HARMONIC BALANCE HarmonicBalance HB2 Freq[1]=14.5 GHz Order[1]=5 NLNoiseMode=yes NoiseFreqPlan= NLNoiseStart=1.0 khz NLNoiseStop=10.0 MHz NLNoiseStep= NLNoiseDec=2 PhaseNoise=yes NoiseNode[1]="vout" NoiseNode[2]="PhaseRe" OscPortName="Osc1" TL83 TL7 OscPort Osc1 W=wo W=wo V= L=7 mm L=4 mmz=50 Ohm NumOctaves=2 Steps=10 FundIndex=1 MaxLoopGainStep= Var Eqn VAR VAR7 wt=0.94 mm DC DC1 DC MLOC TL91 W=1 mm L=5.4 mm TL90 W=1 mm L=1.0 mm MSub MSUB MSub1 H=0.381 mm Er=3.0 Mur=1 Cond=1.0E+50 Hu=1.0e+033 mm T=0.018 mm TanD= Rough=0 mm MTEE Tee6 W1=0.2 mm W2=0.2 mm W3=0.2 mm MLOC TL6 W=wo L=0.3 mm MTEE TL10 Tee12 TL5 ph_hp_atf36077_ W=wo W1=wo W=wo X2 L=0.5 mm W2=wo L=4 mm W3=wo TL71 MTEE Tee17 W=1 mm TL73 L=1.0 mm W1=0.2 mm W2=0.2 mm W=0.2 mm W3=0.2 mm L=3.5 mm TL72 W=0.2 mm L=3.5 mm MRSTUB Stub4 Wi=0.2 mm L=2.2 mm Angle=60 MSTEP Step4 TL74 W1=wo W=wo W2=0.2 mm L=2 mm R R5 R=33 Ohm TL13 W=wo L=2 mm MSTEP Step2 W1=wo W2=0.2 mm TL14 W=0.2 mm L=3.5 mm V_DC SRC4 Vdc=3.5 V MRSTUB Stub2 TL12 Wi=0.2 mm L=2.2 mm W=0.2 mmangle=60 L=3.5 mm MTEE Tee5 TL81 W1=wo W=wo W2=wo L=1.0 mm W3=0.2 mm R R2 R=10 Ohm DC_Block DC_Block1 vout R TL82 R3 R=50 Ohm W=wo L=1.0 mm V d =3.8 V and I d =23 ma ; Fig. 10 Designed DRO.

20 from the linear analysis ; 2.0 m2 freq= 14.15GHz mag(s(1,1))=1.798 m2 200 m1 freq= 14.15GHz phase(s(1,1))= mag(s(1,1)) phase(s(1,1)) m freq, GHz freq, GHz Fig. 11 Simulated results(linear). loop gain > 1 and the phase = 0 o

21 Fig. 12 Schematic layout of the DRO. electrical length and gap d are important parameters no analytic results are available for determining d the electrical length depends on the active device characteristics - no general rule available

22 Harmonic Balance Analysis Results output power ; 7.55 dbm Fig. 13 simulated characteristics. phase 100 khz ; dbc/hz

23 measured characteristics Fig. 14. phase 100 khz. Fig. 15 phase 10 khz.

24 Fig. 16 Designed DRO

25 Design VCDRO using DR and varactor diode Fig. 17. Layout of VCO.

26 Table 1 VCDRO characteristics as a function of (d1=2 mm, d2=5 mm). (mm) tuning range(mhz) phase noise(@100 khz) 0.35 λ dbc/hz 0.25 λ dbc/hz Table 2 VCDRO characteristics as a function of gaps( =6.7 mm). (mm) (mm) tuning range phase noise (MHz) (@100 khz) dbc/hz dbc/hz dbc/hz final results : =6.7 mm, =3.5 mm and =3.5 mm tuning range : 3 MHz phase noise : -113 dbc/hz

27 Designed VCDRO ; R R5 R=33 Ohm Var Eqn Var Eqn VAR VAR2 w35=2.54 mm w70=0.87 mm l35=4.28 mm l70=4.43 mm VAR VAR1 Zo=50 wo=0.94 mm lo=3.75 mm Var VAR Eqn VAR6 Lo=((2*pi*f)^2*Co)^(-1) Co=Qu/(2*pi*f*Ro) Ro=2*B*Zo B=3 f=12.63e9 Qu=120 MSub DC DC1 DC MSUB MSub1 H=0.381 mm Er=3.0 Mur=1 Cond=1.0E+50 Hu=1.0e+033 mm T=0.018 mm TanD= Rough=0 mm OscTest OscTest1 Port_Number=1 Z=50 Ohm Start=2 GHz Stop=20 GHz Points=301 HARMONIC BALANCE HarmonicBalance HB2 Freq[1]=12.63 GHz Order[1]=5 NLNoiseMode=yes NoiseFreqPlan= NLNoiseStart=1.0 khz NLNoiseStop=10.0 MHz NLNoiseStep= NLNoiseDec=2 PhaseNoise=yes NoiseNode[1]="vout" NoiseNode[2]="PhaseRe" OscPortName="Osc1" MLOC TL91 W=1 mm L=9 mm TL90 W=1 mm L=1.0 mm MLOC TL6 W=wo L=0.3 mm MTEE Tee6 W1=0.2 mm W2=0.2 mm W3=0.2 mm TL13 W=wo L=2 mm MSTEP Step2 W1=wo W2=0.2 mm TL14 W=0.2 mm L=3.5 mm V_DC SRC4 Vdc=4 V MRSTUB Stub2 Wi=0.2 mm TL12 L=2.2 mm Angle=60 W=0.2 mm L=3.5 mm R R4 TL70 PRLC PRLC1 R=50 Ohm W=wo R=Ro L=1 mm L=Lo C=Co TL83 W=wo L=7 mm TL7 W=wo L=3.8 mm OscPort Osc1 V= Z=50 Ohm NumOctaves=2 Steps=10 FundIndex=1 MaxLoopGainStep= Var VAR Eqn VAR7 wt=0.94 mm MTEE Tee12 TL10 TL5 MTEE Tee5 TL81 DC_Block DC_Block1 ph_hp_atf36077_ W1=wo W=wo W=wo W1=wo W=wo X2 W2=wo L=1 mm L=2.0 mm W2=wo L=1.0 mm W3=wo W3=0.2 mm TL71 MTEE W=1 mm Tee17 L=1.0 mm W1=0.2 mm W2=0.2 mm W3=0.2 mm TL72 W=0.2 mm L=3.5 mm R MSTEP R2 TL73 Step4 TL74 R=10 Ohm W=0.2 mm W1=wo W=wo MRSTUB L=3.5 mm W2=0.2 mm L=2 mm Stub4 Wi=0.2 mm L=2.2 mm Angle=60 vout TL82 W=wo L=1.0 mm R R3 R=50 Ohm

28 Simulated characteristics of VCDRO at 12 GHz ; 10 m6 freq= 12.73GHz plot_vs(dbm(hb.vout), HB.freq)=9.861 m6 m7 noisefreq= 10.00kHz plot_vs(pnfm, noisefreq)= dbm(hb.vout) pnfm m freq, GHz noisefreq, KHz

29 Measured results of VCDRO : phase noise characteristics ; khz offset, -108 khz offset

30 tuning range of VCDRO 3 MHz measured tuning characteristics :