Exam II. EECS150 - Digital Design Lecture 19 Review. Finite State Machines (FSMs) Lecture 9 - Finite State Machines 1

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1 EECS150 - Digital Design Lecture 19 Review March 31, 2005 John Wawrzynek Exam II Midterm Exam next week Tuesday (4/5) In class Closed book/notes Covers lectures 9 (FSMs) through lecture 17 (memory 1) Exam held in 125 Cory Today: Highlights from lectures 9-17 I will mention most important points from each lecture Exam may cover subtopics not mentioned today Use homework as a guide to the type of questions on the exam Spring 2005 EECS150 - Lec19-review Page 1 Spring 2005 EECS150 - Lec19-review Page 2 Lecture 9 - Finite State Machines 1 Finite State Machines (FSMs) FSM circuits are a type of sequential circuit: output deps on present and past inputs effect of past inputs is represented by the current state February 15, 2005 Behavior is represented by State Transition Diagram: traverse one edge per clock cycle. Spring 2005 EECS150 - Lec19-review Page 3 Spring 2005 EECS150 - Lec19-review Page 4 1

2 Review of Design Steps: Formal Design Process 1. Specify circuit function (English) 2. Draw state transition diagram 3. Write down symbolic state transition table 4. Write down encoded state transition table 5. Derive logic equations 6. Derive circuit diagram FFs for state CL for NS and OUT One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding? Simple design procedure. Circuit matches state transition diagram (example next page). Often can lead to simpler and faster next state and output logic. Why not do this? Can be costly in terms of FFs for FSMs with large number of states. FPGAs are FF rich, therefore one-hot state machine encoding is often a good approach. Spring 2005 EECS150 - Lec19-review Page 5 Spring 2005 EECS150 - Lec19-review Page 6 Even Parity Checker Circuit: One-hot encoded FSM Circuit generated through direct inspection of the STD. Lecture 10 - Finite State Machines 2 February 17, 2005 In General: FFs must be initialized for correct operation (only one 1) Spring 2005 EECS150 - Lec19-review Page 7 Spring 2005 EECS150 - Lec19-review Page 8 2

3 Moore Machine input value STATE [output values] FSM Recap Mealy Machine input value/output values STATE Solution A Moore Machine output function only of PS maybe more states (why?) synchronous outputs no glitches one cycle delay full cycle of stable output FSM Comparison Solution B Mealy Machine output function of both PS & input maybe fewer states asynchronous outputs if input glitches, so does output output immediately available output may not be stable long enough to be useful (below): Both machine types allow one-hot implementations. If output of Mealy FSM goes through combinational logic before being registered, the CL might delay the signal and it could be missed by the clock edge. Spring 2005 EECS150 - Lec19-review Page 9 Spring 2005 EECS150 - Lec19-review Page 10 General FSM Design Process with Verilog Implementation Design Steps: 1. Specify circuit function (English) 2. Draw state transition diagram 3. Write down symbolic state transition table 4. Assign encodings (bit patterns) to symbolic states 5. Code as Verilog behavioral description Use parameters to represent encoded states. Use separate always blocks for register assignment and CL logic block. Use case for CL block. Within each case section assign all outputs and next state value based on inputs. Note: For Moore style machine make outputs depent only on state not depent on inputs. Spring 2005 EECS150 - Lec19-review Page 11 Mealy Machine ) if (rst) ps <= ZERO; else ps <= ns; in) case (ps) ZERO: if (in) begin out = 1 b1; ns = ONE; else begin out = 1 b0; ns = ZERO; ONE: if (in) begin out = 1 b0; ns = ONE; else begin out = 1 b0; ns = ZERO; default: begin out = 1 bx; ns = default; FSMs in Verilog Moore Machine ) if (rst) ps <= ZERO; else ps <= ns; in) case (ps) ZERO: begin out = 1 b0; if (in) ns = CHANGE; else ns = ZERO; CHANGE: begin out = 1 b1; if (in) ns = ONE; else ns = ZERO; ONE: begin out = 1 b0; if (in) ns = ONE; else ns = ZERO; default: begin out = 1 bx; ns = default; Spring 2005 EECS150 - Lec19-review Page 12 3

4 Universal Shift-register Lecture 11 - Shifters & Counters February 24, 2003 Spring 2005 EECS150 - Lec19-review Page 13 Spring 2005 EECS150 - Lec19-review Page 14 Plain shift register: Shifter with shift-enable input Shift Registers QuickTime and a TIFF (Uncompressed) decompressor are needed to see this picture. QuickTime and a TIFF (Uncompressed) decompressor are needed to see this picture. Verilog: assign OUT = Q[0]; (posedge ) if (shiftenable) Q <= {IN; Q[3:1]}; else Q <= Q; FPGA FFs have clock-enable (CE), therefore muxes are not needed. State Transition Diagram: Controller using Counters Assume presence of two binary counters. An i counter for the outer loop and j counter for inner loop. START CE CLK RST counter TC TC is asserted when the counter reaches it maximum count value. CE is count enable. The counter increments its value on the rising edge of the clock if CE is asserted. IDLE CE i,ce j RST i TC i OUTER <outer contol> CE i,ce j RST j TC i START INNER <inner contol> CE i,ce j TC j TC j Spring 2005 EECS150 - Lec19-review Page 15 Spring 2005 EECS150 - Lec19-review Page 16 4

5 Extra combinational logic can be added to terminate count before max value is reached: Example: count to 12 Odd Counts Alternative: load 4 4-bit binary counter TC Synchronous Counters How do we ext to n-bits? Extrapolate c + : d + = d abc, e + = e abcd a + b + c + d + a b c Has difficulty scaling (AND gate inputs grow with n) d CE TC a + b + c + d + a b c CE is count enable, allows external control of counting, TC is terminal count, is asserted on highest value, allows cascading, external sensing of occurrence of max value. d Spring 2005 EECS150 - Lec19-review Page 17 Spring 2005 EECS150 - Lec19-review Page 18 Synchronous Counters Ring Counters CE a + b + c + d + TC one-hot counters 0001, 0010, 0100, 1000, 0001, What are these good for? How does this one scale? Delay grows α n a b c Generation of TC signals very similar to generation of carry signals in adder. Parallel Prefix circuit reduces delay: d q 3 q 2 q 1 D Q D Q D Q D Q S R S R S R S R reset Self-starting version: q 0 log 2 n q 3 q 2 q 1 q 0 D Q D Q D Q D Q log 2 n Spring 2005 EECS150 - Lec19-review Page 19 Spring 2005 EECS150 - Lec19-review Page 20 5

6 Music waveform Digital Audio Lecture 12 Project Description March 1, 2005 Spring 2005 EECS150 - Lec19-review Page 21 A series of numbers is used to represent the waveform, rather than a voltage or current, as in analog systems. Discrete time: regular spacing of sample values in time. Most digital audio system use 44.1KHz (consumer) sample rate or 48KHz (professional) sample rate. Lower frequency would limit the maximum representable frequency content. (Human hearing max is 20KHz) Digital: All inputs/outputs and internal values (signals) take on discrete values (not analog). Most digital audio systems use 16-bit values (64K possible values for any point in waveform). Using much fewer than 16 bits generates noticeable noise from distortion. Spring 2005 EECS150 - Lec19-review Page 22 sound source (microphone) Analog / Digital Conversion sample clock Analog to Digital Converter (ADC) Digital to Analog Converter (DAC) sample clock power amplifier 26, 46, 51, 55, 51, 26, 46, 51, 55, 51, Digital System compression recording processing synthesis decompression playback Converters are used to move from/to the analog domain. ADC & DAC often combined in a single chip called CODEC (coder/decoder). Other types of CODECs perform other functions (ex: video conversion, audio compression/decompression). Spring 2005 EECS150 - Lec19-review Page 23 Digital Audio Data-rates 44.1K samples/sec x 2 (stereo) x 16 bits/samples = 1.4 Mbit/sec = 176,400 Bytes/sec 1 minute 10MByte total Relatively small storage devices has prompted the development and application of many compression algorithms for music and speech: Typically compression ratios of MP3: 32Kbits/sec - 320Kbits/sec (factor of 4x to 44x) These techniques are lossy; information is lost. However the better ones (MP3 & AAC for example) used techniques based on characteristics of human auditory perception to drop information of little importance. In our project, uncompressed audio will be used. Sufficient network bandwidth to support multiple streams of audio. Much simpler hardware design. Uncompressed audio is often referred to as PCM (pulse code modulation). (.wav files in windows) Spring 2005 EECS150 - Lec19-review Page 24 6

7 switch host host Local Area Network (LAN) Basics switch switch host to router or gateway host host A LAN is made up physically of a set of switches, wires, and hosts. Routers and gateways provide connectivity out to other LANs and to the internet. Ethernet defines a set of standards for datarate (10/100Mbps, 1/10Gbps), and signaling to allow switches and computers to communicate. Most Ethernet implementations these days are switched (point to point connections between switches and hosts, no contention or collisions). Information travels in variable sized blocks, called Ethernet Frames, each frame includes preamble, header (control) information, data, and error checking. We usually call these packets. Preamble MAC Payload CRC (8 bytes) header Preamble is a fixed pattern used by receivers to synchronize their clocks to the data. Link level protocol on Ethernet is called the Medium Access Control (MAC) protocol. It defines the format of the packets. Ethernet Medium Access Control (MAC) MAC protocol encapsulates a payload by adding a 14 byte header before the data and a 4-byte cyclic redundancy check (CRC) after the data. A 6-byte destination address, specifies either a single recipient node (unicast mode), a group of recipient nodes (multicast mode), or the set of all recipient nodes (broadcast mode). A 6-byte source address, is set to the ser s globally unique node address. Its common function is to allow address learning which may be used to configure the filter tables in switches. A 2-byte type field, identifies the type of protocol being carried (e.g. 0x0800 for IP protocol). The CRC provides error detection in the case where line errors result in corruption of the MAC frame. In most applications a frame with an invalid CRC is discarded by the MAC receiver. Ethertypes for EECS150 project: 0x0101: audio packets 0x0102: LCD packets (picked from the range of experimental type codes to avoid potential conflict. One way transmission only. All packets will be broadcasted Spring 2005 EECS150 - Lec19-review Page 25 Spring 2005 EECS150 - Lec19-review Page 26 Usual case is that MAC protocol encapsulates IP (internet protocol) which in turn encapsulates TCP (transport control protocol) with in turn encapsulates the application layer. Each layer adds its own headers. Other protocols exist for other network services (ex: printers). When the reliability features (retransmission) of TCP are not needed, UDP/IP is used. Gaming and other applications where reliability is provided at the application layer. Protocol Stacks MAC Layer 2 IP Layer 3 TCP Layer 4 Layer 5 application layer ex: http MAC Layer 2 IP Layer 3 UDP Layer 4 Layer 5 Streaming Ex. Mpeg4 Spring 2005 EECS150 - Lec19-review Page 27 application level interface Standard Hardware-Network-Interface MAC (MAC layer processing) Media Indepent Interface (MII) Usually divided into three hardware blocks. (Application level processing could be either hardware or software.) MAG. Magnetics chip is a transformer for providing electrical isolation. PHY. Provides serial/parallel and parallel/serial conversion and encodes bit-stream for Ethernet signaling convention. Drives/receives analog signals to/from MAG. Recovers clock signal from data input. PHY (Ethernet signal) MAG (transformer) Ethernet connection MAC. Media access layer processing. Processes Ethernet frames: preambles, headers, computes CRC to detect errors on receiving and to complete packet for transmission. Buffers (stores) data for/from application level. Application level interface Could be a standard bus (ex: PCI) or designed specifically for application level hardware. MII is an industry standard for connection PHY to MAC. Calinx has no MAC chip, must be handled in FPGA. Spring 2005 EECS150 - Lec19-review Page 28 7

8 Transistor-level Logic Circuits NAND gate NOR gate Lecture 14 - CMOS March 8, 2005 Note: out = 0 iff both a OR b = 1 therefore out = (a+b) Again pfet network and nfet network are duals of one another. Other more complex functions are possible. Ex: out = (a+bc) Spring 2005 EECS150 - Lec19-review Page 29 Spring 2005 EECS150 - Lec19-review Page 30 Transmission Gate Transmission gates are the way to build switches in CMOS. In general, both transistor types are needed: nfet to pass zeros. pfet to pass ones. The transmission gate is bi-directional (unlike logic gates). 2-to-1 multiplexor: c = sa + s b Pass-Transistor Multiplexor Does not directly connect to Vdd and GND, but can be combined with logic gates or buffers to simplify many logic structures. Switches simplify the implementation: a b s s c Spring 2005 EECS150 - Lec19-review Page 31 Spring 2005 EECS150 - Lec19-review Page 32 8

9 Tri-state Buffers Tri-state buffers are used when multiple circuits all connect to a common bus. Only one circuit at a time is allowed to drive the bus. All others disconnect. Transistor-level Logic Circuits Positive Level-sensitive latch: Bidirectional connections: Busses: Latch Transistor Level: Positive Edge-triggered flip-flop built from two level-sensitive latches: Spring 2005 EECS150 - Lec19-review Page 33 Spring 2005 EECS150 - Lec19-review Page 34 Limitations on Clock Rate 1 Logic Gate Delay 2 Delays in flip-flops Lecture 15 - Timing March 10, 2005 Spring 2005 EECS150 - Lec19-review Page 35 input output t What are typical delay values? Both times contribute to limiting the clock period. Plus clock skew. What must happen in one clock cycle for correct operation? Assuming perfect clock distribution (all flip-flops see the clock at the same time): All signals connected to FF inputs must be ready and setup before rising edge of clock. Spring 2005 EECS150 - Lec19-review Page 36 D Q setup time clock to Q delay 9

10 General Model of Synchronous Circuit clock input Inverter: Gate Switching Behavior input CL reg CL reg output option feedback output In general, for correct operation: T time( Q) + time(cl) + time(setup) T τ Q + τ CL + τ setup for all paths. How do we enumerate all paths? Any circuit input or register output to any register input or circuit output. setup time for circuit outputs deps on what it connects to -Q time for circuit inputs deps on from where it comes. Spring 2005 EECS150 - Lec19-review Page 37 NAND gate: Spring 2005 EECS150 - Lec19-review Page 38 Gate Delay Gate Delay Cascaded gates: Fan-out: Vout Vin transfer curve for inverter. Spring 2005 EECS150 - Lec19-review Page 39 The delay of a gate is proportional to its output capacitance. Because, gates 2 and 3 turn on/off at a later time. (It takes longer for the output of gate 1 to reach the switching threshold of gates 2 and 3 as we add more output capacitance.) Spring 2005 EECS150 - Lec19-review Page 40 10

11 Critical Path Critical Path: the path with the maximum delay, from any input to any output. In general, we include register set-up and -to-q times in critical path calculation. What is the critical path in this circuit? D Q setup time Delay in Flip-flops clock to Q delay Setup time results from delay through first latch. Clock to Q delay results from delay through second latch. Why do we care about the critical path? Spring 2005 EECS150 - Lec19-review Page 41 Spring 2005 EECS150 - Lec19-review Page 42 CLK CLK Clock Skew (cont.) CL CLK CLK If clock period T = T CL +T setup +T Q, circuit will fail. Therefore: clock skew, delay in distribution 1. Control clock skew a) Careful clock distribution. Equalize path delay from clock source to all clock loads by controlling wires delay and buffer delay. b) don t gate clocks. 2. T T CL +T setup +T Q + worst case skew. Most modern large high-performance chips (microprocessors) control to clock skew to a few tenths of a nanosecond. Lecture 16 - Power March 15, 2005 Spring 2005 EECS150 - Lec19-review Page 43 Spring 2005 EECS150 - Lec19-review Page 44 11

12 Basics Power supply provides energy for charging and discharging wires and transistor gates. The energy supplied is stored & then dissipated as heat. P dw / dt Power: Rate of work being done w.r.t time. Rate of energy being used. Units: P = E t Watts = Joules/seconds If a differential amount of charge dq is given a differential increase in energy dw, the potential of the charge is increased by: By definition of current: V = dw / dq I = dq / dt dw dq dw / dt = = P = V I dq dt A very practical formulation! t If we would like w = Pdt total energy to know total energy Spring 2005 EECS150 - Lec19-review Page 45 Metrics How does MIPS/watt relate to energy? Average power consumption = energy / time MIPS/watt = instructions/sec / joules/sec = instructions/joule therefore an equivalent metric (reciprocal) is energy per operation (E/op) E/op is more general - applies to more that processors also, usually more relevant, as batteries life is limited by total energy draw. This metric gives us a measure to use to compare two alternative implementations of a particular function. Spring 2005 EECS150 - Lec19-review Page 46 Switching Energy: energy used to switch a node Calculate energy dissipated in pullup: Energy supplied Power in CMOS Vdd pullup network pulldown network GND 0 t 1 t E sw = 1 t P(t)dt = (V dd v) i(t)dt = 1 (V dd v) c (dv dt) dt = t 0 t 0 v 1 v 1 = cv dd dv c v dv = cv dd 1 2cV dd =1 2cV dd v 0 v 0 C Spring 2005 EECS150 - Lec19-review Page 47 i(t) 1 v(t) Vdd v(t) t 0 t0 Energy stored t1 Energy dissipated An equal amount of energy is dissipated on pulldown. Controlling Energy Consumption What control do you have as a designer? Largest contributing component to CMOS power consumption is switching power: 2 Pavg = n α avg f 1 2cavgVdd Factors influencing power consumption: n: total number of nodes in circuit α: activity factor (probability of each node switching) f: clock frequency (does this effect energy consumption?) V dd : power supply voltage What control do you have over each factor? How does each effect the total Energy? In EECS150 design projects, we will not optimize for power consumption. Spring 2005 EECS150 - Lec19-review Page 48 12

13 Standard Internal Memory Organization 2-D arrary of bit cells. Each cell stores one bit of data. Lecture 17 Memory 1 March 17, 2005 Special circuit tricks are used for the cell array to improve storage density. (We will look at these later) RAM/ROM naming convention: examples: 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words Spring 2005 EECS150 - Lec19-review Page 49 Spring 2005 EECS150 - Lec19-review Page 50 Read Only Memory (ROM) Simply form of memory. No write operation needed. Functional Equivalence: Connections to Vdd used to store a logic 1, connections to GND for storing logic 0. Column MUX in ROMs and RAMs: Controls physical aspect ratio Important for physical layout and to control delay on wires. In DRAM, allows time-multiplexing of chip address pins address decoder bit-cell array Full tri-state buffers are not needed at each cell point. In practice, single transistors are used to implement zero cells. Logic one s are derived through precharging or bit-line pullup transistor. Spring 2005 EECS150 - Lec19-review Page 51 Spring 2005 EECS150 - Lec19-review Page 52 13

14 Cascading Memory Modules (or chips) Example: assemblage of 256 x 8 ROM using 256 x 4 modules: example: 1K x * ROM using 256 x 4 modules: each module has tri-state outputs: Memory Components Types: Volatile: Random Access Memory (RAM): DRAM "dynamic" SRAM "static" Non-volatile: Read Only Memory (ROM): Mask ROM "mask programmable" EPROM "electrically programmable" EEPROM "erasable electrically programmable" FLASH memory - similar to EEPROM with programmer integrated on chip Spring 2005 EECS150 - Lec19-review Page 53 Spring 2005 EECS150 - Lec19-review Page 54 Volatile Memory Comparison The primary difference between different memory types is the bit cell. SRAM Cell DRAM Cell word line word line Dual-ported Memory Internals Add decoder, another set of read/write logic, bits lines, word lines: Example cell: SRAM WL 2 WL 1 bit line bit line Larger cell lower density, higher cost/bit No refresh required Simple read faster access Standard IC process natural for integration with logic bit line Smaller cell higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read longer access time Special IC process difficult to integrate with logic circuits dec a dec b cell array address ports data ports r/w logic r/w logic b 2 b 1 b 1 b 2 Repeat everything but cross-coupled inverters. This scheme exts up to a couple more ports, then need to add additional transistors. Spring 2005 EECS150 - Lec19-review Page 55 Spring 2005 EECS150 - Lec19-review Page 56 14