Unit-1. Power Semiconductor Devices

Transcription

1 Unit-1 Power Semiconductor Devices

2 Objectives: Create an awareness of the general nature of Power electronic equipment; The key features of the principal Power Electronic Devices; An idea about which device to choose for a particular application. Introduction Power Electronics is the art of converting electrical energy from one form to another in an efficient, clean, compact, and robust manner for convenient utilization. A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the scene it consumes less power with reduced stresses on the motor and corruption of the utility mains. Power electronics system or power electronic controller: Fig. 1.1 The block diagram of a typical Power Electronic converter The o/p from the power converter may be ac,dc (or) variable voltage and frequency. It is given to the load & feedback signal measures parameters of the load and compare with the ref. signal. The difference between the signals through the control units controls the load. Key point: Advantages of power electronic system: 1. High efficiency due low loss. 2.Fast response compare to electromechanical system 3.Long life 4.Small size and low weight 5.Lower noise & flexibility in operation

3 It is not primarily in their power handling capacities. While power management IC's in mobile sets working on Power Electronic principles are meant to handle only a few mill watts, large linear audio amplifiers are rated at a few thousand watts. The utilization of the bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best symbolizes the difference. In Power Electronics all devices are operated in the switching mode - either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3. Saturation and cutoff zones in the V CE - I C plane are avoided. In a Power electronic switching amplifier, only those areas in the V CE - I C plane which have been skirted above, are suitable. On-state dissipation is minimum if the device is in saturation (or quasi-saturation for optimizing other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch will try to traverse the active zone as fast as possible to minimize switching losses. Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier Linear operation Switching operation Active zone selected: Active zone avoided : Good linearity between input/output High losses, encountered only during transients Saturation & cut-off (negative bias) Saturation & cut-off zones avoided: poor zones linearity selected: low losses Transistor biased to operate around No concept of quiescent point quiescent point collector Transistor driven directly at base -, emitter Common emitter, Common common base modes Output transistor barely protected and load either on collector or emitter Switching-Aid-Network (SAN) and other protection to main transistor Utilisation of transistor rating of secondary importanc e Utilisation of transistor rating optimised

4 History: Power electronics and converters utilizing them made a head start when the first device the Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The necessity arose of extending the application of the SCR beyond the line-commutated mode of action, which called for external measures to circumvent its turn-off incapability via its control terminals. Various turn-off schemes were proposed and their classification was suggested but it became increasingly obvious that a device with turn-off capability was desirable, which would permit it a wider application. The turn-off networks and aids were impractical at higher powers. The Bipolar transistor, which had by the sixties been developed to handle a few tens of amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior to the SCR in its turn-off capability, which could be exercised via its control terminals. This permitted the replacement of the SCR in all forced-commutated inverters and choppers. However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor and the high base currents required to switch the Bipolar spawned the Darlington. Three or more stage Darlington s are available as a single chip complete with accessories for its convenient drive. Higher operating frequencies were obtainable with a discrete Bipolar compared to the 'fast' invertergrade SCRs permitting reduction of filter components. But the Darlington's operating frequency had to be reduced to permit a sequential turn- off of the drivers and the main transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This device also represents the first successful marriage between modern integrated circuit and discrete power semiconductor manufacturing technologies. Its voltage drive capability giving it again a higher gain, the ease of its paralleling and most importantly the much higher operating frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the MOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier device its on-state voltage is dictated by the R DS(ON) of the device, which in turn is proportional to about V DSS 2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially viable. Improvements were being tried out on the SCR regarding its turn-off capability mostly by reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol for the device. The requirement for an extremely high turn-off control current via the gate and the comparatively higher cost of the device restricted its application only to inverters rated above a few hundred KVA. The lookout for a more efficient, cheap, fast and robust turn-off-able device preceded in different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated Gate Bipolar Transistor (IGBT) basically a MOSFET driven

5 Bipolar from its terminal characteristics has been a successful proposition with devices being made available at about 4 KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET has been able to continue in the sub 10 KVA range primarily because of its high switching frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA. Subsequent developments in converter topologies especially the three-level inverter permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based converters are possible at the highest range where line-commutated or load-commutated converters were the only solution. The surge current, the peak repetition voltage and I 2 t ratings are applicable only to the thyristors making them more robust, specially thermally, than the transistors of all varieties. Presently there are few hybrid devices and Intelligent Power Modules (IPM) is marketed by some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated Gate Commutated Thyristors) of ABB which are promising at the higher power ranges. However these new devices must prove themselves before they are accepted by the industry at large. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about 2 ev that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide is the only wide band gap semiconductor among gallium nitride (GaN, E G = 3.4 ev), aluminum nitride (AlN, E G = 6.2 ev), and silicon carbide that possesses a high-quality native oxide suitable for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times higher than in silicon. This is important for high-voltage power switching transistors. For example, a device of a given size in SiC will have a blocking voltage 8 times higher than the same device in silicon. More importantly, the on-resistance of the SiC device will be about two decades lower than the silicon device. Consequently, the efficiency of the power converter is higher. In addition, SiC-based semiconductor switches can operate at high temperatures (~600 C) without much change in their electrical properties. Thus the converter has a higher reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink size. Moreover, the high frequency operating capability of SiC converters lowers the filtering requirement and the filter size. As a result, they are compact, light, reliable, and efficient and have a high power density. These qualities satisfy the requirements of power converters for most applications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offer substantially better performance. With the SCR and the pin-diodes, so called because of the sandwiched intrinsic i -layer between the p and n layers, having mostly line-commutated converter applications, emphasis was mostly on their static characteristics - forward and reverse voltage blocking, current carrying and overcurrent ratings, on-state forward voltage etc and also on issues like paralleling and series operation of the devices. As the operating speeds of the devices increased, the dynamic

6 (switching) characteristics of the devices assumed greater importance as most of the dissipation was during these transients. Attention turned to the development of efficient drive networks and protection techniques which were found to enhance the performance of the devices and their peak power handling capacities. Issues related to paralleling were resolved by the system designer within the device itself like in MOSFETS, while the converter topology was required to take care of their series operation as in multi-level converters. Classification of power semiconductor Devices: POWER SEMICONDUCTOR DEVICES UNCONTROLLED CONTROLLED RECTIFIERS ACCESSORIES REGENERATIVE NON-REGENERATIVE INTEGRATED POWER SILICON DIODES FREDS SCHOTTKY SCR BJT IGCT DIAC TRIAC MOSFET PIC Zenner GTO IGBT INTELLIGENT MOV POWER MODULES Power semiconductor device variety Types of Power Electronics Converters 1. Diode rectifiers : AC input into fixed DC output (Uncontrolled Rectifiers) 2. AC DC Converters: AC input into variable DC output 3. AC AC converters : i..ac Voltage Regulator: Convert fixed AC voltage into Variable AC voltage without changing frequency ii. Cycloconverter: Convert power at one frequency to another frequency at constant voltage level. 4. DC DC Converter DC Choppers : Fixed DC into Variable DC 5. DC AC Converter Inverter: Fixed DC input into fixed or variable dc output.

7 Power Diodes: di F /dt t 0 t 1 t 2 SNAPPY SOFT to Q1 Q2 IRM VRM

8 Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode' Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent over-current (surge rating about six times average current rating) and surge-voltage withstand capability. They have relatively large Q rr and t rr specifications. Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's, have significantly lower Q rr and t rr (~ 1.0 sec). They areavailable at high powers and are mainly used in association with fast controlled-devices as free-wheeling or DC- DC choppers and rectifier applications. Fast recovery diodes also find application in induction heating, UPS and traction. Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any Q rr.. However, they are available with voltage ratings up to a hundred volts only though current ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no competition in low voltage SPMS applications and in instrumentation. Silicon Controlled Rectifier (SCR) The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer regenerative devices. It is normally turned on by the application of a gate pulse when a forward bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot be turned off via the gate terminals especially at the extremely high amplification factor of the gate. There are two main types of SCR's. Converter grade or Phase Control thyristors These devices are the work horses of the Power Electronics. They are turned off by natural (line) commutation and are reverse biased at least for a few milliseconds subsequent to a conduction period. No fast switching feature is desired of these devices. They are available at voltage ratings in excess of 5 KV starting from about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are built with series- parallel combination of these devices. Conduction voltages are device voltage rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation components. The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years borrowing emitter shorting and other techniques adopted for the faster variety. The requirement for hard gate drives and di/dt limting inductors have been eliminated in the process.

9 Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 secs when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly used in circuits that are operated on DC supplies and no alternating voltage is available to turn them off. Commutation networks have to be added to the basic converter only to turn-off the SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time, t q of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite a few commutation networks were designed and some like the McMurray-Bedford became widely accepted. Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the basic SCR have been proposed for specific applications. The Asymmetrical thyristor is convenient when reactive powers are involved and the light activated SCR assists in paralleling or series operation. MOSFET The Power MOSFET technology has mostly reached maturity and is the most popular device for SMPS, lighting ballast type of application where high switching frequencies are desired but operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency applications, where the currents drawn by the equivalent capacitances across its terminals are small, it can also be driven directly by integrated circuits. These capacitances are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of its main terminals permit easy paralleling externally also. At high current low voltage applications the MOSFET offers best conduction voltage specifications as the R DS(ON) specification is current rating dependent. However, the inferior features of the inherent anti-parallel diode and its higher conduction losses at power frequencies and voltage levels restrict its wider application. The IGBT It is a voltage controlled four-layer device with the advantages of the MOSFET driver and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punch-through (NPT) structures. In the punch-through IGBT, a better trade-off between the forward voltage drop and turn -off time can be achieved. Punch-through IGBTs are available up to about 1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more robust than PT IGBTs particularly under short circuit conditions. However they have a higher forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably shaping the drive signal. This gives the IGBT a number of advantages: it does not require protective circuits, it can be connected in parallel without difficulty, and series connection is possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe Operating Area devoid of a Second Breakdown region.

10 The GTO The GTO is a power switching device that can be turned on by a short pulse of gate current and turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode current to be turned off. Hence there is no need for an external commutation circuit to turn it off. Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is short, thus giving it more capability for highfrequency operation than thyristors. The GTO symbol and turn-off characteristics are shown in Fig GTOs have the I 2 t withstand capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs, the critical aspects are proper design of the gate turn-off circuit and the snubber circuit. Protection of Power devices and converters Power electronic converters often operate from the utility mains and are exposed to the disturbances associated with it. Even otherwise, the transients associated with switching circuits and faults that occur at the load point stress converters and devices. Consequently, several protection schemes must be incorporated in a converter. It is necessary to protect both the Main Terminals and the control terminals. Some of these techniques are common for all devices and converters. However, differences in essential features of devices call for special protection schemes particular for those devices. The IGBT must be protected against latching, and similarly the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible turn-off-able current specification. KEYPOINT: Power semiconductor devices are commonly protected against: 1. Over-current; 2.di/dt; 3.Voltage spike or over-voltage; 4.dv/dt ; 5.Gate-under voltage; 6.Over voltage at gate; 7.Excessive temperature rise; 8.Electro-static discharge; Semiconductor devices of all types exhibit similar responses to most of the stresses, however there are marked differences. The SCR is the most robust device on practically all counts. That it has an I 2 t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal voltage, as shown in Fig This voltage is related to the current carried by the device. Further, the transistors permit designed gate current waveforms to minimise voltage spikes as a consequence of sharply

11 rising Main terminal currents. Gate resistances have significant effect on turn-on and turn-off times of these devices - permitting optimisation of switching times for the reduction of switching losses and voltage spikes. Protection schemes for over-voltages - the prolonged ones and those of short duration - are guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic voltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dt stresses, which again have similar effect on all devices, R- C or R-C-D clamps are used depending on the speed of the device. These 'snubbers' or 'switching-aid-networks', additionally minimise switching losses of the device - thus reducing its temperature rise. Gates of all devices are required to be protected against over-voltages (typically + 20 V) especially for the voltage driven ones. This is achieved with the help of Zener clamps - the zener being also a very fast-acting device. Protection against issues like excessive case temperatures and ESD follow well-set practices. Forced-cooling techniques are very important for the higher rated converters and whole environments are air-cooled to lower the ambient. KEYPOINT: MOSFET---- Highest switching speed; Easy drive features; Can be most effectively paralleled. SCR Highest voltage / current ratings; Can be protected against overcurrents with a fuse. GTO----- Gate-turn off capability with regenerative features. IGBT----- Easy drive and High power handling capability.

12 1.0 Power Semiconductor Diodes Objective: The student will be able to Draw the spatial distribution of charge density, electric field and electric potential in a step junction p-n diode. Calculate the voltage drop across a forward biased diode for a given forward current and vice-verse. Identify the constructional features that distinguish a power diode from a signal level diode. Differentiate between different reverse voltage ratings found in a Power Diode speciation sheet. Introduction: Power semiconductor diode is the power level counter part of the low power signal diodes with which most of us have some degree of familiarity. These power devices, however, are required to carry up to several KA of current under forward bias condition and block up to several KV under reverse biased condition. These extreme requirements call for important structural changes in a power diode which significantly affect their operating characteristics. These structural modifications are generic in the sense that the same basic modifications are applied to all other low power semiconductor devices (all of which have one or more p-n junctions) to scale up their power capabilities. It is, therefore, important to understand the nature and implication of these modifications in relation to the simplest of the power devices, i.e., a power semiconductor diode. 1.1 Review of Basic p-n Diode Characteristics: A p-n junction diode is formed by placing p and n type semiconductor materials in intimate contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type silicon crystal or by the opposite sequence. In an open circuit p-n junction diode, majority carriers from either side will defuse across the junction to the opposite side where they are in minority. These diffusing carriers will leave behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This region of immobile ionized atoms is called the space charge region. This process continues till the resultant electric field (created by the space charge density) and the potential barrier at the junction builds up to sufficient level to prevent any further migration of carriers. At this point the p-n junction is said to be in thermal equilibrium condition. Variation of the space charge density, the electric field and the potential along the device is shown in Fig 2.1 (a).

13 a) (b) (c) Fig 2.1: Space change density the electric field and the electric potential in side a p-n junction under (a) thermal equilibrium condition, (b) reverse biased condition,c) forward biased condition. When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition. This reverse bias adds to the height of the potential barrier. The electric field strength at the junction and the width of the space change region (also called the depletion region because of the absence of free carriers) also increases. On the other hand, free minority carrier densities (n p in the p side and p n in the n side) will be zero at the edge of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process. These two components of current together is called the reverse saturation current I s of the diode. Value of I s is independent of the reverse voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly. The diode is said to have undergone reverse break down. Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated electron in turn may repeat the process. This cascading effect (avalanche) may produce a large number of free electrons very quickly

14 resulting in a large reverse current. The power dissipated in the device increases manifold and may cause its destruction. Therefore, operation of a diode in the reverse breakdown region must be avoided. When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction. The injected minority carriers eventually recombines with the majority carries as they defuse further into the electrically neutral drift region. The excess free carrier density in both p and n side follows exponential decay characteristics. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current I F (flowing from p side to n side) which can be expressed as IF = IS exp qv/kt -1 (2.1) Where I s = Reverse saturation current ( Amps) v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzman s constant T = Temperature in Kelvin From the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn as shown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of the semiconductor body has been neglected. Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode

15 Questions for Practice: Fill in the blanks: 1. The width of the space charge region increases as the applied voltage increases. 2. The maximum electric field strength at the center of the depletion layer increases, with in the reverse voltage. 3.Reverse saturation current in a power diode is extremely sensitive to Variation. 4. Donor atoms are carrier providers in the p type and carrier providers in the n type semiconductor materials. 5. Forward current density in a diode is proportional to the life time of carriers. Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely 1.2 Construction and Characteristics of Power Diodes: As mention in the introduction Power Diodes of largest power rating are required to conduct several kilo amps of current in the forward direction with very little power loss while blocking several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in order to restrict the maximum electric field strength below the impact ionization level. Space charge density in the depletion layer should also be low in order to yield a wide depletion layer for a given maximum Electric fields strength. These two requirements will be satisfied in a lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer. Such a construction, however, will result in a device with high resistively in the forward direction. Consequently, the power loss at the required rated current will be unacceptably high. On the other hand if forward resistance (and hence power loss) is reduced by increasing the doping level, reverse break down voltage will reduce. This apparent contradiction in the requirements of a power diode is resolved by introducing a lightly doped drift layer of required thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b) shows the circuit symbol and the photograph of a typical power diode respectively.

16 (b) Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross section. To arrive at the structure shown in Fig 2.3 (c) a lightly doped n - epitaxial layer of specified width (depending on the required break down voltage) and donor atom density (N dd ) is grown on a heavily doped n + substrate (N dk donor atoms.cm -3 ) which acts as the cathode. Finally the p-n junction is formed by defusing a heavily doped (N aa acceptor atoms.cm -3 ) p + region into the epitaxial layer. This p type region acts as the anode. Impurity atom densities in the heavily doped cathode (N dk.cm -3 ) and anode (N aa.cm -3 ) are approximately of the same order of magnitude (10 19 Cm -3 ) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (N dd Cm -3 ). In a low power diode this drift region is absent. The Implication of introducing this drift region in a power diode is explained next. 1.3 Power Diode under Reverse Bias Conditions As in the case of a low power diode the applied reverse voltage is supported by the depletion layer formed at the p + n - metallurgical junction. Overall neutrality of the space change region dictates that the number of ionized atoms in the p + region should be same as that in the n - region. However, since N dd << N aa, the space charge region almost exclusively extends into the n - drift

17 region. Now the physical width of the drift region (W D ) can be either larger or smaller than the depletion layer width at the break down voltage. Consequently two type of diodes exist, (i) non punch through type, (ii) punch through type. In non-punch through diodes the depletion layer boundary doesn t reach the end of the drift layer. On the other hand in punch through diodes the depletion layer spans the entire drift region and is in contact with the n + cathode. However, due to very large doping density of the cathode, penetration of drift region inside cathode is negligible. Electric field strength inside the drift region of both these type of diodes at break down voltage is shown in Fig 2.4. Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Non-punch through type; (b) punch through type. In non-punch through type diodes the electric field strength is maximum at the p + n - junction and decrease to zero at the end of the depletion region. Where as, in the punch through construction the field strength is more uniform. In fact, by choosing a very lightly doped n - drift region, Electric field strength in this region can be mode almost constant. Under the assumption of uniform electric field strength it can be shown that for the same break down voltage, the punch through construction will require approximately half the drift region width of a comparable non - punch through construction. Lower drift region doping in a punch through diode does not carry the penalty of higher conduction lasses due to conductivity modulation to be discussed shortly. In fact, reduced width of the drift region in these diodes lowers the on-state voltage drop for the same forward current density compared to a non-punch through diode. Under reverse bias condition only a small leakage current (less than 100mA for a rated forward current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This reverse current is independent of the applied reverse voltage but highly sensitive to junction temperature variation. When the applied reverse voltage reaches the break down voltage, reverse current increases very rapidly due to impact ionization and consequent avalanche multiplication process. Voltage across the device dose not increase any further while the reverse current is limited by the external circuit. Excessive power loss and consequent increase in the junction temperature due to continued operation in the reverse brake down region quickly destroies the diode. Therefore, continued

18 operation in the reverse break down region should be avoided. A typical I-V characteristic of a power diode under reverse bias condition is shown in Fig 2.5. Fig 2.5: Reverse bias i-v characteristics of a power Diode. A few other important specifications of a power Diode under reverse bias condition usually found in manufacturer s data sheet are explained below. DC Blocking Voltage (V RDC ): Maximum direct voltage that can be applied in the reverse direction (i.e cathode positive with respect to anode) across the device for indefinite period of time. It is useful for selecting free-wheeling diodes in DC-DC Choppers and DC-AC voltage source inverter circuits. RMS Reverse Voltage (V RMS ): It is the RMS value of the power frequency (50/60 HZ) since wave voltage that can be directly applied across the device. Useful for selecting diodes for controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This rating is different for resistive and capacitive loads. Peak Repetitive Reverse Voltage (V RRM ): This is the maximum permissible value of the instantiations reverse voltage appearing periodically across the device. The time period between two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ supply). This type of period reverse voltage may appear due to commutation in a converter. Peak Non-Repetitive Reverse Voltage (V RSM ): It is the maximum allowable value of the instantaneous reverse voltage across the device that must not recur. Such transient reverse voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or lightning surges. Fig. 2.6 shows the relationship among these different reverse voltage specifications.

19 Fig. 2.6: Reverse Voltage ratings of a power diode; (a) Supply voltage wave form; (b) Reverse i-v characteristics

20 1.4 Power Diode under Forward Bias Condition In the previous section it was shown how the introduction of a lightly doped drift region in the p-n structure of a diode boosts its blocking voltage capacity. It may appear that this lightly doped drift region will offer high resistance during forward conduction. However, the effective resistance of this region in the ON state is much less than the apparent ohmic resistance calculated on the basis of the geometric size and the thermal equilibrium carrier densities. This is due to substantial injection of excess carriers from both the p + and the n + regions in the drift region as explained next. As the metallurgical p + n - junction becomes forward biased there will be injection of excess p type carrier into the n - side. At low level of injections (i.e p << n no ) all excess p type carriers recombine with n type carriers in the n - drift region. However at high level of injection (i.e large forward current density) the excess p type carrier density distribution reaches the n - n + junction and attracts electron from the n + cathode. This leads to electron injection into the drift region across the n - n + junction with carrier densities n = p. This mechanism is called double injection Excess p and n type carriers defuse and recombine inside the drift region. If the width of the drift region is less than the diffusion length of carries the spatial distribution of excess carrier density in the drift region will be fairly flat and several orders of magnitude higher than the thermal equilibrium carrier density of this region. Conductivity of the drift region will be greatly enhanced as a consequence (also called conductivity modulation). The voltage dropt across a forward conducting power diode has two components i.e V ak = V j + V RD (2.2) Where V j is the drop across the p + n - junction and can be calculated from equation (2.1) for a given forward current j F. The component V RD is due to ohmic drop mostly in the drift region. Detailed calculation shows V RD J F W D (2.3) Where J F is the forword current density in the diode and W D is the width of the drift region. Therefore V ak = V j + R ON I F (2.3) The ohmic drop makes the forward i-v characteristic of a power diode more linear.

21 Both V j and V AK have negative temperature coefficient as shown in the figure. Few other important specifications related to forward bias operation of power diode as found in manufacturer s data sheet are explained next. Maximum RMS Forward current (I FRMS ): Due to predominantly resistive nature of the forward voltage drop across a forward biased power diode, RMS value of the forward current determines the conduction power loss. The specification gives the maximum allowable RMS value of the forward current of a given wave shape (usually a half cycle sine wave of power frequency) and at a specified case temperature. However, this specification can be used as a guideline for almost all wave shapes of the forward current. Maximum Average Forward Current (I FAVM ): Diodes are often used in rectifier circuits supplying a DC (average) current to be load. In such cases the average load current and the diode forward current usually have a simple relationship. Therefore, it will be of interest to know the maximum average current a diode can conduct in the forward direction. This specification gives the maximum average value of power frequency half cycle sine wave current allowed to flow through the diode in the forward direction. Average current rating of a diode decreases with reduction in conduction angle due to increase in current form factor. Both I FRMS and I FAVM ratings are given at a specified case temperature. If the case temperature increases beyond this limit these ratings has to be reduced correspondingly. Derating curves provide by the manufacturers give the relationship between I FAVM (I FRMS ) with allowable case temperature as shown in Fig Fig 2.8: Derating curves for the forward current of a Power Diode.

22 Questions for Practice: Fill in the blanks i. The region in a power diode increases its reverse voltage blocking capacity. ii. The maximum DC voltage rating (V RDC ) of a power diode is useful for selecting diodes in a DC-DC chopper. iii. The reverse breakdown voltage of a Power Diode must be greater than. iv. The i-v characteristics of a power diode for large forward current is. v. The average current rating of a power diode with reduction in the conduction angle due to increase in the current. vi. The derating curves of a Power diode provides relationship between the and the. vii. i 2 dt rating of a power diode is useful for selecting the. Answer: (i) drift, (ii) freewheeling, (iii) V RSM, (iv) linear, (v) decrease, form factor, (vi) I FAVM /I FRM, case temperature, (vii) protective fuse. 1.5 Switching Characteristics of Power Diodes Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch ON) and vice versa (switch OFF). Behavior of the diode current and voltage during these switching periods are important due to the following reasons. Severe over voltage / over current may be caused by a diode switching at different points in the circuit using the diode. Voltage and current exist simultaneously during switching operation of a diode. Therefore, every switching of the diode is associated with some energy loss. At high switching frequency this may contribute significantly to the overall power loss in the diode. Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt limiting inductors. The rate of rise of the forward current through the diode during Turn ON has significant effect on the forward voltage drop characteristics. A typical turn on transient is shown in Fig

23 Fig. 2.12: Forward current and voltage waveforms of a power diode during Turn On operation. It is observed that the forward diode voltage during turn ON may transiently reach a significantly higher value V fr compared to the steady slate voltage drop at the steady current I F. In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be high enough to destroy the main power switch. V fr (called forward recovery voltage) is given as a function of the forward di/dt in the manufacturer s data sheet. Typical values lie within the range of 10-30V. Forward recovery time (t fr ) is typically within 10 us. Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn off behavior of a power diode assuming controlled rate of decrease of the forward current. Fig. 2.13: Reverse Recovery characteristics of a power diode

24 Questions for Practice: Fill in the blanks i. Forward recovery voltage appears due to higher ohmic drop in the region of a power diode in the beginning of the Turn On process. ii. The magnitude of the forward recovery voltage is typically of the order of few of volts. iii. The magnitude of the forward recovery voltage also depends on the of the diode forward current. iv. The reverse recovery charge of a power diode increases with the of the diode forward current. v. For a given forward current the reverse recovery current of a Power Diode with the rate of decrease of the forward current. vi. For a given forward current the reverse recovery time of a Power diode with the rate of decrease of the forward current. vii. A snappy recovery diode is subjected to voltage over shoot on recovery. viii. A fast recovery diode has reverse recovery current and time compared to a recovery diode. ix. A Schottky diode has forward voltage drop and reverse voltage blocking capacity. x. Schottky diodes have no transient and very little transient. Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii) large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off.

25 2.0 Power Bipolar Junction Transistor (BJT) Objective: On completion the student will be able to Constructional Features, Operating Principles, Characteristics and specifications of Power Bipolar Junction transistors. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction Transistor. List the salient constructional features of a power BJT and explain their importance. Introduction Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its Turn on and Turn off operations. It simplified the design of a large number of Power Electronic circuits that used forced commutated thyristor at that time and also helped realize a number of new circuits. Subsequently, many other devices that can broadly be classified as Transistors have been developed. Many of them have superior performance compared to the BJT in some respects. They have, by now, almost completely replaced BJTs. However, it should be emphasized that the BJT was the first semiconductor device to closely approximate an ideal fully controlled Power switch. Other transistors have characteristics that are qualitatively similar to those of the BJT (although the physics of operation may differ). Hence, it will be worthwhile studying the characteristics and operation a BJT in some depth. From the point of view of construction and operation BJT is a bipolar (i.e. minority carrier) current controlled device. It has been used at signal level power for a long time. However, the construction and operating characteristics of a Power BJT differs significantly from its signal level counterpart due to the requirement for a large blocking voltage in the OFF state and a high current carrying capacity in the ON state. In this module, the construction, operating principle and characteristics of a Power BJT will be explored.

26 transistor and n A pe,p A nb for p-n-p transistor). A portion of the minority carriers reaching the base recombines with majority carriers. The rest, defuse to the edge of the depletion region at J CB where they are swept away to the collector region by the large electric field. Under this condition the transistor is said to be in the Active region. As V BE is increased injected minority charge into the base region increases and so does the base current and the collector current. For a fixed collector bias voltage V CC, the voltage V CB reduces with increase in collector current due to increasing drop in the external resistance R C. Therefore, the potential barrier at J CB starts reducing. At one point J CB becomes forward biased. The potential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 by variables with a super script s. Due to forward biasing of J CB there will be minority carrier injection into the base from this junction also as shown in Fig The total voltage drop between collector and emitter will be the difference between the forward bias voltage drops at J BE and J CB. Under this condition the transistor is said to be in the saturation region. From the operating principle described above one can form a qualitative idea about the input (i B B vs V BE ) and output (i C Vs V CE ) characteristics of a transistor. In the following section these characteristics of an n-p-n transistor will be discussed qualitatively. Similar explanation applies to a p-n-p transistor. When a biasing voltage V BB of appropriate polarity is applied across the junction J BE the potential barrier at this junction reduces and at one point the junction becomes forward biased. The current crossing this junction is governed by the forward biased p-n junction equation for a given collector emitter voltage. The base current i B B is related to the recombination of minority carriers injected into the base from the emitter. The rate of recombination is directly proportional to the amount of excess minority carrier stored in the base. Since, in a normal transistor the emitter is much more heavily doped compared to the base the current crossing J BE is almost entirely determined by the excess minority carrier distribution in the base. Thus, it can be concluded that the relationship between i B B and V BE will be similar to the i-v characteristics of a p-n junction diode. V CE, however have some effect on this characteristic. As V CE increases reverse bias of J CB increases and the depletion region at J CB moves deeper into the base. The effective base width thus reduces, reducing the rate of recombination in the base region and hence the base current. Therefore i B B for a given V BE reduces with increasing V CE as shown in Fig. 3.2(a). It has been mentioned before that only a fraction (denoted by the letter ) of the total minority carriers injected into the base reaches junction J CB where they are swept in to the collector region by the large electric field at J CB. These minority carriers constitute the major component of the total collector current. The other component of the collector current consists of the small reverse saturation current of the reverse biased junction J CB. Therefore I C = I E + I cs (3.1) Where I cs is the reverse saturation current of junction J CB But I E = I BB + I C (3.2)

27 increases at I CS I C = + I B 1-1- (3.3) By defining 1 I C = IB + ( +1) I cs (3.4) is called the large signal common emitter current gain of the transistor and remains fairly constant for a large range of I C, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out put characteristics (i c vs V CE ) of an n-p-n transistor. With V BB = 0 or negative there is little injected minority carrier into the base from the emitter side. Therefore, i B B = 0 and i C is negligibly small. The transistor is said to be in the cut off region under this condition. As V BB is increased from zero, base current starts flowing. From equation (3.4) it will be expected that the collector current should increase proportionately independent of V CE. However Fig 3.2 (b) does indicate a slight increase in i C with V CE for a given i B. B This is expected because with increasing V CE a larger value of V BE will be required to maintain a given i B B (Fig. 3.2 (a)). Therefore, the component I E of collector current will increase. I CS is,for all practical purpose, independent of V CE. This is the active or amplifier mode of operation of a transistor. In the active region as i B B i C also increases. For a given value of V CC, V CE reduces with increasing i C due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point the junction J CB becomes forward biased. V CE, now is just the difference between the voltages across two forward biased junction J BE and J CB (a few handed milli volts). This is when the transistor enters the saturation mode of operation. The ratio i C /i B B the onset of saturation is called Min and is an important parameter for a power transistor. In saturation i C is almost entirely determined by the external load and further increase in i B changes i C or V CE very little.

28 ib6 ib5 ib4 ib3 Active ib2 ib1 i B = 0 Cut off vce i B increasin g (b) i C i B vce increasing Saturati on vbe (a) (c)

29 Fig. 3.2: Input and output characteristics of an n p n transistor. Questions for Practice: (a) Input characteristics; (b) Output characteristics; (c) Current gain[ ] characteristics Fill in the blank 1. Under forward bias condition a large number of carriers are introduced in the base region. 2. Some minority charge carriers reaching base with majority carriers there and the rest of them to the collector. 3. When the base-emitter junction of a BJT is forward biased while the basecollector junction is reverse biased the BJT is said to be in the region. 4. When both B-E & C-B junction of a BJT are reverse biased it is said to be in the 5. region. 6. When both B-E & C-B junction of a BJT are forward biased it is said to be in the 7. region. Answer: (a) minority; (b) recombine, diffuse; (c) active; (d) cut-off; (e) saturation. 2.1 Constructional Features of a Power BJT Power transistors face the same conflicting design requirements (i.e. large off state blocking voltage and large on state current density) as that of a power diode. Therefore, it is only natural to extend some of the constructional features of power diodes to power BJT. Following Section summarizes some of the constructional features of a Power BJT. Since Power Transistors are predominantly of the n-p-n type, in this section and subsequently only this type of transistor will be discussed. A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and power lass is minimized. In order to maintain a large current gain β (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible.

30 In order to block large voltage during OFF state a lightly doped collector drift region is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being moderate the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor can not be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain ( ) of a Power transistor which typically varies within As will be discusses later the collector drift region has significant effect on the out put characteristics of a Power BJT. viii. Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent current crowding and consequent second break down. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path. These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b) shows the photograph of some community available Power transistors in different packages. mitter contact Base contact n + (emitter) n + n + p (Base) n - (Collector Drift) n + (Collector) (a) Collector contact

31 (b) Fig. 3.3: Constructional Features of a Power Bipolar Junction Transistor (a) Schematic of Construction,Photograph of commercial packages. Questions for Practice: Fill in the blank a) Doping density of the emitter of a Power BJT is several orders of magnitude than the base doping density. b) Collector drift region is introduced in a Power BJT to block voltage. c) Doping density of the base region in a power BJT is. d) Power BJT has DC current gain compared to signal level transistors. e) In a Power BJT multiple, narrow finger like distributed emitter structure is used to avoid emitter. Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding. 2.2 Output i-v characteristics of a Power Transistor A typical output (i C vs V CE ) characteristics of an n-p-n type power transistor is shown in Fig 3.4 A power transistor exhibits Cut off, Active and Saturation regions of operation in its output characteristics similar to a signal level transistor. In fact output characteristics of a Power Transistor in the Cut off and Active regions are qualitatively identical to a signal level transistor. Certain quantitative restrictions apply, however, which are discussed next.

32 i C Hard Saturation Quasi Saturation ib10 ib9 ib8 ib7 ib6 Second break down limit Active Total Power dissipation limit ib5 ib4 ib3 ib2 ib1 Increasing i B Primary break down voltage i B 0 Cut off CE VSUS VCE0 VCB0 (i B = 0) (i B < 0) Fig. 3.4 Output ( i c v CE ) characteristics of an n p n type Power Transistor In the cut off region (i B B 0) the collector current is almost zero. The maximum voltage between collector and emitter under this condition is termed Maximum forward blocking voltage with base terminal open (i B B = 0) and is denoted by V CEO. For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with i B B = 0. This blocking voltage can however be increased to a value V CBO by keeping the emitter terminal open. In this case i B < o. Actually V CBO is the breakdown voltage of the collector base junction. However, since the open base configuration is more common the value of V CEO is used by the manufacturers as the maximum voltage rating of a power transistor. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the base-emitter junction. Therefore, reverse voltage (C negative with respect to E) should not appear across a power transistor. In the active region the ratio of collector current to base current (DC current Gain ( )) remains fairly constant upto certain value of the collector current after which it falls off rapidly. Manufacturers usually provide a graph showing the variation of as a function of the collector current for different junction temperatures and collector emitter voltages. This graph is useful for designing the base drive of a Power transistor. Typically, the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart.

33 for > The maximum collector-emitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. This voltage, denoted by V SUS in Fig, 3.4 is usually smaller than V CEO. The voltage V SUS can be attained only for relatively lower values of collector current. At higher collector current the limit on the total power dissipation defines the boundary of the allowable active region as shown in Fig 3.4. At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called the Second Break down. It appears on the output characteristics of the BJT as a precipitous drop in the collector- emitter voltage at large collector currents. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of current filamements (localized areas of very high current density) by a positive feed-back mechanism. Once current filaments are formed localized thermal runaway quickly takes the junction temperature beyond the safe limit and the device is destroyed. It is in the saturation region that the output characteristics of a Power transistor differs significantly from its signal level counterpart. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor. In the quasi saturation region the base-collector junction is forward biased but the lightly doped drift region is not completely shorted out by excess minority carrier injection from the base. The resistivity of this region depends to some extent on the base current. Therefore, in the quasi saturation region, the base current still retains some control over the collector current although the value of decreases significantly. Also, since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given collector current compared to what it will be in the hard saturation region. In the hard saturation region base current looses control over the collector current which is determined entirely by the collector load and the biasing voltage V CC. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base). Therefore, for larger collector currents the collector-emitter voltage drop is almost proportional to the collector current. Manufacturers usually provide the plots of the variation of V CE (sat) vs. i C for different values of base current and junction temperature. Curves showing the variation of V CE (sat) with i B B different values of i C and junction temperature are also provided by certain manufacturers.applicable operating limits on a power transistors are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. (RBSOA) applicable to i B B 0 and i B B 0 conditions respectively. Typical safe operating areas of power transistors are shown in Fig 3.5.

34 Questions for Practice: Fill in the blanks: i) In the Cut off region collector current of a Power Transistor is. ii) In the region of a Power Transistor the dc current gain remains fairly constant. iii) Saturation region of a Power Transistor can be divided into region and region. iv) Active region operation of a Power BJT is limited mostly by consideration. v) Second breakdown in a Power BJT occurs due to of the collector current distribution. Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power dissipation; (e) non uniformity. 2.3 Switching characteristics of a Power Transistor In a power electronic circuit the power transistor is usually employed as a switch i.e. it operates in either cut off (switch OFF) or saturation (switch ON) regions. However, the operating characteristics of a power transistor differs significantly from an ideal controlled switch in the following respects. i It can conduct only finite amount of current in one direction when ON ii It can block only a finite voltage in one direction. iii It has a voltage drop during ON condition iv It carries a small leakage current during OFF condition v Switching operation is not instantaneous vi It requires non zero control power for switching Of these the exact nature and implication of the first two has been discussed in some depth in the previous section. The third and fourth non idealities give rise to power loss termed the conduction power loss. In this section the nature and implications of the last two non idealities will be discussed in detail.

35 Questions for Practice: Fill in the blanks: a) An ideal switch can conduct current in directions. While a power transistor conducts current in direction. b) In power transistor there will be power loss due to ON state and OFF state. c) Unlike an ideal switch the switching of a power transistor is not. Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous. 2.4 Turn On characteristics of a Power Transistor From the description of the basic operating principle of a power transistor presented in the previous sections it is clear that minority carriers must be moved across different regions of a power transistor in order to make it switch between cut off and saturation regions of operation. The time delay in the switching operation of a power transistor is due to the time taken by the minority carriers to reach appropriate density levels in different regions. The exact level of minority carrier densities (and depletion region widths) required for proper switching is determined by the collector current and biasing collector voltage during switching, both of which are determined by external circuits. The rate at which these densities are attained is determined by the base current waveform. Therefore, the switching characteristics of a power transistor is always specified in relation to the external load circuit and the base current waveform as shown in Fig 3.6 which shows a clamped inductive switching circuit with a flat base drive. VCC i D D I L R B i B i C + Q V CE VBB VBE -

36 (a) VBB t d tri tfv1 tfv2 VBE VBE sat 0 V BB - V BE(sat) R B t i B t i c i d I L I L t vce V CC VCE (sat) t P e VCC IL v CE (sat) I L t (b)

37 Fig 3.6 Turn ON characteristics of a power transistor; (a) Switching circuit, (b) Switching wave forms The switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent idealized version of the actual waveforms that will be observed in a clamped inductive switching circuit as shown in Fig.3.6 (a). Keypoint Some simplifying assumptions have been made to draw these waveforms. These are The load inductor has been assumed to be large enough so that the load current does not change during Turn ON period. A reverse recovery characteristic of D has been ignored. All parasitic elements have been ignored. Before t = 0, the transistor (Q) was in the OFF state. In order to utilize the increased break down voltage (V CBO ) the base- emitter junction of a Power Transistor is usually reverse biased during OFF state. Under this condition only negligible leakage current flows through the transistor. Power loss due to this leakage current is negligible compared to other components of power loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flows through the diode and V CE is clamped to V CC (approximately). To turn the transistor ON at t = 0, the base biasing voltage V BB changes to a suitable positive value. This starts the process of charge redistribution at the base-emitter junction. The process is akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often represented by a voltage dependent capacitor, the value of which is given by the manufacturer as a function of the base- emitter reverse bias voltage. The rising base current that flows during this period can be thought of as this capacitor charging current. Finally at t = t d the BE junction is forward biased. The junction voltage and the base current settles down to their steady state values. During this period, called the Turn ON delay time no appreciable collector current flows. The values of i O and V CE remains essentially at their OFF state levels. At the end of the delay time (t d ON ) the minority carrier density at the base region quickly approaches its steady state distribution and the collector current starts rising while the diode current (i d ) starts falling. At t = t don + t ri the collector current becomes equal to the load current (and i d becomes zero) I L. At this point D starts blocking reverse voltage and V CE becomes unclamped. t ri is called the current rise time of the transistor. At the end of the current rise time the diode D regains reverse blocking capacity. The collector voltage V CE which has so far been clamped to V CC because of the conducting diode D starts falling towards its saturation voltage V CE (sat). The initial fall of V CE is rapid. During this period the switching trajectory traverses through the active region of

38 the output characteristics of the transistor. At the end of this rapid fall (t fv1 ) the transistor enters quasi saturation region. The fall of V CE in the quasi saturation region is considerably slower. At the end of this slow fall (t fv2 ) the transistor enters hard saturation region and the collector voltage settles down to the saturation voltage level V CE (sat) corresponding to the load current I L. Turn ON process ends here. The total turn on time is thus, T SW (ON) = t d (ON) + t ri + t fv1 + t fv2. Power loss occurs at all time during the operation of a power transistor. However, the collector leakage current is usually negligibly small and power loss due it can be safely neglected in comparison to the power loss during ON condition. Power loss occurs during Turning ON a Power transistor due to simultaneous existence of non-zero V CE and i c during t ri, t fv1, and t fv2. The energy lost during these periods is called the Turn ON loss and given by the area under the P l curve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (t ri + t fv1 + t fv2 ). For safe Turn ON this average power loss must be less than the limit set on the maximum power dissipation in the FBSOA corresponding to a pulse width greater than t ri + t fv1 + t fv2. Similar restriction with respect to second break down should also be observed. Turn ON time can be reduced by increasing the base current. However large base current increases the quantity of excess carrier in the base and collector drift region which has to be removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON delay time can however be reduced by boosting the base current at the beginning of the Turn ON process. This can be achieved by connecting a small capacitance across R B. B This increases the rate of rise of V BE & i B. B Therefore, Turn ON delay time decreases. However, in steady state i B B settle downs to a value determined by R B B & V BB and no adverse effect on the Turn OFF time is observed. In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is not negligible then for safe Turn ON operation the sum of the load current and the diode reverse recovery current must be less than the I CM rating of the transistor. Thermal and second break down limits must also be observed. It should be noted that there is some power loss at the BE junction as well. This power loss depends on the current gain of the transistor during hard saturation. Since current gain reduces during saturation (typically between 5 to 10) this power loss may become significant. Manufacturers usually provide the values of t d (ON), t ri, t fv as functions of i c for a given base current and case temperature.

39 Questions for Practice: Fill in the blanks: a) For faster switching of a BJT carriers are to be swept quickly from the region. b) The reverse biased base emitter junction can be represented as a dependent. c) In the quasi saturation region collector-emitter voltage falls at a rate. d) Turn ON delay can be reduced by the rate of rise of the base current. Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing. 2.5 Turn Off Characteristics of a Power Transistor During Turn OFF a power transistor makes transition from saturation to cut off region of operation. Just as in the case of Turn ON, substantial redistribution of minority charge carriers are involved in the Turn OFF process. Idealized waveforms of several important variables in the clamped inductive switching circuit of Fig. 3.6 (a) during the Turn OFF process of Q are shown in Fig 3.7 (a)

40 VBE(sat) t VBB VBE VBB t i B I L I L i C t i d VCE(Sat) VCC t VCE t P e t s trv1 trv2 (a) tfi

41 log i C Reverse recovery current of D ICM P FBSOA P RBSOA Forward recovery Voltage of D Turn off Trajectory Turn on Trajectory VCBO (b) V(sus) VCEO Fig. 3.7: Turn off, characteristics of a BJT. (a) Switching wave forms (b) Switching trajectory log v CE The Turn OFF process starts with the base drive voltage going negative to a value -V BB. The base-emitter voltage however does not change from its forward bias value of V BE (sat) immediately, due to the excess, minority carriers stored in the base region. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. After a time t s called the storage time of the transistor, the remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope. After a further time interval t rv1 the transistor completes traversing through the quasi saturation region and enters the active region. The stored charge in the base region at this point is insufficient to support the full negative base current. V BE starts falling forward V BB and the negative base current starts reducing. In the active region, V CE increases rapidly towards V CC and at the end of the time interval t rv2 exceeds it to turn on D. V CE remains clamped at V CC, thereafter by the conducting diode D. At the end of t rv2 the stored base charge can no longer support the full load current through the collector and the collector current starts falling. At the end of the current fall time t fi the collector current becomes zero and the load current freewheels through the diode D. Turn OFF process of the transistor ends at this point. The total Turn OFF time is given by Ts (OFF) = t s + t rv1 + t rv2 + t fi. As in the case of Turn ON considerable power loss takes place during Turn OFF due to simultaneous existence of i c and V CE in the intervals t rv1, t rv2 and t fi. The last trace of Fig 3.7 (a) shows the instantaneous power loss profile during these intervals. The total energy last per turn off operation is given by the area under this curve. For safe turn off the average power dissipation during t rv1 + t rv2 + t fi should be less than the power dissipation

42 limit set by the FBSOA corresponding to a pulse width greater than t rv1 + t rv2 + t fi. Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions and the base drive design. Manufacturers usually specify these values as functions of collector current for given positive and negative base current and case temperatures. Variations of these time intervals as function of the ratio of positive to negative base currents for different collector currents are also specified. In this section and the precious one inductive load switching have been considered. However, if the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage (V CE ) and collector current (i c ) will fall and rise respectively together during Turn ON and rise and fall respectively together during Turn OFF. Other characteristics of the switching process will remain same. The switching Power loss in this case will also be substantially lower. Questions for Practice: Fill in the blanks: a) Turn OFF process in a BJT is associated with transition from the region to the region. b) Negative current is required to remove excess charge carriers from the region of a BJT during Turn OFF process. c) V CE increases rapidly in the region. Answer: (a) Saturation, Cut-off; (b) base, base; (c) active. Summary: A Bipolar Junction Transistor is a minority carrier, current controlled unidirectional device. A BJT can be of n-p-n or p-n-p type with three terminals called the collector, the base and the emitter. A BJT can operate in cut-off, active or saturation regions. In the cut-off region the base emitter junction is reverse biased and the collector current is almost zero. In the active region the ratio of collector current to base current is fairly constant. This ratio is called the dc current gain ( ). A transistor can be driven into saturation by increasing the base current for a given collector current. In saturation the V CE voltage drop of a transistor is very low. Switching of Power transistors from ON (saturation) to OFF (cut-off) state involves considerable redistribution of minority carriers. Therefore,

43 switching operation is not instantaneous. 3.0 Thyristors and Triacs Objectives We will be able to The operating principle of a thyristor in terms of the two transistor analogy. The i-v characteristics of a thyristor. The gate characteristics of a thyristor. Interpret data sheet rating of a thyristor. The switching characteristics of a thyristor. Operating principle of a Triac. Introduction Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics area truly began with advent of thyristors. One of the first developments was the publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in Bell s Signal application. However, engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in This had a continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme for two entire decades in the history of power electronics. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO). From the construction and operational point of view a thyristor is a four layer, three terminal, minority carrier semi-controlled device. It can be turned on by a current signal but can not be turned off without interrupting the main current. It can block voltage in both directions but can conduct current only in one direction. During conduction it offers very low forward voltage drop due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens of s) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control input, have all but eliminated thyristors in high frequency switching applications involving a DC input (i.e, choppers, inverters). However in power frequency ac applications where the current naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse voltage

44 blocking capability and very low control power requirement. In fact, in very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC (cycloconverters) converters, thyristors still remain the device of choice. 3.1 Silicon Controlled Rectifier (SCR) Construction: i. It is a four layer three terminal device. Anode (A), Cathode (K), Gate (G) ii. iii. These four layers are alternate P type and N type, P N P- N P + layer doped at /Cm 3, P- layer is doped at /cm 3. These layer forms Anode (A). iv N- Layer is lightly doped at /Cm 3.This layer absorbs depletion layer of junction J 2. v. Gate terminal is usually kept near the cathode (K). Modes of operation (Static V-I characteristics): The anode & cathode are connected to main source through the load. The gate and cathode are fed from source Vs which gives +Ve gate current Reverse blocking mode: Anode is made negative w.r.t. cathode and gate is open

45 Due to this junction j 1,j 3 are in reverse biased & j 2 is in forward biased. At this condition thyristor cannot conduct. A small current flow from K to A is called reverse leakage current. This mode is called reverse blocking mode. When we increase the reverse voltage but small current flows. When the voltage reaches the value of reverse breakdown voltage (V BR ) the reverse current increases rapidly. During this condition current and voltage across the SCR increased and leads large power dissipation. At this mode +Ve gate should not be applied. Forward blocking mode: i. At this mode anode is made +ve w.r.t. cathode. ii.due to this forward bias, junction j1 & j3 is forward biased, j2 is reverse biased. iii. A small current flow from anode to cathode & this current is called forward leakage current. iv. This mode is called forward blocking mode, here the SCR is in FB but not turn ON. v. At this mod4e the V AK increased to V BO the thyristor turns ON. vi. Now the thyristor goes from forward blocking mode to forward conduction mode. Forward conduction mode: The SCR is brought in to forward conduction mode by following techniques. i. When V AK > V BO ii. When gate drive is applied iii. When exceeds permissible value When V AK > V BO: When V AK > V BO the avalanche breakdown of the junction j 2 takesplace so that heavy current starts flowing even gate drive is not applied. When gate drive is applied: When a +ve gate signal is applied thyristor is driven in to forward conduction mode.when gate signal is applied the current flows fron gate to cathode adds to forward leakage current. Hence avalanche breakdown occurs at j2 and SCR goes to forward conduction mode even V AK.V BO. Latching current ( I L ):

46 It is the minimum forward current flows through the thyristor to keo it in forward conduction mode (ie) ON state.( If forward current is less than latching current, thyristor doesnot ON) it is n the order of ma. Holding current (I H ): It is the minimum forward current that flows through the thyristor to keep it in forward conduction mode. When the forward current reduces below I H, thyristor turns OFF. Comparison between I L & I H : Sl.No Latching curent Holding current Effective at the time of Turning Effective at the time of Turning 1. ON OFF I L is greater than I H even though 2. I H is less than I L their magnitude are much related 3. I L is the minimum forward current that should flow at the time turn ON Thyristor is already ON state its current should not reduce below I H otherwise turns OFF Two transistor model of Thyristor ( Two transistor Analogy) : The operation of thyristor can be explained with the help of two transistor model. Here two transistor of PNP & NPN are connected in common base configuration When thyristor is in FB and gate open, the current flows as shown in figure. In transistor, I c1 = α 1 I E1 + I C (1) Here, I E1 = I D & I C01 is leakage current of T 1 I c2 = α 2 I E2 + I C (2) I E2 = I D & I C02 is leakage current of T 2 By Analysing fig C. I D = I c1 + I c (3) Putting Eqn. (1 ) & (2 ) in (3) I D = α 1 I D + I C01 + α 2 I D + I C02 = ( α 1 + α 2 ) I D + I C01 + I C02 I D - ( α 1 + α 2 ) I D = I C01 + I C02 [ 1 - ( α 1 + α 2 ) ] I D = I C01 + I C02 [ I C01 + I C02 = I C0 ]

47 I D = (4) I C0 = Reverse leakage current of reverse biased j 2, α 1 = Common base current gain of T 1 α 2 = Common base current gain of T 2. Initially when forward voltage is very small, ( α 1 + α 2 ) is very small, Hence forward blocking current as given in eqn. (4) is also small. As forward voltage increases α 1, α 2 are also increases & ( α 1 + α 2 ) reaches unity, the regeneration starts and the thyristor goes in to ON state. Once the thyristor gets ON the above analysis is not valid. When the current thyristor falls below holding current forward blocking state is regained. I D = Thyristor Turn ON method: 1. Gate drive: Thyristor can be turned ON by applyine +ve gate cathode voltage. 2. High forward voltage: Thyristor can turned ON by applying V AK > V BO 3. : When anode cathode voltage changes rapidly. The leakage current increases and leads to turn ON thyristor. 4. : By applying light energy at cathode gate junction the thyristor can be turned ON. 5. Temperature: Thyristor can be turn ON by increasing the temperature. 3.2 Switching characteristics of SCR:

48 Turn ON Dynamic characteristics: The gate pulse is applied when t = 0, the anode current rise very slowly. This is Called delay time t d. Anode to cathode voltage does not reduce during delay time. During the rise time t r the anode current increases & anode to cathode voltage (V AK ) reduces rapidly At this time high voltage and high current present in the thyristor. Hence large dissipation takes place. This power loss is called switching loss. During spread time t p the starts spreading in the remaining area. Now the anode current reaches to maximum value and V AK falls to lowest value. T on = t d + t r + t p

49 Turn ON time: It is defined as the time from initiation of gate drive to the time when anode current reaches its full value. Turn OFF Dynamic characteristics: The thyristor is turned OFF by commutation circuit. This circuit applies negative voltage across thyristor durin turn OFF period. When we apply ve voltage to the thyristor regains its forward blocking stage. From the graph, the anode current falls and become ve. This current flows through the thyristor for a short period. During conduction stage thyristor have large number of charge carriers. This ve currnt removes these carriers and then j 1 & j 3 achieve their forward blocking stage.the time required for this is called reverse recovery time (t rr ). At the end of t rr the reverse voltage is zero but still the thyrstor is not turned ON since the commutation circuit hold the ve voltage for a time t gr is called gate recovery time. t q = t rr + t gr

50 Turn OFF time: `It can be defined as the time required to achieve forward blocking capability after commutation is initiated. The circuit turn OFF tim t c must be greater than thyristor turn OFF time t q. Inverter grade thyristor has the t q less than 25µs Converter grade thyristor has the t q greaer than 25µs Thyristor Gate Characteristics: It is the graph between gate voltage & gate current. It is similar to the characteristic of diode since the gate cathode circuit is a pn junction. This characteristic has a spread between curve1 & curve2. It is due to the difference in doping levels of P & N junction. To turn on the thyristor successfully the gate current and voltage should be I g(min) I g I g(max) V g(min) V g V g(max) I g(max) - Maximum gate current that can flow through the thyristor without damaging I g(min) V g(max) damaging V g(min) - Minimum gate current below which thyristor cannot turned ON - Maximum gate voltage that can flow through the thyristor without - Minimum gate voltage below which thyristor cannot turned ON

51 Requirement of Gate drive: i. The maximum gate power should not be exceeded by gate drive. ii. The gate current & voltage should be within limits specified by gate characteristics. iii. The gate drive preferably pulsed. iv. The width of the pulse should be sufficient to turned ON the SCR. v. Gate drive should be isolated electrically from thyristor. Thyristor Ratings: (i) Current Ratings: Average current Rating I T : It is the maximum repetitive average current that flow through thyristor. Power loss depends on this rating. RMS current rating (I TR ): It is the maximum repetitive RMS current that flow through thyristor. It required to prevent the heating of metallic leads and interfaces of thyristor. Surge current Rating(I TSM ): It is the peak amplitude of the surge current that the thyristor can withstand only limited number of times in its life cycle. i 2 t Rating (I TR ): This rating is used to determine how long the device can absorb the thermal energy. Rating: This rating specifies the maximum allowable rate of change of current through the device. (ii) Voltage Rating: Peak repetitive forward blocking voltage (VDRM): This is the maximum voltage that the thyristor can block in the forward direction. If this rating is exceeded the device turn-on not damage the device. Peak repetitive reverse voltage (VRRM) or Peak Inverse Voltage (PIV): This is the maximum that the device can withstand repetitively in the blocking state. The device is damaged when this rating is exceeded. Rating: This rating specifies the maximum allowable rate of change of forward voltage tht the device can withstand in forward direction. Snubber for Protection against and over voltage:

52 The transient voltage can swicth on the SCR in some cases, in some cases it will damage the device. This transient are common when converter having inductive load. The thyristor can protected against this by a RC circuit called snubber circuit. The RC circuit acts as low pass filter, so that the circuit is provided across the thyristor and it will absorbs the high transient voltage. The value of R is very small so that the capacitor will absorb the transient very quickly. Some times also generates large voltage transients. This voltage variation also suppressed by snubber circuit. The capacitor is short for ratio. The snubber can be modified more effective by connecting a diode across the resistance as shown in below figure. Keypoint: Design of Snubber: R = 2 Over current Protection: The over current flows through thyristor due to short circuited load,misalignment of fire pulses, over voltages. Normally fast acting fuses are used

53 over current protection. These fuses melts at lower currents than rating of thyristor and disconnect the circuit. Protection: During turn ON period the anode current increase rapidly,thease variationdoesnot spread across the junction and produce local hot spots. This variation of currents is called. The inductor connected in series with SCR to avoid the damage due to ever the is a rapid current variation, the inductor smoothes it and protect the thyristor from damages. The value of inductance can be calculated by,. When L = 3.4 SCR Firing Circuits: Keypoint: Features: a) The firing circuit should produce triggering pulse for every thyristor at correct instant. b) There must be a electrical isolation between firing circuit and SCR. It can be achieved by isolation transformer or optocoupler. R Firing circuit: Rmin is used to limit the gate current to its max. value. Rmin = Rb is the stabilizing resistance. Voltage across this resistor should not exceed Vgmin otherwise thyristor will turned ON. RC firing circuit:

54 In the negative half cycle capacitor charges through D2 to a value of Vm During positive half cycle the capacitor discharge through R The thyristor triggers when the capacitor charges above Vgmin.. The diode D1 prevents the appearance of negative voltage across the gate. By this circuit the triggering angle can be controlled from UJT triggering circuit: It is the mostly used triggering circuit. Here the supply voltage is rectified and given to the zener regulator. The voltage is clamped to the level of zener voltage V z and given to the UJT. The capacitor C charges through R c, when the voltages reaches the value above V p of UJT, the UJT turns ON. Then the pulse transformer produces the pulses and it apply to the gate of the SCR Questions for Practice: Fill in the blanks: 1.A thyristor is a carrier semi controlled device. 2.A thyristor can conduct current in direction and block voltage in direction.

55 3.A thyristor can be turned ON by applying a forward voltage greater than forward voltage or by injecting a positive current pulse under forward bias condition. 4.To turn OFF a thyristor the anode current must be brought below current and a reverse voltage must be applied for a time larger than time of the device. 5. A thyristor may turn ON due to large forward. 6. Forward break over voltage of a thyristor decreases with increase in the current. 7. Reverse voltage of a thyristor is of the gate current. 8.Reverse saturation current of a thyristor with gate current. 9. In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the time of the device. 10. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate voltage. Answers: (1) minority; (2) one, both; (3) break over, gate; (4) holding, turn off; 5) dv dt 6)gate; (7) break down, independent; (8) increases; (9) Turn ON; (10) nontrigger. 3.5 Bidirectional triode thyristor (TRIAC) TRIAC is a bidirectional device. It conducts in both the direction. It is equivalent to two antiparallel SCRs. It has three terminal Main termina 1 (MT 1 ), Main terminal 2 (MT 2 ), and gate. The current will flow from MT1 to MT 2 when MT 1 is positive & flow from MT 2 to MT 1 when MT 2 as positive. The triac is turned ON when gate positive as well as negative.

56 Structure & V - I characteristics of TRIAC: Here the MT 1 is connected to two layers N 2 & P 2 Gate is connected to N 3 & P 2, MT 2 also connected to two layers N 4 & P 1. V- I Characteristics: The current I is plotted with respect to voltage. I F & V F are the forward current and voltage. Its forward characteristic is similar to that of the SCR. The V R & I R are the reverse voltage and current. When gate drive is applied the tria can conduct even below the V BO Once the triac turns ON the voltage drop across the device drops and current increases rapidly. Operation modes (or) triggering modes of TRIAC: Mode 1 (MT2 is positive with positive gate):

57 At this mode MT 2 is positive with positive gate, the gate current flows from gate terminal to MT 1 through the layer P 2 N Now the conduction is taking place through the P 1 N 1 P 2 N The P 2 is flooded with electrons, this electrons diffuse through J 2 and collected by N Negative space charge is established in N 1 & holes from the P 1 neutralize the space charge. P 2 N The holes arrive at J 2 and produce positive space charge at in the P 2 so that more electrons injected from N 2 to P 2. It forms positive regeneration then the layer P 1 N 1 P 2 N 2 conducts. Mode 2 (MT2 is positive with negative gate): (junction gate operation) At this mode the gate current flows from This current forward biases the junction P 2 N 3, as a result P 1 N 1 P 2 N 3 conducts. Due to this conduction voltage drop across the P 2 N 3 rises towards anode potential of MT 2. So that there is a potential gradient exist with left hand region having higher potential. Now the conduction shifted from left to right now the conduction layer is P 1 N 1 P 2 N 2. Mode 3: (MT2 is negative with positive gate): (Remote gate operation) At this mode the device operates in III quadrant. First the conduction is taking place through the layer P 2 N 1 P 1 N 4 with N 4 acting as remote gate. The gate current forward biases P 2 N 2 junction. The layer N 2 injects electrons into P 2 & it is collected by P 2 N 1 which increases the current. More electrons from N 4 diffuse into P 1 so that the conduction is established through P 2 N 1 P 1 N 4. Mode 4: (MT2 is negative with negative gate) At this mode N3 act as remote gate and the conduction takes place through P 2 N 1 P 1 N 4 Merits of Triac: It can conduct in both the directions.

58 It can be turn OFF easily by reversing the voltage Single gate controls the conduction in both the direction High current & voltage rating triac can available Demerits of Triac: i. It is not suitable for DC power applications ii. iii. Once it conducts gate has no control It has very small switching frequencies Applications: AC power controllers and heater, fan etc., Triggering device for SCRs 3.7 Triac Switching and gate trigger circuit Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result the triacs are operated only at power frequency. Switching characteristics of a triac is similar to that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when a triac is used to control a lagging power factor load. At the current zero instant (when the triac turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. Theresulting dv dt may turn on the triac again. Similar problem occurs when a triac is used tocontrol the power to a resistive element which has a very low resistance before normal working condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply voltage very large junction capacitance charging current will turn ON the device. To prevent such condition an R-C snubber is generally used across a triac. The triac should be triggered carefully to ensure safe operation. For phase control application, the triac is switched on and off in synchronism with the mains supply so that only a part of each half cycle is applied across the load. To ensure clean turn ON the trigger signal must rise rapidly to provide the necessary charge. A rise time of about 1 s will be desirable. Such a triac gate triggering circuit using a diac and an R-C timing network is shown in Fig 4.16.

59 LOAD R 1 V 1 R 2 D 1 R Fig. 4.16: Triac triggering circuit using a diac. In this circuit as Vi increases voltage across C 1 increases due to current flowing through load, R 1, R 2 and C 1. The voltage drop across diac D 1 increases until it reaches its break over point. As D 1 conducts a large current pulse is injected into the gate of the triac. By varying R 2 the firing can be controlled from zero to virtually 100%. Questions for Practice: Fill in the blanks 1)A Triac is a minority carrier device 2)A Triac behaves like two connected thyristors. 3)The gate sensitivity of a triac is maximum when the gate is with respect to MT 1 while MT 2 is positive with respect to MT 1 or the gate is with respect to MT 1 while MT 2 is negative with respect to MT 1 4)A Triac operates either in the or the quadrant of the i-v characteristics. 5)In the quadrant the triac is fired with gate current while in the quadrant the gate current should be. 6)The maximum possible voltage and current rating of a Triac is considerably compared to thyristor due to

60 of the two current carrying paths inside the structure of the triac. 7)To avoid unwanted turn on of a triac due to large dv dt are used across triacs. 8)For clean turn ON of a triac the of the gate current pulse should be as as possible. Answer: (i) Summary bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first, positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time, small. Thyristor is a four layer, three terminal, minority carrier, semi-controlled device. The three terminals of a thyristor are called the anode, the cathode and the gate. A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage. A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. This is called gate triggering. A thyristor can block voltage of both polarity but conducts current only from anode to cathode. After a thyristor turns on the gate looses control. It can be turned off only by bringing the anode current below holding current.

61 4.0 Metal OxideSemiconductor FieldEffect transistor(mosfet) Objectives We will be able to Constructional Features, Operating principle and characteristics of Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The output i-v characteristics of a MOSFET and explain it in terms of the operating principle of the device. Design the gate drive circuit of a MOSFET. Introduction Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc) have been the front runners in the quest for an ideal power electronic switch. Ever since the invention of the transistor, the development of solid-state switches with increased power handling capability has been of interest for expending the application of these devices. The BJT and the GTO thyristor have been developed over the past 30 years to serve the need of the power electronic industry. Their primary advantage over the thyristors have been the superior switching speed and the ability to interrupt the current without reversal of the device voltage. All bipolar devices, however, suffer from a common set of disadvantages, namely, (i) limited switching speed due to considerable redistribution of minority charge carriers associated with every switching operation; (ii) relatively large control power requirement which complicates the control circuit design. Besides, bipolar devices can not be paralleled easily. The reliance of the power electronics industry upon bipolar devices was challenged by the introduction of a new MOS gate controlled power device technology in the 1980s. The power MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The new device promised extremely low input power levels and no inherent limitation to the switching speed. Thus, it opened up the possibility of increasing the operating frequency in power electronic systems resulting in reduction in size and weight. The initial claims of infinite current gain for the power MOSFET were, however, diluted by the need to design the gate drive circuit to account for the pulse currents required to charge and discharge the high input capacitance of these devices. At high frequency of operation the required gate drive power becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area of the device cross section which increases with the blocking voltage rating of the device. Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred khz.

62 From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement type. Both of these can be either n- channel type or p- channel type depending on the nature of the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gate-source voltage characteristics (transfer characteristics).

63 G D I D G D I D G D D I D I D G S S S S I D I D I D I D VGS VGS VGS VGS n-channel depletion type p-channel depletion type n-channel enhancement p-channel enhancement MOSFET MOSFET type MOSFET type MOSFET (a) (b) Fig 6.1: Different types of power MOSFET. Circuit symbols and transfer characteristics Photograph of n-channel enhancement type MOSFET. From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of the n-channel variety) is more popular for power electronics applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b) shows the photograph of some commercially available n-channel enhancement type Power MOSFETs.

64 4.1 Constructional Features of a Power MOSFET POWER MOSFETS: It has three terminals called drain (D), source(s), and Gate (G) It is a unipolar device because its operation depends on flow of majority carriers only. It has high input impedance in the order of ohm. It does not have the problem of secondary breakdown. It is current controlled device In the symbol the arrow indicates the direction of current flow. If the arrow points inward it is N-channel, points outward means P- channel. Types of MOSFETS: 1. Depletion MOSFET N channel D MOSFET P channel D MOSFET 2. Enhancement MOSFET N channel D MOSFET P channel D MOSFET Among the types N channel Enhancement MOSFET is commonly used because of high mobility of electrons. Basic structure of N Channel MOSFET On n+ substrate n- layer is epitaxially grown. Its thickness determines the voltage blocking capability. On other side of n+ substrate a metal layer is deposited to form drain terminal. Now p regions are diffused in epitaxially grown n- layer,further n+ layer regions are diffused in p region. As before SiO2 layer is added, which is then etched so as to fit metallic contact for source and gate.

65 Operation: When gate circuit is open junction between n+ below drain and p-substrate is reverse biased by input voltage V DD No current flow from drain to source and load. When gate is made positive as shown in fig. an electric field is established. Induced negative charges are formed below SiO2 layer and causing the p- layer below gate become an induced n layer. Due to this induced n layer the current flow from drain to source. If V GS is made more positive, induced n layer become deeper and hence more current flow from D to S.

66 4.2 Static characteristics of MOSFET: Transfer Characteristic: It is the graph between I D and V GS. VGST is the threshold voltage. It is the minimum voltage between gate and source to induce n channel. Thus below this voltage the device cannot conduct. This voltage is in the order of 2 3 V Output or V I characteristic: I t shows the variation of I D with respect to V DS. With V GS as a parameter. For low values of V DS the graph is almost linear, this indicates constant value of on resistance. If we increase the V DS this characteristics will be flat. An it indicates that I D is almost constant. Is called active region If we draw a load line it intersects the curve at A and B, at this point MOSFET operates as a switch. 4.3 Switching or Dynamic Characteristics of MOSFET:

67 Turn - on process: Turn on time is defined as the sum of delay time rise time of the device. During turn on delay time t dn period the input capacitance of the device charges to gate threshold voltage V GST and the drain current is zero. During rise time t r gate voltage rises to V GSP, which is the gate source peak voltage. This voltage drives the device into on state. Now the drain current I D rises from zero. t on = t dn + t r Turn off process: This process can be initiated by removing the gate sources voltage V GS at a time t 1.the turn off time is the sum of turn off delay time t df and fall time. During turn off delay time capacitance discharges from over drive gate voltage V 1 to V GSP but I D doesn t a change. During fall time the input capacitance again discharges from V GSP to V GST, now the drain current falls to zero. When V GS V GST MOSFET turn off. Drive circuit for MOSFET:

68 o When Vg is positive Q 2 turned ON, so pulse transformer dotted poles become positive. o D 1, D 2 will forward bias and charge the input capacitor of the MOSFET and turn ON it. o During this D 2 is ON, the emitter base junction of Q 1 reverse biased and it become OFF. o When Vg is made zero, Q 2 turn off and the dotted pole of the pulse transformer become negative. o D 1, D 2 will reverse bias and switched off. In turn Q 1 pull down through R 3. o The charges on input capacitance of the MOSFET make the emitter base junction of Q 1 forward bias and turn ON. o Now the input capacitance of the MOSFET discharges through Q 1 & turn OFF. 4.4 MOSFET protection circuit: di/dt protection: The di/dt can be limited by using a small inductor in series with the MOSFET. It is shown in fig.

69 dv/dt protection: (Snubber circuit) A snubber circuit is series combination of resistance & capacitance. It is connected in parallel with MOSFET. It is mainly used to protect the dv/dt. The RC circuit acts as low pass filter, so that the circuit is provided across the thyristor and it will absorbs the high transient voltage. The value of R is very small so that the capacitor will absorb the transient very quickly. Some times also generates large voltage transients. This voltage variation also suppressed by snubber circuit. The capacitor is short for ratio. Difference between MOSFET and BJT: Sl.No. MOSFET BJT 1 Low switching loss High switching loss 2. More conduction loss Low conduction loss 4. Unipolar device Bipolar device 5. It operates MHz frequency range It operates KHz frequency range 6. It has positive temperature co efficient. It has negative temperature co efficient. 7. Secondary breakdown does not occur Secondary breakdown occur 8. Available in the range of 550V,140A Available in the range of 1200V,800A 9. High input Impedance High output Impedance

70 Questions for Practice: Fill in the blanks i. A MOSFET is a controlled carrier device. ii. iii. iv. Enhancement type MOSFETs are normally devices while depletion type MOSFETs are normally devices. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of. The MOSFET cell embeds a parasitic in its structure. v. The gate-source voltage at which the layer in a MOSFET is formed is called the voltage. vi. The thickness of the layer remains constant as gate source voltage is increased byond the voltage. Answer: (i) voltage, majority; (ii) off, on; (iii) SiO 2, (iv) BJT, (v) inversion, threshold; (vi) depletion, threshold. Summary: MOSFET is a voltage controlled majority carrier device. A Power MOSFET has a vertical structure of alternating p and n layers. The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n + type semiconductor. The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO 2. p type semiconductor body separates n + type source and drain regions. A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel. The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. Switching times of a MOSFET can be controlled completely by external gate drive design.

71 5.0 Gate Turn Off Thyristor(GTO) Objective: We will be able to constructional features of a GTO The turn off mechanism of a GTO. The switching characteristics of a GTO. The block diagram of a GTO gate drive unit and the functions of different blocks. Introduction The thyristor has reigned supreme for well over two decades in the power electronics industry and continues to do so at the very highest level of power. It, however, has always suffered from the disadvantage of being a semi-controlled device. Although it could be turned on by applying a gate pulse but to turn it off the main current had to be interrupted. This proved to be particularly inconvenient in DC to AC and DC to DC conversion circuits, where the main current does not naturally becomes zero. A bulky and expensive commutation circuit had to be used to ensure proper turning off of the thyristor. The switching speed of the device was also comparatively slow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor (GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made a rather late entry (1973) into the thyristor family the technology has matured quickly to produce device comparable in rating (5000V, 4000Amp) with the largest available thyristor. Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and DC to DC converter circuits. Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ from conventional thyristor in that, they are designed to turn off when a negative current is sent through the gate, thereby causing a reversal of the gate current. A relatively high gate current is need to turn off the device with typical turn off gains in the range of 4-5. During conduction, on the other hand, the device behaves just like a thyristor with very low ON state voltage drop. Several different varieties of GTOs have been manufactured. Devices with reverse blocking capability equal to their forward voltage ratings are called symmetric GTOs. However, the most poplar variety of the GTO available in the market today has no appreciable reverse voltage (20-25v) blocking capacity. These are called Asymmetric GTOs. Reverse conducting GTOs (RC-GTO) constitute the third family of GTOs. Here, a GTO is integrated with an anti-parallel freewheeling diode on to the same silicon wafer. This lesson will describe the construction, operating principle and characteristic of Asymmetric GTOs only.

72 Constructional Features of a GTO Fig 5.1 shows the circuit symbol and two different schematic cross section of a GTO. A Anode Short. p + n p + n p Anode Contact p + J 1 n n Layer Buffer n - G p J 3 n K (a ) G G J n n n p C (b) (c) Fig. 5.1: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol, (b) Anode shorted GTO structure, (c) Buffer layer GTO structure. C Like a thyristor, a GTO is also a four layer three junction p-n-p-n device. In order to obtain high emitter efficiency at the cathode end, the n + cathode layer is highly doped. Consequently, the break down voltage of the function J 3 is low (typically 20-40V). The p type gate region has conflicting doping requirement. To maintain good emitter efficiency the doping level of this layer should be low, on the other hand, from the point of view of good turn off properties, resistively of this layer should be as low as possible requiring the doping level of this region to be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to optimize current turn off capability, the gate cathode junction must be highly interdigitated. A 3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a accessed via a common contact. The most popular design features multiple segments arranged in concentric rings around the device center. The maximum forward blocking voltage of the device is determined by the doping level and the thickness of the n type base region next. In order to block several kv of forward voltage the doping level of this layer is kept relatively low while its thickness is made considerably higher (a few hundred microns). Byond the maximum allowable forward voltage either the electric field at the main junction (J 2 ) exceeds a critical value (avalanche break down) or the n base fully depletes, allowing its electric field to touch the anode emitter (punch through). The junction between the n base and p+ anode (J 1 ) is called the anode junction. For good turn on properties the efficiency of this anode junction should be as high as possible requiring a heavily doped p+ anode region. However, turn off capability of such

73 a GTO will be poor with very low maximum turn off current and high losses. There are two basic approaches to solve this problem. In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make contact with the same anode metallic contact. Therefore, electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. This is the classic anode shorted GTO structure as shown in Fig 5.1 (b). Due to presence of these anode shorts the reverse voltage blocking capacity of GTO reduces to the reverse break downvoltage of junction J 3 (20-40 volts maximum). In addition a large number of anode shorts reduces the efficiency of the anode junction and degrades the turn on performance of the device. Therefore, the density of the anode shorts are to be chosen by a careful compromise between the turn on and turn off performance. In the other method, a moderately doped n type buffer layer is juxtaposed between the n - type base and the anode. As in the case of a power diode and BJT this relatively high density buffer layer changes the shape of the electric field pattern in the n - base region from triangular to trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in a conventional anode shorted GTO structure would have increased the efficiency of the anode shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection. This is called the Transparent emitter structure and is shown in Fig 5.1 (c). 5.2 Operating principle of a GTO GTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can be explained in a manner similar to that of a thyristor. In particular, the p-n-p-n structure of a GTO can be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerative configuration as shown in Fig 5.2.

74 p A I A A i B p n p n n n ic1 ic2 p p n I G p p n G G ib2 n Hole current n p Hole current Electron Electron I G K current C A current C C (a (b) ) p A G Fig 5.2: Current distribution in a GTO (a) During turn on; (b) During turn off. From the two transistor analogy (Fig 5.2 (a)) of the GTO structure one can write. i C1 = p I A + I CBO1 i B1 = i C 2 = n I k + I CBO2 I k = I A + I G and I A = i B1 + i C1 n I G + i CBO1 + i CBO2 Combinin g I A = p n With applied forward voltage V AK less than the forward break over voltage both I CBO1 and I CBO2 are small. Further if I G is zero I A is only slightly higher than (I CBO1 + I CBO2 ). Under this condition both n and p are small and ( p + n ) <<1. The device is said to be in the forward blocking mode. To turn the device on either the anode voltage can be raised until I CBO1 and I CBO2 increases by avalanche multiplication process or by injecting a gate current. The current gain of silicon transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes a momentary increase in the emitter current can be used to turn on the device. Normally, this is done by injecting current into the p base region via the external gate contract. As n + p approaches unity the anode current tends to infinity. Physically as n + p nears unity the device starts to regenerate and each transistor drives its companion into saturation. Once in saturation, all junctions assume a forward bias and total potential drop across the device becomes approximately equal to that of a single p-n diode. The anode

75 current is restricted only by the external circuit. Once the device has been turned on in this manner, the external gate current is no longer required to maintain conduction, since the regeneration process is self-sustaining. Reversion to the blocking mode occurs only when the anode current is brought below the holding current level. To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode. The holes injected from the anode are, therefore, extracted from the p base through the gate metallization into the gate terminal (Fig 5.2 (b)). The resultant voltage drop in the p base above the n emitter starts reverse biasing the junction J 3 and electron injection stops here. The process originates at the periphery of the p base and the n emitter segments and the area still injecting electron shrinks. The anode current is crowded into higher and higher density filaments in most remote areas from the gate contact. This is the most critical phase in the GTO turn off process since highly localized high temperature regions can cause device failure unless these current filaments are quickly extinguished. When the last filament disappears, electron injection stops completely and depletion layer starts to grow on both J 2 and J 3. At this point the device once again starts blocking forward voltage. However, although the cathode current has ceased the anode to gate current continues to flow (Fig 5.2 (b)) as the n base excess carriers diffuse towards J 1. This tail current then decays exponentially as the n base excess carriers reduce by recombination. Once the tail current has completely disappeared does the device regain its steady state blocking characteristics. Anode Shorts (or transparent emitter) helps reduce the tail current faster by providing an alternate path to the n base electrons to reach the anode contact without causing appreciable hole injection from anode. Questions for Practice: Fill in the blanks: 1. A GTO is a controlled carrier device. 2. A GTO has layers and terminals. 3. A GTO can be turned on by injecting a gate current and turned off by injecting a gate current. 4. The anode shorts of a GTO improves the performance but degrades the performance. 5. The reverse voltage blocking capacity of a GTO is small due to the presence of. Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v) anode shorts.

76 5.3 Steady state and dynamic characteristics of a GTO Steady state output and gate characteristics + VAK - I A I A I G - + v g I G Min Ma x I L VBRR I L VBRF VAK v g (a) (b ) Fig. 5.3: Steady state characteristics of a GTO (a) Output characteristics; (b) Gate characteristics. This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.3 (a). However, the latching current of a GTO is considerably higher than a thyristor of similar rating. The forward leakage current is also considerably higher. In fact, if the gate current is not sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable anode current. It should be noted that a GTO can block rated forward voltage only when the gate is negatively biased with respect to the cathode during forward blocking state. At least, a low value resistance must be connected across the gate cathode terminal. Increasing the value of this resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (20-30 V) reverse break down voltage. This may lead the device to operate in reverse avalanche under certain conditions. This condition is not dangerous for the GTO provided the avalanche time and current are small. The gate voltage during this period must remain negative. Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curves reflects parameter variation between individual GTOs. These characteristics are valid for DC and low frequency AC gate currents. They do not give correct voltage when the GTO is turned on with high dia dt and di G dt. V G in this case is much higher.

77 5.4 Dynamic characteristics of a GTO i A, V AK di V D dt I L V DM 0.9I L 0.9V D V D to N 0.1V D I g Vg t d t r dig/d t IGM V T I G 0.1I L t s t f ttail Itail t i g V d R L I L di/dt limitin g L t v g VgR QgQ IgQ di gq dt Fig. 5.4: Switching characteristics of a GTO. Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching circuit shown on the right hand side. When the GTO is off the anode current is zero and V AK = V d. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A substantial gate current ensure that all GTO cathode segments are turned on simultaneously and within a short time. There is a delay between the application of the gate pulse and the fall of anode voltage, called the turn on delay time t d. After this time the anode voltage starts falling while the anode current starts rising towards its steady value I L. Within a further time interval t r they reach 10% of their initial value and 90% of their final value respectively. t r is called thecurrent rise time (voltage fall time). Both t d and maximum permissible on state di A dependent. High value of I gm and dig dt dt are very much gate current at turn on reduces these times and increases maximum permissible on state di A dt. It should be noted that large value of i g (I gm )and dig dt are required during t d and t r only. After this time period both v g and i g settles down totheir steady value. A minimum ON time period t ON (min) is required for homogeneous anode current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its rated anode current.

78 To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With the application of the negative bias the gate current starts growing in the negative direction. However, the anode voltage,current or the gate voltage does not change appreciably from their on state levels for a further time period called the storage time (t s ). The storage time increases di gq with the turn off anode current and decrease with dt. During storage time the load current at the cathode end is gradually diverted to the gate terminal. At the end of the storage time gate current reaches its negative maximum value I gq. At this point both the junctions J 2 & J 3 of the GTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltage starts rising towards their final value while the anode current starts decreasing towards zero. At the end of current fall time t f the anode current reaches 10% of its initial value after which both the anode current and the gate current continues to flow in the form of a current tail for a further duration of t tail. A GTO is normally used with a R-C turn off snubber. Therefore, V AK does not start to rise appreciably till t f. At this point V AK starts rising rapidly and exceeds the dc voltage V d (V dm ) (due to resonance of snubber capacitor with di dt setting limiting inductor) before down at its steady value V d. A GTO should not be retriggered within a minimum off period off (min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gain in the range of GTO gate drive circuit A GTO gate drive has to fulfill the following functions. b) Turn the GTO on by means of a high current pulse (I GM ) c) Maintain conduction through provision of a continuous gate current (I G, also known as the back-porch current ). d) Turn the GTO off with a high negative gate current pulse. e) Reinforce the blocking state of the device by a negative gate voltage. A typical gate drive arrangement for a large power GTO is show in Fig 5.5.

79 Outpu H.F.DC to H.F. AC to DC t AC INV. H.F TXF Rectifier Stage A B C D E F Optical Contr Fiber optic ol Logic cable Electrical Optical - Electrical Converter (a) + A R 1 R 2 C 2 + ON T 1 - G OFF T 2 - (b) - R 3 + K Fig. 5.5: Gate drive circuit of a GTO. = Block diagram, = Circuit diagram of the output stage In the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kvs between the master control and individual gate units. The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic cables. These optical signals are converted to electrical signals by a optical electrical converter. These electrical signals through the control logic then produces the ON and OFF signal for the out put stage which in turn sends positive and negative gate current to the GTO. Depending on the requirement the control logic may also supervise GTO

80 conduction by monitoring the gate-cathode voltage. Any fault is relayed back via fiber optic cable to the master control. Power supply for the Gate drive units are derived from a common power supply through a high frequency SMPS (Blocks A, B & C) arrangement. Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T 1 sends positive gate pulse to the GTO gate. At the instant of turn on of T 1,C 2 acts almost as a short circuit and the positive gate current is determined by the parallel combination of R 1 and R2. However, at steady state only R 1 determines the gate current I G. The bottom switch T 2 is used for biasing the GTO gate negative with respect to the cathode. Since, relatively large negative gate current flows during turn off, no external resistance is used in series with T 2. Instead, the ON state resistance of T 2 is utilized for this purpose. In practice, a large number of switches are connected in parallel to obtain the required current rating of T 2. A low value resistance R 3 is connected between the gate and the cathode terminals of the GTO to ensure minimum forward blocking voltage. Questions for Practice: Fill in the blanks: 1. The current and forward current of a GTO are considerably higher compared to a thyristor. 2. If the gate current is insufficient a GTO can operate as a low gain. 3. Reverse blocking voltage of GTO is small. 4. To ensure that all GTO cathode segments are turned on simultaneously the magnitude of the current should be. 5. High value of gate current and dig/dt enhances the capability of a GTO during turn on. 6. During storage time the load current in a GTO is diverted from the to the terminal. 7. GTOs have low turn off gain. 8. After the current fall time during turn off of a GTO the anode current continuous for some more time in the form of a. 9. The gate drive unit of a GTO should provide continuous positive gate during ON period and continuous negative gate during OFF period. 10. In the gate drive unit of a GTO a low value resistance is connected between the gate and the cathode terminals to ensure minimum voltage. Answer: (1) transistor; (2) asymmetric; (3) gate, high; (4) di/dt; (5) cathode, gate; (6) current; (7) current tail; (8) current, voltage; (9) forward blocking.

81 5.6 GTO Ratings Steady state voltage and current rating V DRM : It is the maximum repetitive forward voltage the GTO can block in the forward direction assuming line frequency sinusoidal voltage waveform. It is important to note that GTO can block rated voltage only if the gate is reverse biased or at least connected to the cathode through a low value resistance. Manufactures usually provide the forward voltage withstanding capacity of the GTO as a functions of the gate cathode reverse voltage (and /or resistance) for a given forward dv dt. V RRM : It is the maximum repetitive reverse voltage the GTO is able to withstand. For all asymmetric GTOs this value is in the range of V, since it is determined by the gate cathode junction break down voltage. Due to the anode shorted structure of the GTO the anode base junction (J 1 ) does not block any reverse voltage. Unlike V DRM, V RRM rating may be exceeded for a short time without destroying the device. This reverse avalanche capability of the GTO is useful in certain situations as explained in Fig 5.6. VG1 V D VG1 IG1 I L V D IG1 G 1 D 1 VG1 t I L IG1 ID2 VG2 G 2 (a) V D VG2 D 2 ID2 Vfr > VRRM (b) I L t Fig. 5.6: Reverse avalanche capability of a GTOVoltage source inverter phase leg; Voltage, current waveforms. In the voltage source inverter phase leg shown in Fig 5.6 (a), as the GTO G 1 is turned off the current through it (I G1 ) starts reducing. The difference current (I L - I G1 ) is transferred to the snubber capacitance of G 1 and the voltage across G 1 (V G1 ) starts increasing. When if becomes equal to the dc link voltage V D, D 2 is forward biased. However, due to the forward recoveryvoltage of D 2 (V fr ) the reverse voltage across G 2 may exceed V RRM rating of G 2 and drive it into reverse avalanche. This condition is not dangerous for G 2 provided the avalanche time andcurrent are small (typically within 10 s and 1000 A respectively). However, the gate voltage must remain negative during this time.

82 V DC : This is the maximum continuous DC voltage the device can withstand. Exceeding this voltage does not immediately lead to device failure, but the probability of a cosmic radiation failure increases progressively with the applied dc voltage. IFAVM and I FRMS : These are maximum average and RMS on state current respectively. They arespecified at a given case temperature assuming half wave sinusoidal on state current at power frequency. I FSM : This is the maximum allowed peak value of a power frequency half sinusoidal nonrepetitive surge current. The pulse is assumed to be applied at an instant when the GTO is operating at its maximum junction temperature. The voltage across the device just after the surge should be zero. i 2 dt : This is the limiting value of the surge current integral assuming half cycle sine wave surge current. The junction temperature is assumed to be at the maximum value before the surge and the voltage across the device following the surge is assumed to be zero. The i 2 t rating of a semiconductor fuse must be less than this value in order to protect the GTO. Plots of both I FSM and i 2 dt as functions of surge pulse width are usually provided by the manufacturer. V F : This is the plot of the instantaneous forward voltage drop vs instantaneous forward current at different junction temperatures. P av : For some frequently encountered current waveforms (e.g. sine wave, square wave) the plot of the average on state power dissipation as a function of the average on state current is provided by the manufacturers at a given junction temperature. I H : This is the holding current of the GTO. This current, in case of a GTO 1, is considerably higher compared to a similarly rated thyristor. Serious problem may arise due to anode current variation because the GTO may un-latch at an in appropriate moment. This problem can be avoided by feeding a continuous current into the gate (called the back porch current) during ON period of the device. This DC gate current should be about 20% higher than the gate trigger current (I GT ) at the lowest expected junction temperature. di : This is the maximum permissible value of the rate of change of forward current during dt crit turn on. This value is very much dependent on the peak gate current magnitude and the rate of increase of the gate current. A substantial gate current ensures that all GTO cathode segments are ON simultaneously and turned within a short time so that no local hot spot is created.

83 Th e d i g dt and I gm values specified in the operating conditions should, therefore, be considered as minimum values. 5.7 Gate specification I g vs V g : It is a plot of instantaneous gate current as a function of the gate voltage. This characteristic is valid for DC and low frequency AC gate currents. They do not define the di g gatevoltage when the GTO is turned on from high anode voltage with high di/dt and dt. Vg in thiscase is much higher. Generally the gate cathode impedance of a GTO is much lower than that of a conventional thyristor. V gt, I gt : I gt is the gate trigger current and V gt, the instantaneous gate cathode voltage when I gt is flowing into the gate. I gt has a strong junction temperature dependence and increases very rapidly with reduced junction temperature. I gt merely specifies the minimum back porch currentnecessary to turn on the GTO at a low di dt in conduction. and maintain it V grm : It is the maximum repetitive reverse gate voltage, exceeding which drives the gate cathode junction into avalanche breakdown. I grm : It is the peak repetitive reverse gate current at V grm and T j (max). I gqm : It is the maximum negative turn off gate current. The gate unit should be designed to deliver this current under any condition. It is a function of turn off anode current, di g dt during turn off and the junction temperature. 5.8 Specifications related to the switching performance: t d, t r, : These are turn on delay time and anode voltage fall time respectively. Both of them can di di g and I gm for a given turn on anode voltage, current and be reduced with higher dt dt. t on (min) : This is the minimum time the GTO requires to establish homogeneous anode current. This time is also necessary for the GTO to be able to turn off its rated anode current. E ON : It is the energy dissipated during each turn on operation. Manufacturers specify them as functions of turn on anode current for different turn on di/dt and anode voltage E ON reduces with increased I gm.

84 I Fgqm : It is the maximum anode current that can be repetitively turned off by a negative gate current. It can be increased by increasing the value of the turn off snubber capacitance which limits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase I Fgqm. t s : The storage time t s is defined as the time between the start of negative gate current and the decrease in anode current. High value of the turn off anode current and junction temperature increases it while a large negative dig/dt during turn off decreases it. t f : This is the anode current fall time. It can not be influenced much by gate control. t off (min) : This is the minimum off time before the GTO may be triggered again by a positive gate current. If the device is re-triggered during this time, localized turn on may destroy it. E off : This is the energy dissipated during each turn off operation of the GTO. E off increases with increase in the turn off anode current and junction temperature while it reduces with turn off snubber capacitance. Questions for Practice: Fill in the blanks: 1 A GTO can block rated forward voltage only when the gate is biased with respect to the. 2 A GTO can operate in the reverse region for a short time. 3 The holding current of a GTO is much compared to a thyristor. 4 After a current surge the voltage across a GTO should be reduced to. 5 The gate cathode impedance of a GTO is much compared to a thyristor. 6 The turn on di/dt capability of a GTO can be increased by in creasing the magnitude of the gate current and during turn on. 7 The turn on delay time and current rise time of a GTO can be reduced by increasing the gate current and during turn ON. 8 The maximum anode current that can be turned off repetitively can be increased by increasing the turn off snubber and negative.

85 Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller;(vi) peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt. Summary: GTO is a four layer, three terminal current controlled minority carrier device. A GTO can be turned on by applying a positive gate current pulse when it is forward biased and turned off by applying a negative gate current. A GTO has a shorted anode and highly inter-digitized gate cathode structure to improve the gate turn off performance. Due to the presence of anode shorts a GTO can block only a small reverse voltage. These are called asymmetric GTOs. The forward i-v characteristics of a GTO is similar to that of a thyristor. However, they have relatively larger holding current and gate trigger current. The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate current and large rate of rise of the gate current. GTOs have relatively low turn off current gain. 6.0 Insulated Gate Bipolar Transistor (IGBT) Objectives We will be able to Constructional features, operating principle and characteristics of Insulated Gate Bipolar Transistors (IGBT) Differentiate between the constructional features of an IGBT and a MOSFET. Draw the operational equivalent circuit of an IGBT and explain its operating principle in terms of the schematic construction and the operational equivalent circuit. the steady state output and transfer characteristics of an IGBT. the switching characteristics of an IGBT and identify its differences with that of a MOSFET. Design a basic gate drive circuit for an IGBT.

86 Introduction: The introduction of Power MOSFET was originally regarded as a major threat to the power bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were diluted by the need to design the gate drive circuit capable of supplying the charging and discharging current of the device input capacitance. This is especially true in high frequency circuits where the power MOSFET is particularly valuable due to its inherently high switching speed. On the other hand, MOSFETs have a higher on state resistance per unit area and consequently higher on state loss. This is particularly true for higher voltage devices (greater than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg. SMPS). With the discovery that power MOSFETs were not in a strong position to displace the BJT, many researches began to look at the possibility of combining these technologies to achieve a hybrid device which has a high input impedance and a low on state resistance. The obvious first step was to drive an output npn BJT with an input MOSFET connected in the Darlington configuration. However, this approach required the use of a high voltage power MOSFET with considerable current carrying capacity (due to low current gain of the output transistor). Also, since no path for negative base current exists for the output transistor, its turn off time also tends to get somewhat larger. An alternative hybrid approach was investigated at GE Research center where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However, this device was also not a true replacement of a BJT since gate control was lost once the thyristor latched up. After several such attempts it was concluded that for better results MOSFET and BJT technologies are to be integrated at the cell level. This was achieved by the GE Research Laboratory by the introduction of the device IGT and by the RCA research laboratory with the device COMFET. The IGT device has undergone many improvement cycles to result in the modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics for high voltage (> 100V) medium frequency (< 20 khz) applications. This device along with the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT completely. 6.1 Constructional Features of an IGBT Vertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTs are possible n channel devices are more common and will be the one discussed in this lesson.

87 Emitter Gate SiO 2 SiO 2 (Gate oxide) n + n - (Gate oxide) p Body region J 3 Drain drift - J 2 n region J 1 n + Buffer layer + Injecting p layer Collector Fig. 7.1: Vertical cross section of an IGBT cell. The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers into it. The n type drain layer itself may have two different doping levels. The lightly doped n-region is called the drain drift region. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J 2 ) of the device. However, it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. This construction of the device is called Punch Trough (PT) design. The Non-Punch Through (NPT) construction does not have this added n+ buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. However, it does so at the cost of lower reverse break down voltage for the device, since the reverse break down voltage of the junction J 1 is small. The rest of the construction of the device is very similar to that of a vertical MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) emitter (n+ type) structure. The doping level and physical geometry of the p type body region however, is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT device. The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig 7.2(a). The constituent p-n-p transistor, n-p-n transistor and the driver MOSFET are shown by dotted lines in this figure. Important resistances in the current flow path are also indicated.

88 Gate Emitter Drift resistanc MOSFET n-p-n + n J 3 p Body spreading resistance p-np e n - J 2 n + p + J 1 (a) Collector Drift region resistance Collector Drift region resistance Collector Gate Body spreading resistance Gate Emitter (c) (b) Fig. 7.2: Parasitic thyristor in an IGBT cell. Schematic structure Exact equivalent circuit. Approximate equivalent circuit Emitter Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top p-n-p transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and the p type body layer as the collector. The lower n- p-n transistor has the n+ type source, the p type body and the n type drain as the emitter, base and collector respectively. The base of the lower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due to imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower n-p-n transistor. If the output current is large enough, the voltage drop across this resistance may forward bias the lower n-p-n transistor and initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. A major effort in the development of IGBT has been towards prevention of latch up of

89 the parasitic thyristor. This has been achieved by modifying the doping level and physical geometry of the body region. The modern IGBT is latch-up proof for all practical purpose. Fig 7.3(a) and (b) shows the circuit symbol and photograph of an IGBT. C E (a) (b ) G Questions for Practice: Fill in the blanks Fig. 7.3: Circuit symbol of an IGBT. 2. Circuit symbol. 3. Photograph. i. i. An IGBT is a device combining the advantages of a and a. ii. IGBT is suitable for voltage iii. frequency applications. In an IGBT cell structure a type injecting layer is added on top of the drain of an n channel MOSFET. iv. The forward blocking voltage of an IGBT is determined by the and of the drain drift layer. v. A punch through IGBT has reverse break down vi. voltage while the Non punch through IGBT has voltage blocking capacity. The IGBT cell has a parasitic structure embedded into it. vii. The parasitic structure of an IGBT cell can at large collector current due to imperfect body emitter shorting. viii. The doping level and physical geometry of the IGBT region is designed to be considerably different from that of a MOSFET to prevent its. Answers: i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low, symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.