CM1293A. 2 and 4-Channel Low Capacitance ESD Protection Arrays

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1 2 and 4-Channel Low Capacitance ES Protection rrays Product escription The CM1293 family of diode arrays has been designed to provide ES protection for electronic components or subsystems requiring minimal capacitive loading. These devices are ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ES channel consists of a pair of diodes in series that steer the positive or negative ES current pulse to either the positive (V P ) or negative (V N ) supply rail. Zener diode is embedded between V P and V N which helps protect the V CC rail against ES strikes. The CM1293 protects against ES pulses up to ±8 kv contact discharge) per the IEC Level 4 standard. This device is particularly well suited for protecting systems using high speed ports such as USB2.0, IEEE1394 (FireWire, i.link), Serial T, VI, HMI, and corresponding ports in removable storage, digital camcorders, V RW drives and other applications where extremely low loading capacitance with ES protection are required in a small package footprint. Features Two and Four Channels of ES Protection Provides ES Protection to IEC ±8 kv Contact ischarge Low Loading Capacitance of 2.0 pf Max Low Clamping Voltage Channel I/O to I/O Capacitance 1.5 pf Typical Zener iode Protects Supply Rail and Eliminates the Need for External By Pass Capacitors Each I/O Pin Can Withstand over 1000 ES Strikes* These evices are Pb Free and are RoHS Compliant pplications VI Ports, HMI Ports in Notebooks, Set Top Boxes, igital TVs, LC isplays Serial T Ports in esktop PCs and Hard isk rives PCI Express Ports General Purpose High Speed ata Line ES Protection *Standard test condition is IEC level 4 test circuit with each pin subjected to ±8 kv contact discharge for 1000 pulses. ischarges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. SOT 143 SR SUFFIX CSE 318 CH1 V P V N CM SR CM SO CH2 SC 74 (Pb Free) MSOP 10 (Pb Free) CH4 MRKING IGRM XXX M V P CH3 CH1 V N CH2 CM MR ORERING INFORMTION evice Package Shipping CM SR SOT ,000 / (Pb Free) Tape & Reel CM SO CM MR SC 74 SO SUFFIX CSE 318F BLOCK IGRM XXX M XXX = Specific evice Code M = ate Code = Pb Free Package (*Note: Microdot may be in either location) MSOP 10 MR SUFFIX CSE 846E 3,000 / Tape & Reel 4,000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BR8011/. Semiconductor Components Industries, LLC, 2012 July, 2012 Rev. 8 1 Publication Order Number: CM1293/

2 Table 1. PIN ESCRIPTIONS PCKGE/PINOUT IGRM 2 Channel, 4 Lead SOT143 4 Package (CM SR) Pin Name Type escription 1 V N GN Negative Voltage Supply Rail 2 CH1 I/O ES Channel 3 CH2 I/O ES Channel 4 V P PWR Positive Voltage Supply Rail 2 Channel, SC 74 Package (CM SO) Pin Name Type escription 1 NC No Connect 2 VN GN Negative Voltage Supply Rail 3 CH1 I/O ES Channel 4 CH2 I/O ES Channel 5 NC No Connect 6 VP PWR Positive Voltage Supply Rail 4 Channel, 10 Lead MSOP 10 Package (CM MR) Pin Name Type escription 1 CH1 I/O ES Channel 2 NC No Connect 3 V P PWR Positive Voltage Supply Rail 4 CH2 I/O ES Channel 5 NC No Connect 6 CH3 I/O ES Channel 7 NC No Connect 8 V N GN Negative Voltage Supply Rail 9 CH4 I/O ES Channel 10 NC No Connect Top View V N (1) V P (4) CH1 (2) VN (2) CH1 (3) CH1 NC V P CH2 NC Lead SOT143 4 Top View 2 Channel SC 74 Top View 10 Lead MSOP 10 CH2 (3) NC (1) VP (6) NC (5) CH2 (4) NC CH4 V N NC CH3 2

3 SPECIFICTIONS Table 2. BSOLUTE MXIMUM RTINGS Parameter Rating Units Operating Supply Voltage (V P V N ) 6.0 V Operating Temperature Range 40 to +85 C Storage Temperature Range 65 to +150 C C Voltage at any Channel Input (V N 0.5) to (V P + 0.5) V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STNR OPERTING CONITIONS Parameter Rating Units Operating Temperature Range 40 to +85 C Package Power Rating SOT143 4 Package (CM SR) SC 74 Package (CM SO) MSOP 10 Package (CM MR) mw Table 4. ELECTRICL OPERTING CHRCTERISTICS (Note 1) Symbol Parameter Conditions Min Typ Max Units V P Operating Supply Voltage (V P V N ) V I P Operating Supply Current (V P V N ) = 3.3 V 8.0 V F iode Forward Voltage Top iode Bottom iode I F = 8 m, T = 25 C V I LEK Channel Leakage Current T = 25 C, V P = 5 V, V N = 0 V ±0.1 ±1.0 C IN Channel Input Capacitance t 1 MHz, V P = 3.3 V, V N = 0 V, V IN = 1.65 V 2.0 pf C IO Channel I/O to I/O Capacitance 1.5 pf V ES ES Protection Peak ischarge Voltage at any Channel Input, in System Contact ischarge per IEC Standard Human Body Model, MIL ST 883, Method 3015 T = 25 C (Notes 2 and 4) T = 25 C (Notes 3 and 4) ±8 ±15 kv V CL Channel Clamp Voltage Positive Transients Negative Transients T = 25 C, I PP = 1, t P = 8/20 S (Note 4) V R YN ynamic Resistance Positive Transients Negative Transients T = 25 C, I PP = 1, t P = 8/20 S (Note 4) ll parameters specified at T = 40 C to +85 C unless otherwise noted. 2. Standard IEC with C ischarge = 150 pf, R ischarge = 330, V P = 3.3 V, V N grounded. 3. Human Body Model per MIL ST 883, Method 3015, C ischarge = 100 pf, R ischarge = 1.5 k, V P = 3.3 V, V N grounded. 4. These measurements performed with no external capacitor on V P. 3

4 PERFORMNCE INFORMTION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of C IN vs. V IN (f = 1 MHz, V P = 3.3 V, V N = 0 V, 0.1 F Chip Capacitor between V P and V N, 25C) Figure 2. Typical Variation of C IN vs. Temp (f = 1 MHz, V IN = 30 mv, V P = 3.3 V, V N = 0 V, 0.1 F Chip Capacitor between V P and V N ) 4

5 PERFORMNCE INFORMTION (Cont d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 Environment) Figure 3. Insertion Loss (S21) vs. Frequency (0 V C Bias, V P = 3.3 V) Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V C Bias, V P = 3.3 V) 5

6 PPLICTION INFORMTION esign Considerations In order to realize the maximum protection against ES pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ES protection device. Refer to Figure 5, which illustrates an example of a positive ES pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L 1 and L 2. The voltage V CL on the line being protected is: V CL = Fwd voltage drop of 1 + V SUPPLY + L 1 x d(i ES ) / dt+ L 2 x d(i ES ) / dt where I ES is the ES current pulse, and V SUPPLY is the positive supply voltage. n ES current pulse can rise from zero to its peak value in a very short time. s an example, a level 4 contact discharge per the IEC standard results in a current pulse that rises from zero to 30 mps in 1 ns. Here d(i ES )/dt can be approximated by I ES /t, or 30/(1x10 9 ). So just 10 nh of series inductance (L 1 and L 2 combined) will lead to a 300 V increment in V CL! Similarly for negative ES pulses, parasitic series inductance from the V N pin to the ground rail will lead to drastically increased negative voltage on the line being protected. The CM1293 has an integrated Zener diode between V P and V N. This greatly reduces the effect of supply rail inductance L 2 on V CL by clamping V P at the breakdown voltage of the Zener diode. However, for the lowest possible V CL, especially when V P is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 μf ceramic chip capacitor be connected between V P and the ground plane. s a general rule, the ES Protection rray should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V P pin of the Protection rray as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ES device to minimize stray series inductance. V P L 2 POSITIVE SUPPLY RIL V CC 0.22 F ONE CHNNEL 2 1 L 1 PTH OF ES CURRENT PULSE I ESO CHNNEL INPUT 25 LINE BEING PROTECTE V CL SYSTEM OR CIRCUITRY BEING PROTECTE V N 0 GROUN RIL CHSSIS GROUN Figure 5. pplication of Positive ES Pulse between Input Channel and Ground 6

7 PCKGE IMENSIONS SOT 143 CSE ISSUE U E1 e E GUGE PLNE L2 ETIL L SETING PLNE NOTES: 1. IMENSIONING N TOLERNCING PER SME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. MXIMUM LE THICKNESS INCLUES LE FINISH. MINIM UM LE THICKNESS IS THE MINIMUM THICKNESS OF BSE MTERIL. 4. IMENSIONS N E O NOT INCLUE MOL FLSH, PRO TRUSIONS, OR GTE BURRS. MOL FLSH, PROTRUSIONS, N GTE BURRS SHLL NOT EXCEE 0.25 PER SIE. IMENSION E1 OES NOT INCLUE INTERLE FLSH OR PROTRUSION. INTERLE FLSH N PROTRUSION SHLL NOT EXCEE 0.25 PER SIE. 5. IMENSIONS N E1 RE ETERMINE T TUM H. 6. TUMS N B RE ETERMINE T TUM H. b1 e1 1 B TOP VIEW SIE VIEW 3X b 0.20 M C -B c C SETING PLNE 0.10 C H ETIL EN VIEW c MILLIMETERS IM MIN MX b b c E E e 1.92 BSC e BSC L L BSC RECOMMENE SOLERING FOOTPRINT* X X 0.54 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 7

8 PCKGE IMENSIONS SC 74 CSE 318F 05 ISSUE N SCLE 2:1 H E E NOTES: 1. IMENSIONING N TOLERNCING PER NSI Y14.5M, CONTROLLING IMENSION: INCH. 3. MXIMUM LE THICKNESS INCLUES LE FINISH THICKNESS. MINIMUM LE THICKNESS IS THE MINIMUM THICKNESS OF BSE MTERIL F 01, 02, 03, 04 OBSOLETE. NEW STNR 318F (0.002) e 1 b L C MILLIMETERS INCHES IM MIN NOM MX MIN NOM MX b c E e L H E SOLERING FOOTPRINT* SCLE 10:1 mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 8

9 PCKGE IMENSIONS MSOP 10, 3x3 CSE 846E 01 ISSUE O SYMBOL MIN NOM MX b c E E1 E E e 0.50 BSC L L1 REF L2 θ 0.25 BSC 0º 8º ETIL TOP VIEW 2 c EN VIEW 1 e b SIE VIEW L2 Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) Complies with JEEC MO-187. ETIL L1 L FireWire is a registered trademark of pple Computer, Inc. i.link is a trademark of Sony Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORERING INFORMTION LITERTURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative CM1293/

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