A Novel GGNMOS Macro-Model for ESD Circuit Simulation

Transcription

1 Chinese Journal of Electronics Vol.18, No.4, Oct A Novel GGNMOS Macro-Model for ESD Circuit Simulation JIAO Chao and YU Zhiping (Institute of Microelectronics, Tsinghua University, Beijing , China) Abstract A novel macro-model for ESD circuit with only five fitting parameters is proposed. In this model a new topology and a new multiplication factor equation are proposed as well as the extracting method. This modeling approach greatly reduces time and effort required for circuit design while making use of GGNMOS (Gate-grounded NMOS) as ESD (Electrostatic discharge) protection, which is widely used for integrated circuits to protect IOs and power rails. The DC characteristics of GGNMOS and transient behavior of GGNMOS under HBM (Human body model) stress are simulated using both our macro-model and two-dimensional device simulator, Taurus (Synopsys). Good agreement has been obtained. Key words Gate-grounded-NMOS, Electrostatic discharge, ESD modeling, Human body model, Snapback. I. Introduction Electrostatic discharge (ESD) is one of the most significant reliability concerns for modern integrated circuits. But the circuit models for devices working under ESD condition are still not widely available. This lack of suitable SPICE (Simulation program with integrated circuit emphasis) models impedes circuit designers effort in performing of entire circuit when ESD protection devices are present. With deep-sub-micron CMOS integrated circuit processes, the most popular device for ESD protection circuit is GGN- MOS. Because of the existence of snapback behavior in its DC characteristics, it is rather challenging in developing an accurate and robust circuit model. The snapback effect is, however, essential for ESD protection devices to discharge the excess power efficiently. Several works on compact modeling of ESD devices with emphasis on the snapback effects have been reported [1 5]. In Refs.[1 4] compact models are based on BSIM3. Although these models can characterize ESD devices correctly, the parameter extraction for these models is extremely difficult because of the complexity in BSIM3 parameters. In Ref.[5], a compact model for SCR (Silicon controlled rectifier) is provided. This macro-model contains a nonlinear resistor which is implemented using three pieces of linear functions, and smoothing functions have to be used to ensure the continuous derivatives of the I-V characteristics. Moreover, the convergence is poor while used in circuit without manual intervention. In recent years, Technology computer-aided design (TCAD) s of ESD elements have been accomplished to assess GGNMOS and SCRs [6,7], which has been verified that the TCAD can be used to characterize the ESD devices including both DC and transient behaviors. Therefore, the ESD device data from TCAD tools is used to verify the device modeling approach. For the device under HBM stress, the circuit and device mixed mode is used [8]. In this paper we propose a new macro-model for GGN- MOS. Because of the new proposed topology, it has only five fitting parameters and the parameter extraction is with ease. A new multiplication factor equation is introduced and integrated in the model. The model can be implemented into SPICE using the enhanced MNA (Modified nodal analysis) method [9] to improve its convergence property. Simulation results using this macro-model of DC and transient characteristics of GGNMOS are presented. The results are compared with those from using the device tool Taurus, and good agreement is achieved. II. Operational Principle of GGNMOS ESD Devices GGNMOS devices have snapback behavior in its I V characteristics. The key snapback element of the GGNMOS for ESD protection is the parasitic NPN bipolar transistor. GGN- MOS is a two-terminal configured NMOS with the gate and substrate connected to source; hence the base of the parasitic NPN is connected to the emitter through substrate resistance (Fig.1). When a big enough drain voltage is applied to a GGN- MOS which is initially in its off state, the FET together with the parasitic NPN bipolar transistor undergoes from increasing drain current to eventually an avalanche breakdown. The high electric field in the depletion region of drain-substrate junction induces avalanche current, which grows exponentially with the drain voltage. This avalanche current flows to the ground terminal through the substrate, driving the parasitic NPN base voltage up to a turn-on voltage (about 0.7V). After the parasitic NPN is turned on, the dynamic (i.e. incremental) resistance of the GGNMOS becomes negative in value, Manuscript Received Jan. 2008; Accepted May This work is supported by the National Natural Science Foundation of China (No ).

2 A Novel GGNMOS Macro-Model for ESD Circuit Simulation 631 and the snapback process happens. This snapback effect, with its low-voltage drop and high on-current, can efficiently discharge large amount of electrostatic charges on the device s drain contact. and holding current i h1, and the last is the turn-on resistance r on. Fig. 1. Cross-section of an NMOS transistor configured as GGNMOS showing the parasitic NPN transistor Fig. 3. Schematic of the DC model for ESD protection devices with snapback characteristics, where v av is the voltage drop in i av, v b and i b are the diode voltage and current respectively, r on is the turn on resistance, and g b represents the substrate conductance Shown in Fig.3, our model contains only one diode i b (Eq.(1)), one dependent source i av (Eq.(2)), and two constant resistors r on and g b. In the following equations, v av and v b is shown in Fig.3, V t is the thermal voltage, i s, k m, and v m are fitting parameters. M is the proposed multiplication factor equation and is detailed in the next section. ( ( ) ) vb i b = i s exp 1 (1) This expression is the diode rule, where i s is reverse saturation current. V t Fig. 2. I V characteristic of GGNMOS and the four features considered in our model III. The Proposed GGNMOS Macro-Model The proposed macro-model is based on the physical observation on the above GGNMOS operation principle. When a circuit is in its normal operation region, GGNMOS for ESD protection is in off state. When ESD stress occurs, voltage applied to the drain of GGNMOS rises rapidly. Avalanche breakdown will occur at the drain-substrate junction once V ds exceeds the breakdown voltage V t1. The drain-substrate junction break-down current can be modeled by a dependent current source i av which counts in the avalanche effect. The substratesource junction is a diode. The substrate resistance between the portion of substrate, which is at the drain-substrate junction, and that the source-substrate junction is denote by g b. The resistance of the drain side r on represented the main resistance after the GGNMOS breaks down. Fig.3 is the schematic of the model proposed. D denotes the drain, S the source and B the substrate. There are four features (Fig.2) on the ESD I V curve, which have been carefully considered in our model, first is the trigger point including trigger voltage v t1 and trigger current i t1, second is the snapback slope, third is the holding point including holding voltage v h1 i av = Mi b (2) M = exp[k m(v av v m)] exp( k mv m) + 1 (3) 1. Multiplication factor The multiplication factor is often written in the following form [2] : 1 M = ( ) (4) A 1 A exp 2 V d V dsat where A 1 and A 2 are fitting parameters, V dsat is the saturation voltage for MOSFET, and V d is voltage applied to drain. At low V d, M is close to 1. The drawback of Eq.(4) is convergence problems when it is implemented to circuit simulator. As V d approaches to V dsat the singularity problem occurs. In Ref.[10] the multiplication factor is improved to the expression: M = exp(k 1(V d V dsat v 1)) + exp(k 2(V d V dsat v 2)) (5) where k 1, k 2 and v 1, v 2 are fitting parameters. Although this expression can overcome the convergence problem, it introduced two more parameters which increases extract difficulty. We using the expression in Eq.(3), where the number of fitting parameters is reduce to only 2, and the accuracy is also guaranteed. Fig.4 is the comparison among the three expression. For Eq.(4), as the drain voltage approaches break down voltage the multiplication factor reaches infinity quickly which causes the SPICE simulator fail with singularity errors. Eqs.(5) and (3) both have the same trend as Eq.(4). And they both can

3 632 Chinese Journal of Electronics 2009 overcome the convergence problems since they are exponential functions. The little difference between Eqs.(5) and (3) are at the low apply voltage region. But the difference between Eqs.(5) and (3) can be neglected, because the ESD device is in its off state during low V d, Fig. 4. Multiplication factor vs. drain voltage, multiplication factor is in log scale. Figures for Eqs.(3), (4), and (5) for ESD MOS with v t1 = 6.0V are shown 2. Parameter extraction There are five parameters, which have to be extracted in this model. They are r on, g b, i s, k m, and v m. r on is the turnon resistance and it is extracted from the slope of the line in Fig.2. g b reflects the snapback slope in the I-V curve and its value can be calculated using Eq.(6). g b = i h1 i t1 v t1 v h1 (6) where i s represents the reverse saturation current due to diffusion of holes. The expression for i s can be found from the basic bipolar model [11], it is given by Eq.(7) i s = q n2 i A E D p N E L pe (7) where n i is the intrinsic concentration, A E is the effective emitter area of the parasitic transistor, D p is the effective diffusion constant for holes in the emitter, N E is the emitter concentration, and L pe is the hole diffusion length. After assuming the turn-on voltage v on 0.7V for the diode, the value for k m and v m can be calculated using Eqs.(8) and (9) v m = v h1 v on (8) k m = ln it1 + von/vt v t1 v m (9) IV. Results and Discussion We simulated the GGNMOS with different channel length using two-dimensional device Simulator Taurus and compared the TCAD results with that of our model. Good agreement is obtained. The cross-section of the simulated device is shown in Fig.5. The substrate, source and gate are connected to ground, and drain is the ESD stress input. The comparison between our model and the simulated data is demonstrated in Fig.6 to Fig.8 which represents the snapback I-V characteristics of GGNMOS with different channel length. The GGNMOS in Fig.6 has the channel length of 0.13µm, in Fig.7 has the channel length of 0.18µm and in Fig.8 has the channel length of 0.25µm. It is clearly found that our model can accurately describe snapback behaviors of the GGNMOS under ESD events. Fig. 5. The GGNMOS structure for two-dimensional device It is found that the trigger voltage decreases with reduced gate length. So is the holding voltage. The model developed can precisely describe the four features demonstrated in Fig.2. Since our model has only five parameters needed to be extracted, the parameter extraction process is extremely straightforward. Because SCR devices have the analogous I V curve with GGNMOS, our model can also be easily applied to SCRs. The characteristics of GGNMOS device under HBM stress are also compared between Taurus and our model. The schematic is shown in Fig.9. Fig. 6. Snapback I V characteristics of 0.13µm from our model and device Fig. 7. Snapback I V characteristics of 0.18µm from our model and device Fig. 8. Snapback I V characteristics of 0.25µm from our model and device

4 A Novel GGNMOS Macro-Model for ESD Circuit Simulation 633 Fig. 9. 2kV HBM stress sub-circuit for Spice and Taurus A 2kV HBM stress is performed to the drain of GGNMOS ESD protection device. The results are shown in Fig.11. Symbolic is the result simulated using Taurus, and line is simulated using our model. To catch the transient characteristics of the GGNMOS device, capacitors are added to our model. There are two capacitors that affect the transient process. First is the gate-substrate capacitance, and then is the gate-drain capacitance (Fig.10). The effect of capacitance is noticeable only when the current of the device is small that is before the GGNMOS is turned on. And therefore the capacitance for C gd and C gb when the drain voltage equals zero can be used in this model. For gate-substrate capacitance, it can be calculate using the equation C gb = W LC ox. For gate-drain capacitance, it mainly consists of gate-drain overlap capacitance and can be calculate by C gd = 0.6X jw C ox [12]. Where C ox is the gate capacitance per unit area, W is gate width, L is gate length, and X j is the junction depth of drain/source. Fig.11 shows the results of our model and Taurus. It is clear that before the applied voltage reached the trigger voltage v t1, the two results make a good matched. After the device triggered on, the device exhibits NDR (Negative dynamic resistance) and it undergoes a non-quasi-static process, then the results can vary because of a very small parasitic value. So the results of this region are not very reliable both for our model and Taurus. When GGNMOS passed its NDR region, the applied voltage continued to increase, and it is found in Fig.11 that the two results matched again. The results shown in Fig.11 and Fig.12 demonstrate that the model give good agreement with the Taurus in the reasonable regions. Fig. 10. Transient model of GGNMOS and its combination with cross-section of MOSFET V. Conclusion A macro-model that consists of only one diode, one dependent current source, and two resistors, is proposed. Due to the new proposed topology, it has only five parameters that have to be extracted, and the parameter extraction is straightforward. In this model, a new multiplication factor equation is introduced. The new equation reduces the number of fitting parameters for multiplication factor from 4 to 2. This modeling approach can improve the design efficiency for making use of GGNMOS as ESD protection circuit. The new macro-model can precisely describe the I-V curve for GGNMOS. The transient for the drain side of GGNMOS under HBM stress is performed, and a good agreement is achieved in the reasonable region. That means by adding the expected capacitors the model can describe the transient characteristics of GGNMOS as well. References [1] X.F. Gao, J.J. Liou, J. Bemier, G. Croft and A. Ortiz-Conde, Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Fig. 11. Comparison of Taurus results and our model, they are transient voltages on the drain of ESD MOS device during 2kV HBM pulse Fig. 12. Comparison of Taurus results and our model, they are transient currents on the drain of ESD MOS device during 2kV HBM pulse Systems, Vol.21, No.12, pp , [2] A. Amerasekera, S. Ramaswamy, M.C. Chang and C. Duvvury, Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current s, Proc. of IEEE International Reliability Physics Symposium, Dallas, Texas, USA, pp , [3] Y. Zhou, D. Connerney, R. Carroll and T. Luk, Modeling MOS snapback for circuit-level ESD using BSIM3 and VBIC models, Proc. of International Symposium on Quality of Electronic Design (ISQED), San Jose, CA, USA, pp , [4] J. Li, S. Joshi, R. Barnes and E. Rosenbaum, Compact modeling of on-chip ESD protection devices using Verilog-A, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.25, No.6, pp , [5] P.A. Juliano and E. Rosenbaum, A novel SCR macromodel for ESD circuit, Proc. of International Electron Devices Meeting (IEDM), Washington, D.C., USA, pp , [6] J.A. Salcedo, J.J. Liou, L. Zhiwei and J.E. Vinson, TCAD methodology for design of SCR devices for electrostatic discharge (ESD) applications, IEEE Transactions on Electron Devices, Vol.54, No.4, pp , [7] H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, A.Z.H. Wang and R. Gafiteanu, A mixed-mode ESD protection circuit -design methodology, IEEE Journal of Solid-State

5 634 Chinese Journal of Electronics 2009 Circuits, Vol.38, No.6, pp , [8] Taurus Device User Guide, Synopsys, Inc., USA, [9] C. Jiao and Z. Yu, A robust novel techniqe for SPICE of ESD snapback characteristics, Chinese Journal of Electronics, Vol.17, No.1, pp.71 74, [10] S.L. Lim, X.Y. Zhang, Z. Yu, S. Beebe and R.W. Dutton, A computationally stable quasi-empirical compact model for the of MOS breakdown in ESD-protection circuit design, Proc. of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, USA, pp , [11] D.P. Kennedy and J.A. Phillips, Device Electronics for Integrated Circuits, John Wiley & Sons, New York, USA, [12] W. Liu, X. Jin, J. Chen, M.C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P.K. Ko and C. Hu, BSIM3v3.2.2 MOSFET Model Users Manual, University of California at Berkeley, USA, JIAO Chao received the B.S. degree from Tsinghua University, Beijing, China, in He is currently working toward the Ph.D. degree in microelectronics at Tsinghua University. His research interests include modeling and designing of electrostatic discharge devices especially in RFICs. ( jiaochao99@mails.tsinghua.edu.cn) YU Zhiping graduated from Tsinghua University, Beijing, China, in 1967 with B.S. degree. He received M.S. and Ph.D. degrees from Stanford University, Stanford, CA, USA in 1980, and 1985, respectively. He is presently a professor in the Institute of Microelectronics, Tsinghua University, Beijing, China. From 1989 to 2002, he has been a senior research scientist in the Department of Electrical Engineering in Stanford University, while serving as a faculty member in Tsinghua University. Between 2003 and 2005, he held Pericom (San Jose, USA) Microelectronics Professorship and from 2006 on (for three years) he holds Novellus (San Jose, USA) Microelectronics Professorship. His research interests include device for nanoscale MOSFETs, quantum transport in nanoelectronic devices, compact circuit modeling of passive and active components in RF CMOS, and numerical analysis techniques. Dr. Yu has published more than 200 technical papers and is the co-author of a book on TCAD (Technology CAD) in English. A co-authored book on RF CMOS circuit design (in Chinese) was published by Tsinghua University Press in He is a senior member of IEEE and served as the Associate Editor of IEEE Trans. CAD of IC & Systems (ICCAD) from 1996 to He is a member of Modeling and Simulation Subcommittee for IEDM. He serves as a member of IEEE EDS Nanotechnology Committee from 2006.