Chapter 2. Dynamic Body Bias Technique *

Transcription

1 Chapter 2 Dynamic Body Bias Technique * *The results of this chapter and some part of the introductory chapter have been published in the following papers: 1. Vandana Niranjan, Maneesha Gupta, Body Biasing-A circuit level approach to reduce leakage in Low power CMOS circuits, Journal of Active and Passive Electronic Devices, Old City Publishing Science, Philadelphia, USA, Vol.6, No.1-2, pp.89-99, Vandana Niranjan, Maneesha Gupta, An Analytical model of the Bulk-DTMOS transistor, Journal of Electron Devices, University of Perpignan, France,Vol.8, pp , 2010

2 Increasing demand for battery powered portable electronic devices has been the motivation towards lowering supply voltages and power consumption in mixed signal integrated circuits. This reduction in the supply voltage primarily affects the performance of analog circuits in terms of speed, linearity, dynamic range, noise, gain and bandwidth. In this chapter, dynamic body bias technique has been investigated to circumvent these limitations and improve the performance of circuits capable of operating under low supply voltage as low as 1 V. Various reported applications of dynamic body bias technique in analog circuits have been reviewed and triple-well CMOS technology, necessary for implementation of dynamic body bias technique is explained. A new small signal model of a dynamic body biased MOS transistor is proposed and modification in small signal parameters due to bias voltage is discussed. At the end, the effect of mobile charge carriers present in depletion region of a dynamic body biased MOS transistor has been studied with the help of proposed analytical model. 2.1 Introduction With the downscaling of the CMOS technology, the output resistance of a MOS transistor is decreasing due to the channel length modulation effect [69]. Therefore, the maximum achievable intrinsic gain of a MOS transistor in deep submicron CMOS technologies is becoming unsatisfactorily low as channel length is decreasing. In analog applications, it is possible to boost the transistor output resistance by setting the channel length of critical transistors two to four times the minimum allowed by the technology. But greater channel lengths lose the high bandwidth advantages offered by the advanced technology. Therefore, increasing the channel length in order to boost the intrinsic gain is not a viable solution. Another possible solution to increase the intrinsic gain is by increasing MOS transconductance which can be increased by increasing the aspect ratio but this increases the power dissipation and the increased parasitic capacitance limits the input/output swing. Due to the shrinking sizes of MOS transistor, it is necessary to lower the power supply voltage in order to ensure the device reliability. However, reduced supply voltage limits the input and output voltage swing capability of analog circuits. One of the possible solution to overcome the swing limitation is to lower the threshold voltage of the MOS transistor. Therefore, body bias approach can be very effective to improve the circuit swing. In this research work, dynamic body bias technique has been used to improve the performance of

3 analog circuits by reducing the threshold voltage and increasing the intrinsic gain of a MOS transistor. 2.2 Principle of Dynamic Body Bias Technique The idea of dynamic body bias technique was first introduced by J. Colinge, in 1987 in the form of a voltage controlled bipolar-mos transistor, in which the channel region is connected to the gate [71]. This was mainly aimed to improve the performance of on-chip analog functions as the device has enhanced current drive capability. Later the dynamic body biased MOS transistor was renamed as dynamic threshold MOS (DTMOS) due to the dynamic nature of its threshold voltage [39]. The threshold voltage of MOS transistor is not expected to decrease further than what is available today. As a result, mixed signal circuit designers face many limitations. This has led to many non conventional low voltage MOS transistor implementation techniques such as body/bulk-driven, floating-gate and quasi floating-gate to push the power supply voltage towards threshold voltage of the MOS transistor. But these techniques suffer from low transconductance, low transition frequency, higher noise, complex circuit structure and require more chip area. A conventional gate-driven technique is shown in Fig In the figure, MOS transistor M 1 is biased using biasing current I B and power supply voltage V DD and body terminal is at ground. As the input signal is applied to the gate terminal of MOS transistor, only gate transconductance (g m ) contributes to the conduction current. V DD I B V out V in M 1 Figure 2.1 Gate-driven technique

4 A non conventional body-driven technique [20] is shown in Fig The input signal is applied at the bulk/body terminal of the MOS transistor and a sufficient voltage is applied at the gate terminal to keep the transistor in the conductance region. As the gate terminal in body-driven MOS transistor is at ground for the input signal therefore, only bulk transconductance (g mb ) contributes to conduction current. Unfortunately, the transconductance of a body-driven transistor is only 30 % to 40 % that of a conventional gate-driven transistor [13]. V DD I B V out V in M 1 V GS Figure 2.2 Body-driven technique From Fig. 2.1 and Fig. 2.2, it is concluded that, if input signal is applied to the gate as well as body terminal simultaneously then both g m and g mb can contribute to the conduction current in a MOS transistor. Fig. 2.3 shows such a solution where, both gate and body terminals are tied together and used as signal input. By configuring the MOS transistor in this way, the threshold voltage of the MOS transistor becomes function of input signal. Any variations of the gate potential induce the same variations to the body potential and dynamically changes the threshold voltage due to body effect. Thus, due to dynamic body bias, both gate and body transconductances contribute to the conduction current and effective transconductance of the gate and body driven transistor becomes (g m + g mb ). In this research work, dynamic body bias technique is viewed as combination of gate driven and bulk/body driven techniques for a fair comparison with existing non conventional low voltage MOS transistor implementation techniques. The idea of utilizing both terminals came from the

5 requirement of increasing the effective transconductance of a MOS transistor for low voltage analog applications requiring these features. V DD I B V out V in M 1 Figure 2.3 Gate and body driven technique Although source-body junction parasitic diode is slightly forward biased but any substantial conducting p-n junction current can be eliminated by limiting the gate input to one diode voltage. Dynamic body bias technique offers good perspectives as a low power and low voltage technique because it provides improvement of the following electrical characteristics for analog performance. Using dynamic body bias technique, the threshold voltage can be reduced by more than 25 % [56,63] Due to the reduced depletion region charge and lower effective normal field in the channel, the mobility of charge carriers in dynamic body biased MOS transistor is higher than conventional gate-driven MOS transistor [39]. Also, as the potential in the channel region is strongly controlled by two gates i.e the gate and body terminals, it leads to a high transconductance owing to faster current transport. The transconductance of DTMOS transistor is 30 % to 40 % higher as compared to conventional gate-driven MOS transistor. Dynamic body bias technique offers superior control over the short-channel effects such as drain-induced barrier lowering (DIBL), channel length modulation (CLM) and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOS transistors [72,73]. Therefore, the output and intrinsic gain of a MOS transistor can be improved using dynamic body bias

6 technique due to reduced channel length modulation effects. Narasimhulu et al. [82] have reported that single halo doping can further improve the intrinsic gain of a DTMOS transistor. The subthreshold swing is an important parameter in modeling the weak inversion regime of MOS transistor, especially for high gain analog applications, imaging circuits and low voltage applications. Subthreshold swing is defined as the change in the gate voltage required to reduce the subthreshold current by one decade [10]. Smaller the value of the swing, better is turn ON performance of MOS transistor. Using dynamic body bias technique, the ideal subthreshold swing of 60 mv/dec can be achieved as compared to 80 mv/dec in conventional gate-driven MOS transistor. This is due to the fact that input voltage is directly applied to the body terminal in DTMOS transistor whereas in gate-driven MOS input voltage is coupled capacitively to the body terminal [74]. Dynamic body bias technique overcomes the variations in drain current and transconductance due to the process, voltage and temperature deviations. The performance deviations across the process corners has been reported to get reduced to 12 % as compared to 77 % using dynamic body bias [75]. Thus, dynamic body bias technique can be effectively used to desensitize the circuit against the process, voltage and temperature variations. The term 'hot carriers' refers to electrons or holes in the body/substrate of a MOS device that have energies significantly above average. Hot carriers may be present as a result of very high fields in the drain region of a MOS transistor. They may compromise operation of the device by generating charged defects in the oxide layer and by degrading the oxide and the Si-SiO2 interface [76]. These effects constitute a reliability problem. Hot-carrier reliability in DTMOS transistor can be improved using indium super steep retrograde channel implantation [77]. The steady increase of environmental electromagnetic pollution has constantly raised the level of RF interference superimposed onto nominal signals in present day integrated circuits. Therefore, a high immunity to electromagnetic interference has consequently become a mandatory requirement for low voltage integrated circuits. Recently in 2013, op-amps using dynamic body

7 bias technique have been reported to be more immune to electromagnetic interference [78]. Dynamic body bias technique improves the cutoff and maximum oscillation frequency of a MOS transistor. The high frequency characteristics of DTMOS are described in [79]. Noise in DTMOS is 30 times lower and input referred noise is 10 times smaller than conventional gate-driven MOS transistor [80]. This makes it a competitive candidate for low noise RF applications. The temperature dependence of intrinsic small-signal parameters in a DTMOS are basically the same as those for the conventional gate-driven MOS transistor. The temperature effect on the DC characteristics of a DTMOS transistor has been investigated [83]. The transconductance increases with increase in temperature and cutoff frequency has positive temperature coefficient for low voltage applications ( < 0.5 V). 2.3 Applications of Dynamic Body Bias Technique in Analog Circuits A MOS transistor using dynamic body bias technique i.e. DTMOS transistor is an ideal device for low voltage analog applications due to its high drive current, small parasitic components, ideal subthreshold characteristics and improved short channel effects. The operation of DTMOS transistor was first reported for silicon-on-insulator (SOI) process technology in 1994 [39]. The main issue with SOI DTMOS is its high body resistance, leading to large RC delay in circuits. Also, it is difficult to achieve both low threshold voltage and low body resistance simultaneously in SOI DTMOS. Many solutions have been proposed in the literature to reduce this delay such as nonuniform doping, reduction of device width etc. However, RC delay remains an inherent problem of SOI DTMOS [84]. This diverted the circuit designers to prefer bulk DTMOS as compared to SOI DTMOS. In 1996, first standard CMOS/bulk DTMOS transistor was reported by Kotaki et al. [38] which was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The most significant result of fabricating DTMOS transistor on bulk substrate is its reduced body resistance as compared to SOI substrate. A bulk DTMOS transistor has a layered shallow well structure in which a high concentration layer is sandwiched by low concentration layers to achieve excellent threshold voltage controllability without increase of body resistance. Aggressive technological improvements and

8 careful optimization of bulk DTMOS through junction-capacitance and wellresistance reduction has lead to impressive speeds even at a 0.3 V supply voltage [42]. For this research work, bulk DTMOS transistor has been preferred as compared to SOI DTMOS for low voltage analog circuits as the scalability of SOI process technology for analog performance provides no significant advantage over bulk process technology. SOI process has significantly diminished performance gain relative to bulk process for sub 100 nm technology nodes [85]. Self heating effects due to buried oxide layer, are much more apparent in SOI substrate than in bulk substrate due to poor thermal conductivity of the underlying buried oxide [86]. Therefore, SOI DTMOS temperature can rise dynamically many tens of degrees above ambient temperature during normal operation which can degrade the performance of circuits significantly. In SOI MOS transistor, the silicon film under channel region is electrically floating. This floating body causes the appearance of a kink in the output characteristics of the DTMOS which can seriously affect many SOI based analog circuits [87]. Therefore, use of DTMOS as part of a standard bulk process shows great promise for fabricating low voltage, low power and low cost integrated circuits. Many analog circuits such as A/D and D/A converters require voltage references. A bandgap reference is a voltage reference of which the output voltage is referred to the bandgap energy of the used semiconductor. The bandgap voltage reference is required to exhibit both high power supply rejection and low temperature coefficient and is probably the most popular high performance voltage reference used in integrated circuits today. However, IC design is now predominated by low power and low voltage objectives. With this aim, a low voltage low power bandgap reference circuit was first reported using bulk DTMOS transistor in 1999 by Anne-Johan [88]. This circuit runs at supply voltages down to 0.85 V while consuming only 1 μw. In 2006, Maymandi-nejad et al. [56] designed a low voltage, fully differential amplifier with a common mode feedback (CMFB) circuit and a low-voltage comparator, incorporating the bulk DTMOS transistor. In the case of CMFB, the DTMOS helps in reducing the circuit complexity without consuming extra power. Similarly, in the case of the comparator, the DTMOS makes it possible to get a rail-torail input range. However, the main limitation of the proposed applications are that they are specific to p-type DTMOS transistor.

9 Achigui et al. [57] in 2007, fabricated and tested a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier based on bulk DTMOS transistors. The fully differential opamp circuit makes use of the DTMOS transistor for reducing the threshold voltage of transistors and increase their overdrive voltage. Use of DTMOS transistor increases the input common mode range and results in better matching of transistors in the differential input stage as compared to conventional gate-driven MOS transistors. The reported operational amplifier operates at 1 V and is more suitable for low power and low noise applications. However, the main limitation is that only p-type DTMOS transistor has been used to take advantage of the maximum input range. Using triple-well option, n-type DTMOS transistors can improve the performance further. A bulk DTMOS based second generation current conveyor (CCII) circuit capable of operating under 0.4 V in the subthreshold region has been reported by Uygur [58]. The total power consumption of the CCII circuit is only 214 nw and use of DTMOS results in a very compact circuit topology, consisting of only four DTMOS transistors and four ordinary NMOS transistors. Recently in 2014, a voltage differencing transconductance amplifier operating in the subthreshold region has been reported [59]. Use of bulk DTMOS transistor in the amplifier enables ultra low voltage operation under ± 0.2 V symmetric supply voltages. The bulk DTMOS based voltage follower proposed in [60] can drive ± 0.25 V to the load of 500 Ω with the total harmonic distortion of 0.4 % at the operating frequency of 1 MHz. The circuit is developed using complementary source follower with a common-source output stage. The bandwidth and power dissipation of the voltage follower are 288 MHz and 103 μw respectively. Another recent reported application of bulk DTMOS transistor is class AB current differencing buffered amplifier [61]. This circuit is based on two low voltage current mirrors and voltage follower in which DTMOS transistor is employed as core device to enable low voltage operation at 0.7 V. A class AB current mirror using bulk DTMOS transistor is presented in [62]. The circuit is based on a conventional class AB current mirror structure with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and operates at low supply voltage of 0.7 V. Ehsan et al. [63] have designed OTA using weak inversion MOS transistors for biomedical applications, consuming only 386 nw. The proposed OTA utilizes DTMOS transistor to enable low voltage operation at 0.4 V whereas RHP zero

10 controlling techniques have been used for improving its unity gain bandwidth. Many OTA amplifiers have been reported in [64-67] and operational amplifiers in [68,69]. However in most of these applications, DTMOS has been used in the differential input stage to enable low voltage and low power operation. 2.4 Process Technology for Dynamic Body Bias Technique Several comparison studies in terms of performance have been reported for dynamic body biased MOS transistor fabricated on SOI versus bulk silicon substrates. The bulk DTMOS have advantages in terms of cost and defect density of silicon substrate, heat transfer and compatibility with conventional CMOS devices. Many techniques have been reported in the literature to obtain large body effect factor such as super-steepretrograde channel profile by using indium implantation [77] in DTMOS transistor. Highly doped body in a DTMOS transistor is effective for suppressing the short channel effect and reducing the body resistance however, a high body impurity doping induces an increase in threshold voltage. To overcome this limitation of high threshold voltage, strained SiGe layer in the channel region [89] has been reported as one of the effective solutions as mobile charge carriers have higher mobility in strained layer. Thus, strained SiGe layer can help to maintain both high body effect factor and low threshold voltage in a bulk DTMOS transistor. As discussed in previous section, dynamic body bias technique has been used only in p-type MOS transistor in reported analog circuits. The reason being that in bulk CMOS technology, the p-type substrate is common for all n-type MOS transistors. Therefore, n-type transistors cannot be operated as four-terminal devices because of their shared body connection with p-type substrate. In order to access the body terminal of individual n-type MOS transistor, each must have its own p-well. This requires an additional implant layer in fabrication process. This process is known as triple-well CMOS technology [90]. Therefore, using triple-well structure dynamic body bias technique can be implemented in both n-type and p-type MOS transistors in a circuit. To demonstrate the principle, a simplified cross section of MOS transistors using dynamic body bias technique is shown in Fig. 2.4 with terminals drain D, shorted gate and body G (B) and source S. A p-well is formed in a deep n-well, which in turn is formed on a p-type substrate. As compared to standard CMOS technology, an extra well is used for n-type and p-type MOS transistors which allows independent

11 control on the body terminal of individual MOS transistors. The main advantage of fabricating both types of transistors in separate wells is that extra thick N-isolation layer separates the individual p-well from the common p-substrate and thus avoids any excess current due to parasitic diodes. The layer also breaks the resistive path from any digital noise source on chip into the analog circuits. This is particularly helpful when using separate V DD and V SS for the digital and analog circuits. G ( B ) G ( B ) S D D S N+ P+ P+ SiO 2 N+ N+ P+ N-well P-well Deep N-well P-substrate Figure 2.4 Dynamic body bias technique implemented using triple-well CMOS technology Although triple-well structure involves additional fabrication cost but it is more robust to process and parasitic junction capacitance variations. A triple-well is more effective in reducing substrate noise and cross-talk in mixed systems-on-chip designs. In addition, the p-n junction capacitance associated with triple-well structures works as a decoupling capacitance and contributes to mitigation of the power supply noise. The total noise reduction of a triple-well structure is superior to that of a twin-well structure [91,92]. It is worth mentioning here that triple-well technology enables the possibility of biasing the p-well independently from the p-substrate. This offers an additional flexibility to circuit designers mainly due to the biasing of the p-well. The body potentials have to be routed to each well contact so in addition to power supply

12 potentials two more rails are required. This results in area overhead depending on technology node and specific layout rules. The triple-well technology is more reliable technology due to minimized latch-up. With regard to the parasitics in triple-well CMOS, it seems that they are comparable to the parasitics in standard CMOS. Recent CMOS processes normally provide a triple-well n-type MOS transistor option, which possesses independent body biasing capacity. Main advantages of using dynamic body bias technique in triple-well n-type MOS transistor includes Deep N-well provides better isolation of the DTMOS transistor, thus minimizing the noise level that could be coupled from nearby subcircuits. Better device isolation alleviates a potential latch-up problem. An n-type MOS transistor in a deep N-well offers reduction of the gate capacitance, offers higher intrinsic charge mobility relative to the p-type MOS transistor, resulting in higher cutoff frequency f T and maximum oscillator frequency f max. 2.5 Proposed Small Signal Model for Dynamic Body Biased MOS Transistor Analog circuit design is heavily dependent on using an accurate MOS model for predicting correct behavior of the designed circuit. Small signal modeling is the foundation of all analog circuit analysis. Circuit simulators requires highly accurate models which are very complex. Therefore, for pencil and paper design where simple hand calculations are needed, it is more convenient to use a dedicated small signal MOS model. This dedicated model leads to understanding and insight into circuit operation. From Eq. (1.7), it is seen that (2.1) It can be seen from Eq. (2.1) that, for all values of the gate input V GS > ψ s, circuit simulation program may fail to converge. Thus in a DTMOS transistor large errors can be expected for higher gate input voltage. Therefore, dynamic body bias technique is more suitable for ultra low voltage integrated circuits. A MOS transistor using dynamic body bias technique, i.e a DTMOS transistor is shown in Fig. 2.5 (a) and its proposed small signal model is shown in Fig. 2.5 (b). As both body and gate terminals are used as signal input, body terminal has important influence in its behavior. Many efforts have been done by the researchers to model

13 DTMOS transistor in [93-98] but most of the reported work is related to modeling for SOI DTMOS transistor. Drain Gate (Body ) Sourc Figure 2.5 (a) A MOS transistor using dynamic body bias technique R body +R gb C gd Drain Gate (Body) C body C bd C gs g m V gs g mb V gs r o Source Figure 2.5 (b) Proposed model of dynamic body biased MOS transistor Probably, for the first time, a small signal model for bulk DTMOS transistor has been proposed in this research work. The proposed small signal model is derived from standard MOS model [25] which has been modified to incorporate body-related parasitics. In the proposed model, there are two current generators which are controlled by the same gate voltage. In the model, the capacitances C gs, C gd, C bd are gate-source, gate-drain, and body-drain parasitic junction capacitances respectively. Due to gate and body connection, an additional parasitic capacitance and parasitic resistance associated with the body has been introduced and shown as C body and R body respectively in the proposed small signal model. Junction capacitances in DTMOS can

14 be reduced using sidewall elevated drains [38]. Thus, the effective input capacitance of a bulk DTMOS transistor is given by (2.2) The body of a MOS transistor has finite resistance and shown as R body in the model. Thus, the effective input resistance of bulk DTMOS transistor is given by (2.3) where R gb is gate-body contact resistance, which is mainly ohmic in nature and has a very small magnitude, therefore neglected for the frequencies targeted in this research work. The body contact provides the transistor a resistive path for charging/ discharging of the body. R body is proportional to gate width of DTMOS transistor and plays an important role in both DC & AC performance. If gate width is large then due to higher body resistance, body potential is not able to follow gate voltage. This results in lower operating speed and large power consumption in DTMOS based circuit. Therefore, body resistance must be minimized using various layout techniques such as folded gate finger and multi-finger pattern [99]. Body resistance affects the frequency response of analog circuits as it forms a pole with body capacitance which may affect gain. The typical values of the body sheet resistance for DTMOS transistor is nearly (1-10) KΩ per square. Body resistance can be further reduced using process and/or device optimization. In a DTMOS transistor, since source is not at the same potential as body, therefore this potential difference gives rise to a drain current component, which we shall write as g mb V BS. As gate and body terminals are shorted together, V BS = V GS is maintained all the time. Therefore, in a DTMOS transistor body effect can be modeled as controlled source g mb V GS. The drain current in terms of transconductance can be written as (2.4) From Eq. (2.4), the effective transconductance of a DTMOS transistor is given as (2.5)

15 Thus, DTMOS transistor exhibits an increased transconductance and drive current due to dynamic reduction of the threshold voltage. Quantitatively, the drain current of a bulk DTMOS transistor in strong inversion is given by (2.6) where all symbols have their usual meaning. In a DTMOS transistor, the amount of threshold voltage shift is closely related to the body effect factor given as [100] (2.7) where t ox is a gate oxide thickness, W dep is width of depletion layer under the channel and three is the ratio of permittivity of silicon to that of SiO 2. Therefore, from Eq. (2.7), it is concluded that high channel impurity concentration is effective in increasing body effect factor due to small depletion layer width. For the proposed small signal model, we define the unity gain frequency for the bulk DTMOS transistor as (2.8) In a MOS transistor, as gate bias increases, carriers moves upward to the Si/SiO2 interface and interact with the surface states under the gate oxide. This interaction is the main source of noise in a MOS transistor. However, in a DTMOS transistor, due to low transverse electric field, the interaction between carriers and surface states is reduced. Therefore, carriers flow far away from the Si/SiO2 interface and noise fluctuation influenced by surface state is low. This results in reduction of input referred noise as gate voltage increases. The input referred noise power spectral density for a DTMOS transistor is defined as (2.9) where i 2 ni is the total drain current generated by the noise sources. Thus, due to higher effective transconductance in a DTMOS transistor, the input referred noise power spectral density is low as compared to conventional gate-driven MOS transistor. A DTMOS transistor or in other words a gate and body driven transistor has many advantages over conventional gate-driven and bulk-driven MOS transistors.

16 Based on the proposed small signal model in Fig. 2.5, a comparison of relations for effective transconductance, threshold voltage, transition frequency and input referred noise of the gate and body driven MOS transistor with gate-driven and bulk-driven MOS transistors has been summarized in Table 2.1. Table 2.1 Comparison of gate and body driven transistor with gate-driven and bulkdriven transistors Type of MOS transistor Threshold Voltage requirement, V T Gate-driven E k O E8 5$ F O o 8 6 L8 6r (generally 8 5$ Lr) Effective Transcondu ctance C I Transition frequency, f T C I tł% CO Input referred noise, v 2 noise (f) t E JE Ct I Bulk/Bodydriven Removed from signal path C I> C I> tł:% >O E% >K@U t E JE t C I> Gate and Body driven/ Dynamic body biased/ DTMOS 8 6r E k O F8 )5 F O o Reduced when input signal is applied otherwise it s same as gate-driven MOS transistor for no input signal. C I EC I> Increased C I EC I> tł:% CO E% >K@U t E JE :C I EC I> ; t In summary, DTMOS transistor has lower threshold voltage, higher effective transconductance, lower input referred noise and higher transition frequency as compared to gate-driven and bulk-driven MOS transistor. For analog circuit design, DTMOS transistor offers several advantages such as In low voltage applications there is not much voltage headroom for signal swing and reducing the threshold voltage can be helpful. Therefore, using the dynamic body bias technique, it is possible to extend the input voltage range of a circuit. As source-body junction is forward biased, transverse electric field decreases thereby reducing the degradation of the carrier mobility. In a DTMOS transistor carrier mobility is higher because the depletion charge is reduced. Evidently higher mobility leads to a higher current drive capability which also improves the speed. DTMOS transistor exhibit lower noise and higher cutoff frequency.

17 DTMOS has lower output conductance for short gate lengths, which suggests that drain current saturates very well due to small channel length modulation effect [101]. Output resistance of a DTMOS increases due to suppression of short channel effects which results in an increased effective gate control of the channel charge. Therefore, the intrinsic gain of a DTMOS is very high as compared to MOS transistor of similar size. Using a dynamic body bias technique can be advantageous since it results in a simpler circuit without using additional circuitry for bias generation as compared to other body bias techniques. DTMOS has ideal subthreshold characteristics Although dynamic body bias technique has many advantages, it also has a few limitations, namely Due to body capacitance (C body ), the unity gain frequency of a DTMOS transistor is degraded slightly but higher transconductance compensates for this degradation. Since C body is only a small part of total capacitance in DTMOS, effect of total parasitic capacitances on cutoff frequency is comparable to that in a standard MOS transistor. Body-drain capacitor forms a miller capacitor in DTMOS transistor, is an issue important in RF analog circuits. Since input signal is applied at body terminal also, it is important to use a large amount of contacts to reduce body resistance since body resistance contributes to noise and degrades the frequency response. By keeping the gate width per finger small and using body contacts liberally, it is possible to minimize the effect of body resistance. The allowed range for input signal (typically less than 600 mv) is quite narrow. This is required to maintain the parasitic diodes in slightly 'cutoff' condition in order to avoid large parasitic currents inside the transistor body that would deteriorate the transistor performance. In order to get large dynamic range such as rail-to-rail voltage range, higher output swing and higher overdrive voltage, dynamic body bias technique is suitable for low voltage analog circuits design.

18 2.6 Effect of Mobile Charge Carriers in the Depletion Region As discussed in the previous section, the conventional MOS transistor circuit model, including body related small signal parameters, has been used to predict the response of dynamic body biased MOS transistor. It has to be noted that the circuit model of a conventional MOS transistor is developed under the assumption that the channel is free of mobile charge carriers, which is the total depletion approximation. While designing integrated circuits using dynamic body bias technique, it is essential to make use of a SPICE based simulator to quickly verify the analytically predicted circuit functionality. However, the accuracy of simulation is limited by the SPICE model BSIM3V3 used for simulation of bulk DTMOS based circuits. BSIM (Berkeley Short-Channel IGFET Model) is based on total depletion region approximation and completely neglects the influence of mobile carriers within the 'depletion layer' [102]. Thus expressions for the ionic charge density in addition to the inversion charge density do not consider the existence of mobile carriers in the depletion region. However, for a dynamic body biased MOS transistor, this is not the case because body-source junction is slightly forward biased due to which few mobile charge carriers are also present in body-source depletion region. Therefore threshold voltage given by Eq. (1.7), based on total depletion approximation might get violated by the presence of mobile carriers. In order to assess the effect of charge carriers on the operation of DTMOS transistor and level of accuracy of simulation results, an analytical drain current model is proposed by taking into account the presence of mobile charge carriers in bodysource junction. A bulk MOS transistor has parasitic BJT embedded in its structure as shown in Fig With an effective short circuit between the body and the source terminals, the parasitic BJT always remain in cutoff [71]. However, in a DTMOS transistor, source-body junction which is equivalent to the emitter-base junction of parasitic BJT, gets slightly forward biased if input signal increases. Therefore, the bipolar effect appears as the carriers injected from the source can be collected by the drain terminal. For considering the presence of mobile charge carriers in the depletion region, in the first order approximation, total current in a DTMOS transistor can be modeled as parallel combination of drain current in surface MOS transistor and collector current in parasitic BJT. In the analysis, it is assumed that the MOS current flows close to the channel surface and bulk-parasitic BJT current flows through the

19 Body Source Drain Gate p+ n+ n+ Figure 2.6 Parasitic BJT embedded in MOS transistor bulk region, thereby neglecting the interaction between these two currents. Thus the total drain current is expressed as (2.10) Electrostatic potential in a MOS transistor is shown in Fig Here, y is coordinate parallel to oxide surface of MOS transistor with y = 0 at the source terminal and x is coordinate directed into the semiconductor with x = 0 at the oxide semiconductor interface. U is defined as normalized electrostatic potential in the semiconductor, then U Source is the value of U at y = 0 that is at source terminal and U Drain is the value of U at y = L that is at drain terminal. Body Source Gate Drain y p+ n+ n+ x = J p substrate x Figure 2.7 Electrostatic potential in a MOS transistor

20 The first accurate and complete quantitative MOS transistor model was the Pao-Sah model [103]. Perhaps the Pao-Sah model is the most complete in the sense that it accounts for a two dimensional charge distribution without simplifications. As a result, both electrons and holes are allowed to exist in the depletion region and it is valid in all biasing regions including weak, moderate and strong inversion. Therefore, small signal equation of Pao-Sah model is more suitable for modeling mobile charge carriers in forward biased body-source junction in DTMOS transistor. Detailed step by step analysis is presented in appendix A and only important results are given here. In DTMOS transistor as body-source junction is forward biased and electrons are injected from source into the body, therefore these injected electrons also contribute to the total current. To take into account the effect of injected electrons, depletion region width is selected wider enough to consider mobile electrons. The total current in a DTMOS transistor is expressed as &6/ 15 B 9 J % KT D@8. ) -6 A:8 M 5. F8 5 ;F :8 5. F8 5 ; 8 $ B :7 &N=EJ F ;F :7 5KQN?A F ;F :7 &N=EJ F ; :7 5KQN?A F ; CE C B 9 J % KT. T - O A-6. - & kj LK oț :A F7 5KQN?A FA F7 &N=EJ ;C (2.11) K where, + /15 B 9 J % KT D@8. ) -6 A:8 M 5. F8 5 ;F :8 5. F8 5 ; 8 $ B :7 &N=EJ F ;F :7 5KQN?A F ;F :7 &N=EJ F ; :7 5KQN?A F ; CE C (2.12) and + $,6 B 9 J % KT. T - O A-6. - & kj LK oț :A F7 5KQN?A FA F7 &N=EJ ;C (2.13) K Eq. (2.13) represents collector current of BJT with source as the emitter and body as the base. Potentials at the source end of the channel and drain end of the channel respectively are given as 8 -6 M A:7 5KQN?A ; (2.14) 8 -6 M A:7 &N=EJ ; (2.15)

21 and X J is depletion region width, L D is intrinsic debye length, K o is oxide dielectric constant, x o is oxide thickness, K s is semiconductor dielectric constant, V' G is gate voltage and V B is the body voltage in the drain current model Eq. (2.11). Rest other symbols have their usual meaning. In summary, the Pao-Sah model has been extended so that it applies to a forward biased body-source junction, which for the first time justifies modeling of bulk DTMOS transistor as a parallel combination of the standard charge-sheet MOS transistor model and a bipolar transistor term. An expression has been derived where the purely MOS transistor drain current was distinguished and added to the purely BJT collector current. In this analytical drain current model, no integrals need to be evaluated numerically. However, the main limitation of the proposed model is that SPICE node list would have twice as many transistors as the original DTMOS circuit, which would be very expensive from the point of view of computer simulation time in SPICE simulator. 2.7 Result The core of the analytical model is Eq. (2.11). Using this equation the performance of the proposed model was studied for W = 10 μm, L = 1 μm, x o = 10 nm, N A = /cm 3 X J = 0.2 μm, n po = n i. The expected values were calculated by using the proposed drain current model and compared with SPICE model. The output current characteristics of DTMOS transistor using analytical model and SPICE model shown in Fig As observed from the result, there is some disagreement between the analytical and SPICE simulation for drain voltages less than about 70 mv. It is also seen from the results that as gate input voltage is increasing, proposed analytical model estimates a slightly higher drain current value as compared to SPICE model. This may be consequence of various approximations under which DTMOS drain current model has been derived. However, for drain voltages higher than 70 mv, both analytical and simulation results agrees well and shows the validity of the depletion approximation based SPICE model for simulating DTMOS based circuits. It is concluded from the results that the well known long channel model for threshold voltage is still valid for low forward biases (< 0.6 V) since the number of minority carriers at low forward biases is small. The proposed analytical drain current model for bulk DTMOS transistor does not include short channel effects, therefore it would be more accurate for submicron

22 40 30 V G = 0.3 V V G = 0.27 V IDTMOS (na) V G = 0.25 V V Drain (mv) Figure 2.8 DTMOS output current characteristics using analytical model (solid line) and SPICE simulation (dotted line) devices. Additionally, vertical drain-body and source-body junction currents, which has been neglected in this research work, add another dimension and this might require two dimensional DTMOS model for more accurate results. However, these can be neglected if the forward body bias voltage is kept below 0.6 V voltage level and the device channel length is not chosen very small to prevent short channel effects. Therefore, in circuit realizations, forward biased diode current do not effect much the operation of DTMOS transistor. 2.8 Conclusion Dynamic body bias technique offers good perspectives as a low power and low voltage technique because it provides improvement in electrical characteristics for analog performance. In order to get more dynamic range such as rail-to-rail voltage range, higher output swing and higher overdrive voltage, dynamic body bias technique is viable solution in low voltage analog circuits design. Using triple-well option in CMOS technology, it is possible to implement dynamic body bias technique in n-type and p-type MOS transistors. Triple-well option provides isolation of noise sensitive n- type MOS transistors in analog and RF circuits from digital n-type MOS transistors that collectively discharge significant current to the substrate and thus generate

23 'substrate noise'. Thus triple-well option is very beneficial for mixed-signal circuits as ever increasing integration densities can facilitate more complex systems-on-chip. The proposed small signal model for DTMOS transistor is efficient for analytical predictions in analog circuits. The operating range of the DTMOS transistor must be smaller than the turn-on voltage of the body-source p-n junction diode, which causes a remarkable current through the body terminal and increases power dissipation. It is relatively safe to use DTMOS transistor at low voltage applications more than other applications. At low voltage levels, mobile carrier concentrations do not reach high levels in modern highly doped substrates leading to high turn-on voltage of parasitic diodes in DTMOS transistor. The proposed formulations are useful for future integrated circuit design using DTMOS approach. It is important to note that compact model such as BSIM3V3 is still valid for less than 0.6 V forward biased body source junctions even those models assume the total depletion approximation. Under these voltage levels, free carriers in the channel are so small in numbers that their effects can be neglected in the operation of long channel DTMOS transistor. Therefore, BSIM3V3 model can be conveniently used for circuit simulation by selecting minimum channel length equivalent to long channel transistors. This approach predicts correct behavior of DTMOS transistor by preventing significant short channel effects.