Advanced Digital Design
|
|
|
- Johnathan Mills
- 5 years ago
- Views:
Transcription
1 Advanced Digital Design Limits of Synchonous Design by A. Steininger and M. Delvai Vienna University of Technology
2 recall Previous Conclusion The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 2
3 recall What we actually need When can SNK use its input? When it is valid and consistent SRC f(x) SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 3
4 recall Ideal Design Method An ideal design method minimizes power consumption miminizes circuit overhead naturally supports composability naturally aids testability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 4
5 Outline Timed Communication Model Control Flow Conditions Classification of Sychronous Design Benefits of Synchronous Design Problems with Synchronous Design Evaluation Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 5
6 Timed Comm.. Model Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 6
7 The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: t invalid,x > t safe,x μ src > - Δ invalid Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 7
8 The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: t cons,x > t snkrdy,x μ snk > - Δ snktrg Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 8
9 Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 9
10 Synchronous Philosophy If the problem originates from the time domain, why don t we solve it in the time domain! Process inputs only after they have become stable. Use clock to signal these instants. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 10
11 Control by Global Time Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 11
12 Synchronous Timing clock period active clock edge setup/hold window recovery from transients * clock to output delay * combinational delay * routing delay, HI LO Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 12
13 The Synchronous Concept FF1 f(x) FF2 T Clk After some TIME T clk FF2 can use f(x) s output and at the same time FF1 can apply a new input Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 13
14 The Implications Clock Period T Clk = Period π Must be determined by static timing analysis Phase ϕ = π (!) this implies that μ src = -(Δ snktrg + Δ cons still we must guarantee μ src > -Δ invalid therefore cons ) Δ invalid > Δ snktrg + Δ cons (issue condition) This is not formally safe but it works! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 14
15 Benefits of Sync. Logic Simplicity improves productivity design on high level of abstraction truth table with previous state transients are irrelevent, all considered states are clearly defined timing analysis separate, after design clear distinction between data and clock simplifies timing analysis Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 15
16 Benefits of Sync. Logic (2) High implementation efficiency: one single control signal for the complete system! periodic clock is easy to generate single-rail data coding minimum number of transitions on the data rails clock also provides a time base Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 16
17 Resume 1 Synchronous design does work billions of working designs Synchronous design is VERY efficient wrt. design wrt. implementation So everything is solved Is it? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 17
18 recall The Original Problem When can SNK use its input? When it is valid and consistent SRC f(x) SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 18
19 recall What have we done? We have expressed a simple information related condition by means of complicated timing related parameters that we don t even know! DOES IT MATTER? Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 19
20 That damned traffic light YES! It does matter Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 20
21 That damned Traffic light number of waiting cars Microwave oven temperature of the food Wiper visibility through the front shield Stairway light presence of a person in the stairway Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 21
22 What s wrong? Often events define important points in time. This does, however, not mean that the occurrence of the event can be a priori related to (absolute or relative) time. BUT: Time is relatively easy to measure Therefore it is often much more efficient to establish such an indirect relation than to observe the actual event (that is sometimes invisible) This starts to become annoying when the artificial relation between actual event and time model is too weak. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 22
23 The Synchronous Approach Relating flow control to time in this way is convenient and effective, but in fact the implied relation does not (naturally) exist! FF1 f(x) FF2 We need to establish this relation artificially during design (timing optimization & constraints) T Clk After some TIME T clk FF2 can use f(x) s output and at the same time FF1 can apply a new input Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 23
24 The annoying consequences need to determine clock period circuit functionality is technology dependent considerable design efforts,, large design loops need to make worst-case assumptions necessarily pessimistic no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems power consumption problems Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 24
25 recall Can we predict Delay? after synthesis: logic depth complexity of operation optimization & mapping after routing: interconnect geometrie (lengths, capacitances) vias, switches during operation: actual values process variations temperature supply voltage Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 25
26 Timing Analysis not possible before the end of the design flow (large iteration loops!) Specification Validation Design-Entry Behavioral Simulation Synth. & Technol.-Mapping Prelayout-GL-Simulation Partitioning & Placement Routing Postlayout-GL-Simulation Manufact. Test Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 26
27 Timing Analysis not possible before the end of the design flow (large iteration loops!) tight & safe esti- mation has become a major issue sync model transients reality setup/hold Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 27
28 Timing Analysis not possible before D the end of the FF1 CLK design flow D (large iteration FF2loops!) CLK tight & safe esti- D FFk mation has become CLK a major issue t PD,CLK combin. logic t dly,data,1m feasible with ideal clock net only t dly,data,2m original idea: avoid having to deal with transients current practice: timing analysis most difficult D CLK FFm t dly,data,km Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 28
29 Worst-Case Assumptions normally too pessimistic real, chip could run faster no tolerance when exceeded graceful degradation desirable Η(α) α lim α Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 29
30 ! Performance Efficiency E perf = t F t F t F 44 % real computation time lib: worst vs. typ crosstalk, IR drop process variation clock skew unbalanced stages [Cortadella, ICCD 04] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 30
31 Clock Distribution clock distribution network widely spread over chip minimization of delay & skew very tedious and costly A Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 31
32 ! Area Efficiency area proportion devoted to intended logic function E area = A F A + F A Ctrl = 50 % area proportion devoted to necessary flow control overhead: clock network 45% [Wilton IEEE Jnl. SSC 2/2005] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 32
33 Power Dissipation clock network con- sumes much energy concurrent switching => current peaks => voltage drops permanent switching => artificial activity D CLK D CLK according to CLK publications D 40% (DEC, e.g.).) CLK D D CLK Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 33
34 ! Power Efficiency dissipated power (total) power for intended function P tot = ( 1 δ) P + δ P + P = (1 + δ) P F F clk F static part dynamic part circuit utilization E pwr * [Duarte] α P = P tot F α PF = 1.9 P F control part (dynamic only * ) α = % 5.3% * clk δ P F P δ 90% ( α = ( α = 100%) 10%) Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 34
35 Electromagn. Interference long clock rails are good antennas virtually all radiated energy is con- centrated to one single spectral line E(f) max / CE f A Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 35
36 ! Composability each and every small change in the design requires a completely new timing analysis a switch to a new technology completely changes the timing interoperation between IP cores on a chip requires detailed specification (and matching) ) of both logic function and timing behavior Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 36
37 Asynchronous Inputs clock period T clk dec. win. T 0 setup/hold asynchronous event probability of setup/hold violation P violate T = 0 >0 T clk Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 37
38 Multiple Clock Domains CLK 1 (Ref) CLK 2 arbitrary phase relation setup/hold violation inevitable (fundamentally!) A Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 38
39 Latch: : Operation Model transparent hold Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 39
40 Response Time of a FF An input transition during the decision wwindow leads to an (unbounded) increase of clock-to-output delay t clk2out CLK D t clk2out,nom t setup 0 t hold t clk2data Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 40
41 Physical Equivalent Ball may remain on top ( metastable ) for unbounded time A small disturbance causes the ball to fall in either direction Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 41
42 Metastability Propagation u out Invertercharacteristics data D Metastab. X D X u in clk CLK CLK A The inverter maps metastable inputs to metastable outputs Therefore metastability can propagate Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 42
43 Inconsistent Perception D Metastab. X CLK D D A CLK B CLK 0 1 CMOS 3V threshold A treshold B 2.0V 0.8V 3.3V 2.4V X 0.4V 0.0V The metastable state may be regarded as 1 by one FF and as 0 by another A Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 43
44 Resolution Time t r = T clk t comb t SU clk asyn syn t clk2out t r t comb t SU normal operation: t clk2out < t r upset: asyn clk D CLK syn comb. logic D CLK t clk2out > t r Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 44
45 Mean Time Between Upset Upset metastable output is captured by subsequent FF after t r Mean Time Between Upset (MTBU) expected value (statistics!) for interval between two subsequent upsets MTBU = tr exp τ c T 0 f 1 clk f dat Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 45
46 Parameters Resolution time t r interval available for output to settle after active clock edge Flip-Flop Flop parameters τ c,t 0 experimentally determined time constant τ c dep.. on transit frequ. T 0 from effective width of decision window Clock period of FF T clk = 1/f clk Average rate of change f dat average data rate at FF data input Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 46
47 Derivation of formula upset-rate transition rate at data input 1 MTBU T r Rupset 0 = = exp τc Tclk t f dat probability of metastable state not being resolved during t r probability of transition hitting decision window Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 47
48 Synchronizer Example: Cascade of n Input-FFs asyn D D syn clk CLK CLK Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 48
49 ! Robustness metastability Issues clock = single point of failure non-redundant signal coding no gracxeful degradation timing margins help masking faults but they are shrinking! Fault Injection Results for SPEAR [Thesis Rahbaran] Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 49
50 ! Testability Test Pattern Generator register chain register chain comb logic comb logic comb logic register chain Response Analysis Scan test turns sequential problem into combinational one => hard to beat! Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 50
51 Conclusion An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an issue condition and a capture condition. This convenient solution is used by some design styles,, in particular the synchronous design. This mapping is, however, not natural. As an alternative signal coding may be used to control the triggers of source and sink. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 51
52 Conclusion Synchronous design is extremely efficient wrt. design and testing. It establishes a relation between handshake events and time that becomes increasingly cumbersome. Weak points are inherent robustness and composability Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits. Lecture "Advanced Digital Design" A. Steininger & M. Delvai / TU Vienna 52
Advanced Digital Design
Advanced Digital Design The Synchronous Design Paradigm A. Steininger Vienna University of Technology Outline The Need for a Design Style The ideal Method Requirements The Fundamental Problem Timed Communication
Advanced Digital Design
Advanced Digital Design Introduction & Motivation by A. Steininger and M. Delvai Vienna University of Technology Outline Challenges in Digital Design The Role of Time in the Design The Fundamental Design
INF3430 Clock and Synchronization
INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability
Advanced Digital Design
Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology Outline Skew versus consistency The need for a design style Hazards, Glitches & Runts Lecture "Advanced
Timing Issues in FPGA Synchronous Circuit Design
ECE 428 Programmable ASIC Design Timing Issues in FPGA Synchronous Circuit Design Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 1-1 FPGA Design Flow Schematic capture HDL
! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
Lecture #2 Solving the Interconnect Problems in VLSI
Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology
! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
The challenges of low power design Karen Yorav
The challenges of low power design Karen Yorav The challenges of low power design What this tutorial is NOT about: Electrical engineering CMOS technology but also not Hand waving nonsense about trends
CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
Exploring the Basics of AC Scan
Page 1 of 8 Exploring the Basics of AC Scan by Alfred L. Crouch, Inovys This in-depth discussion of scan-based testing explores the benefits, implementation, and possible problems of AC scan. Today s large,
In this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems.
1 In this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems. The important concepts are related to setup and hold times of registers
DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N
DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical
CMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
VLSI Design Verification and Test Delay Faults II CMPE 646
Path Counting The number of paths can be an exponential function of the # of gates. Parallel multipliers are notorious for having huge numbers of paths. It is possible to efficiently count paths in spite
Lecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
A Novel Low-Power Scan Design Technique Using Supply Gating
A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,
Lecture 10. Circuit Pitfalls
Lecture 10 Circuit Pitfalls Intel Corporation jstinson@stanford.edu 1 Overview Reading Lev Signal and Power Network Integrity Chandrakasen Chapter 7 (Logic Families) and Chapter 8 (Dynamic logic) Gronowski
A Survey of the Low Power Design Techniques at the Circuit Level
A Survey of the Low Power Design Techniques at the Circuit Level Hari Krishna B Assistant Professor, Department of Electronics and Communication Engineering, Vagdevi Engineering College, Warangal, India
! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
EITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 4.2.1: Learn More Liang Liu liang.liu@eit.lth.se 1 Outline Crossing clock domain Reset, synchronous or asynchronous? 2 Why two DFFs? 3 Crossing clock
A Bottom-Up Approach to on-chip Signal Integrity
A Bottom-Up Approach to on-chip Signal Integrity Andrea Acquaviva, and Alessandro Bogliolo Information Science and Technology Institute (STI) University of Urbino 6029 Urbino, Italy acquaviva@sti.uniurb.it
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high
VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture - 48 Testing of VLSI Circuits So, welcome back. So far in this
The Digital Abstraction
The Digital Abstraction 1. Making bits concrete 2. What makes a good bit 3. Getting bits under contract Handouts: Lecture Slides L02 - Digital Abstraction 1 Concrete encoding of information To this point
ECE 551: Digital System Design & Synthesis
ECE 551: Digital System Design & Synthesis Lecture Set 9 9.1: Constraints and Timing 9.2: Optimization (In separate file) 03/30/03 1 ECE 551 - Digital System Design & Synthesis Lecture 9.1 - Constraints
ECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 Timing Analysis Lecture 11: 1 Announcements Lab report guidelines are uploaded on CMS As part of the assignment for Lab 3 report Lab 4(A) prelab
The Need for Gate-Level CDC
The Need for Gate-Level CDC Vikas Sachdeva Real Intent Inc., Sunnyvale, CA I. INTRODUCTION Multiple asynchronous clocks are a fact of life in today s SoC. Individual blocks have to run at different speeds
Pulse propagation for the detection of small delay defects
Pulse propagation for the detection of small delay defects M. Favalli DI - Univ. of Ferrara C. Metra DEIS - Univ. of Bologna Abstract This paper addresses the problems related to resistive opens and bridging
Memory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather
Lecture 19: Design for Skew
Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004 Outline Clock Distribution Clock Skew Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant
6.004 Computation Structures Spring 2009
MIT OpenCourseWare http://ocw.mit.edu 6.004 Computation Structures Spring 009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. The Digital Abstraction
1/19/2012. Timing in Asynchronous Circuits
Timing in Asynchronous Circuits 1 What do we mean by clock? The system clock for an integrated circuit is a voltage signal that pulses at a regular frequency. 1 0 Time The clock tells each stage of a circuit
A Digital Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
A Digital Clock Multiplier for Globally Asynchronous Locally Synchronous Designs Thomas Olsson, Peter Nilsson, and Mats Torkelson. Dept of Applied Electronics, Lund University. P.O. Box 118, SE-22100,
VLSI Design I; A. Milenkovic 1
CPE/EE 427, CPE 527 VLSI Design I L02: Design Metrics Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-03f
ENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design : Conventions, Problems, Solutions Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally
Microcircuit Electrical Issues
Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the
74F50729 Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics
Metastability. 1
Metastability talarico@gonzaga.edu 1 Asynchronous Inputs Synchronous circuits can have asynchronous inputs Even a supposedly synchronous circuit like the D flip flop can have asynchronous inputs such as
Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
74F5074 Synchronizing dual D-type flip-flop/clock driver
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop/clock driver 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics Output skew guaranteed less than 1.5ns High source current
Design for Testability & Design for Debug
EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin Agenda Why test? Scan: What is it?
CHAPTER 4 GALS ARCHITECTURE
64 CHAPTER 4 GALS ARCHITECTURE The aim of this chapter is to implement an application on GALS architecture. The synchronous and asynchronous implementations are compared in FFT design. The power consumption
EECS150 - Digital Design Lecture 28 Course Wrap Up. Recap 1
EECS150 - Digital Design Lecture 28 Course Wrap Up Dec. 5, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John Wawrzynek)
Design and implementation of LDPC decoder using time domain-ams processing
2015; 1(7): 271-276 ISSN Print: 2394-7500 ISSN Online: 2394-5869 Impact Factor: 5.2 IJAR 2015; 1(7): 271-276 www.allresearchjournal.com Received: 31-04-2015 Accepted: 01-06-2015 Shirisha S M Tech VLSI
8-Bit, high-speed, µp-compatible A/D converter with track/hold function ADC0820
8-Bit, high-speed, µp-compatible A/D converter with DESCRIPTION By using a half-flash conversion technique, the 8-bit CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power.
ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
Digital design & Embedded systems
FYS4220/9220 Digital design & Embedded systems Lecture #5 J. K. Bekkeng, 2.7.2011 Phase-locked loop (PLL) Implemented using a VCO (Voltage controlled oscillator), a phase detector and a closed feedback
Multiplexer for Capacitive sensors
DATASHEET Multiplexer for Capacitive sensors Multiplexer for Capacitive Sensors page 1/7 Features Very well suited for multiple-capacitance measurement Low-cost CMOS Low output impedance Rail-to-rail digital
Test Automation - Automatic Test Generation Technology and Its Applications
Test Automation - Automatic Test Generation Technology and Its Applications 1. Introduction Kwang-Ting (Tim) Cheng and Angela Krstic Department of Electrical and Computer Engineering University of California
Memory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers 1 General Table Lookup Synthesis A B 00
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication Peggy B. McGee, Melinda Y. Agyekum, Moustafa M. Mohamed and Steven M. Nowick {pmcgee, melinda, mmohamed,
64-Macrocell MAX EPLD
43B CY7C343B Features 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance Available in 44-pin
Towards PVT-Tolerant Glitch-Free Operation in FPGAs
Towards PVT-Tolerant Glitch-Free Operation in FPGAs Safeen Huda and Jason H. Anderson ECE Department, University of Toronto, Canada 24 th ACM/SIGDA International Symposium on FPGAs February 22, 2016 Motivation
ECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code
Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code Shao-Hui Shieh and Ming-En Lee Department of Electronic Engineering, National Chin-Yi University of Technology, ssh@ncut.edu.tw, s497332@student.ncut.edu.tw
Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits
Design as You See FIT: System-Level Soft Error Analysis of Sequential Circuits Dan Holcomb Wenchao Li Sanjit A. Seshia Department of EECS University of California, Berkeley Design Automation and Test in
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing Nestoras Tzartzanis and Bill Athas nestoras@isiedu, athas@isiedu http://wwwisiedu/acmos Information Sciences Institute
The Digital Abstraction
The Digital Abstraction 1. Making bits concrete 2. What makes a good bit 3. Getting bits under contract 1 1 0 1 1 0 0 0 0 0 1 Handouts: Lecture Slides, Problem Set #1 L02 - Digital Abstraction 1 Concrete
How to design little digital, yet highly concurrent, electronics? Alex Yakovlev Newcastle University Newcastle upon Tyne, U.K.
How to design little digital, yet highly concurrent, electronics? Alex Yakovlev Newcastle University Newcastle upon Tyne, U.K. Outline Little Digital electronics: Why going asynchronous? Six Asynchronous
Lecture 11: Clocking
High Speed CMOS VLSI Design Lecture 11: Clocking (c) 1997 David Harris 1.0 Introduction We have seen that generating and distributing clocks with little skew is essential to high speed circuit design.
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency
Non-linear Control. Part III. Chapter 8
Chapter 8 237 Part III Chapter 8 Non-linear Control The control methods investigated so far have all been based on linear feedback control. Recently, non-linear control techniques related to One Cycle
UNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
EE 330 Lecture 42. Other Logic Styles Digital Building Blocks
EE 330 Lecture 42 Other Logic Styles Digital Building Blocks Logic Styles Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic Domino Zipper Static CMOS Widely used Attractive
LC2 MOS Dual 12-Bit DACPORTs AD7237A/AD7247A
a FEATURES Complete Dual 12-Bit DAC Comprising Two 12-Bit CMOS DACs On-Chip Voltage Reference Output Amplifiers Reference Buffer Amplifiers Improved AD7237/AD7247: 12 V to 15 V Operation Faster Interface
SPT BIT, 100 MWPS TTL D/A CONVERTER
FEATURES 12-Bit, 100 MWPS digital-to-analog converter TTL compatibility Low power: 640 mw 1/2 LSB DNL 40 MHz multiplying bandwidth Industrial temperature range Superior performance over AD9713 Improved
HIGH-performance microprocessors employ advanced circuit
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 5, MAY 1999 645 Timing Verification of Sequential Dynamic Circuits David Van Campenhout, Student Member, IEEE,
Managing Cross-talk Noise
Managing Cross-talk Noise Rajendran Panda Motorola Inc., Austin, TX Advanced Tools Organization Central in-house CAD tool development and support organization catering to the needs of all design teams
ECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis Overview Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation
EECS 141: FALL 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
EC O4 403 DIGITAL ELECTRONICS
EC O4 403 DIGITAL ELECTRONICS Asynchronous Sequential Circuits - II 6/3/2010 P. Suresh Nair AMIE, ME(AE), (PhD) AP & Head, ECE Department DEPT. OF ELECTONICS AND COMMUNICATION MEA ENGINEERING COLLEGE Page2
Mohit Arora. The Art of Hardware Architecture. Design Methods and Techniques. for Digital Circuits. Springer
Mohit Arora The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits Springer Contents 1 The World of Metastability 1 1.1 Introduction 1 1.2 Theory of Metastability 1 1.3 Metastability
POWER GATING. Power-gating parameters
POWER GATING Power Gating is effective for reducing leakage power [3]. Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers Muhammad Nummer and Manoj Sachdev University of Waterloo, Ontario, Canada mnummer@vlsi.uwaterloo.ca, msachdev@ece.uwaterloo.ca
Digital Systems Power, Speed and Packages II CMPE 650
Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent
A 0.9 V Low-power 16-bit DSP Based on a Top-down Design Methodology
UDC 621.3.049.771.14:621.396.949 A 0.9 V Low-power 16-bit DSP Based on a Top-down Design Methodology VAtsushi Tsuchiya VTetsuyoshi Shiota VShoichiro Kawashima (Manuscript received December 8, 1999) A 0.9
ICCAD 2014 Contest Incremental Timing-driven Placement: Timing Modeling and File Formats v1.1 April 14 th, 2014
ICCAD 2014 Contest Incremental Timing-driven Placement: Timing Modeling and File Formats v1.1 April 14 th, 2014 http://cad contest.ee.ncu.edu.tw/cad-contest-at-iccad2014/problem b/ 1 Introduction This
電子電路. Memory and Advanced Digital Circuits
電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education Email: chenhh@cc.ncue.edu.tw Spring 2010 2 Reference Microelectronic
Fan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
Lecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
Module -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 6: RX Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Prelab due now Exam
We ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits
Basic Timing Issues We ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits The fundamental timing issues we considered then apply
ECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 9: Noise Sources Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 5 Report and Prelab 6 due Apr. 3 Stateye
Mux-Based Latches. Lecture 8. Sequential Circuits 1. Mux-Based Latch. Mux-Based Latch. Negative latch (transparent when CLK= 0)
Mux-Based Latches Lecture 8 equential Circuits Negative latch (transparent when = 0) Positive latch (transparent when = ) Peter Cheung epartment of Electrical & Electronic Engineering Imperial College
Testing scheme for IC's clocks. DEIS - University of Bologna. Viale Risorgimento, 2. treated as a side eect. In fact, it is easy to
Testing scheme for IC's clocks ichele Favalli and Cecilia etra DEIS - University of Bologna Viale Risorgimento, 2 40136 Bologna, Italy Abstract This paper proposes a testing scheme to detect abnormal skews
An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS Technology
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 10 March 2016 ISSN (online): 2349-6010 An Optimal Design of Ring Oscillator and Differential LC using 45 nm CMOS
Welcome to 6.111! Introductory Digital Systems Laboratory
Welcome to 6.111! Introductory Digital Systems Laboratory Handouts: Info form (yellow) Course Calendar Safety Memo Kit Checkout Form Lecture slides Lectures: Chris Terman TAs: Karthik Balakrishnan HuangBin
THE design of reliable circuits is becoming increasingly
496 IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 3, MARCH 2013 Low Cost NBTI Degradation Detection and Masking Approaches Martin Omaña, Daniele Rossi, Member, IEEE Computer Society, NicolòBosio, and Cecilia
To Boldly Do What Can t Be Done: Asynchronous Design for All. Kenneth S. Stevens University of Utah
To Boldly Do What Can t Be Done: Asynchronous Design for All Kenneth S. Stevens University of Utah 1 Scaling Moore s Law transistor counts double every one to two years Cost has followed inverse trend
Design of Pipeline Analog to Digital Converter
Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analog-to-digital converter (ADC) architecture is the most popular topology
CROSS-COUPLING capacitance and inductance have. Performance Optimization of Critical Nets Through Active Shielding
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 51, NO. 12, DECEMBER 2004 2417 Performance Optimization of Critical Nets Through Active Shielding Himanshu Kaul, Student Member, IEEE,
Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design
Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design Cao Cao and Bengt Oelmann Department of Information Technology and Media, Mid-Sweden University S-851 70 Sundsvall, Sweden {cao.cao@mh.se}
A Novel Latch design for Low Power Applications
A Novel Latch design for Low Power Applications Abhilasha Deptt. of Electronics and Communication Engg., FET-MITS Lakshmangarh, Rajasthan (India) K. G. Sharma Suresh Gyan Vihar University, Jagatpura, Jaipur,