Probabilistic Modelling of Performance Parameters of Carbon Nanotube Transistors

Transcription

1 Probabilistic Modelling of Performance Parameters of Carbon Nanotube Transistors Amitesh Narayan, Snehal Mhatre, Yaman Sangar Department of Electrical and Computer Engineering, University of Wisconsin-Madison (narayan3, sjmhatre, Abstract CMOS technology has come to a standstill and not much scope remains for further advancements. With a motivation to find alternatives, we explore the domain of Carbon Nanotube based Field Effect Transistors (CNTFETs). A comparison of the delay and power consumption of basic gates in both technologies shows that CNTFETs have better delay and power characteristics which provides us a strong inspiration to look out further. Process variations cause faults such as presence of metallic Carbon Nanotubes (CNTs) and special techniques are required to remove them. These faults affect performance by causing excessive leakage currents, changing delay and degrading noise margin. The number of these CNTs can be modelled as binomial function. We work on a mathematical analysis of these faults and present some directions that might be helpful when working on CNT based circuits. I. INTRODUCTION Carbon Nanotubes (CNTs) are cylindrical structures of graphene of nano-scaled diameters wrapped up to form a tube. C-60 allotropes, also called fullerenes are used to make CNTs. The minimum diameter, practically possible currently, is in the range of 0.5 nm-3 nm. The strong σ bonds between carbon atoms lead to a rigid structure and a weak π bond at the surface provide loosely bonded electrons which contribute significantly to a high current density. All carbon atoms are arranged in a hexagonal aromatic rings. CNTs have unique electrical properties by which they can act as a metal, insulator or the semiconductor based on the chirality of the structure (that is, the angle in which the sheet is rolled). Carbon Nanotube Field Effect Transistors (CNTFETs) use carbon nanotubes as the channel as opposed to silicon in a MOSFET device. In a simplified structure, as shown in figure 1, the bulk of the transistor structure is made of silicon. The gate, is made by placing one or more carbon nanotubes between the source and drain contacts which acts as a connection between the two terminals. The drain and source junctions are heavily doped to have excess carriers near the conduction band which can easily conduct on application of a voltage difference. A silicon dioxide substrate acts as the insulator between the metal contacts and the CNT semiconductor part, thus completing the structure of the CNTFET. The CNTFET is a four terminal device with operating characteristics similar to a MOSFET. A voltage is applied between the source and drain terminals and the current is controlled by the voltage applied at the gate. The presence of metallic CNTs due to chirality variations, however creates a short circuit between the drain and source terminals which leads to a high current and further reliability issues. Figure 1. A Side-view of CNTFET Structure II. COMPARISON WITH CMOS TECHNOLOGY CMOS technology has been the dominant building block in the semiconductor industry so far. The consistent aggressive scaling of the dimensions and the industry competition has led to decrease in the feature size, as predicted by the Moore s Law. This continuous decrease in the transistor dimensions led to scaling of voltages as well, contributing to an effective decrease in the chip power consumption. However, the threshold voltage has now hit a wall of 0.1V because the operation of a MOS device at an extremely low threshold leads to the device not getting completely turned off, leading to large leakage currents in the OFF state. Hence, a constant voltage scaling technique has been applied to scale down the feature size without lowering the operating voltages which led to a consistent increase in the power density of the chip and a slower operating speed. Thus, to enhance the performance of microprocessors made in CMOS technology, architectural enhancements like multicore processing, simultaneous multithreading and massively parallel processing are being employed. However, the rate of increase in processor performance has been slowing down over the years and a radical shift is required. Moreover, the CMOS technology is projected to hit a power wall due to excessive leakage and Moore s Law is expected to break down [1]. Hence, a significant research in alternate building materials such as FinFETs, Ge-nanowire FET, Si-nanowire FET, wrap-around gate MOS graphene ribbon FET etc. has been going on to replace the CMOS technology. Another very promising candidate is the CNTFET technology which can be used at a

2 very low feature size (around 2 nm) and also provides considerably better performance as compared to CMOS technology in terms of speed and power consumption. To build up on the point mentioned above and provide motivation for further research in this field, we did a comparative study between some basic CMOS and CNTFET gates on HSPICE. We simulated basic gates such as inverter, nand and nor and the results for delay and power consumption have been tabulated in table 1. We used the CNTFET libraries provided by Nanoelectronics Lab at Stanford University. Circuit FET Delay (In ps) Table 1. Comparison between CMOS and CNTFET circuits in HSPICE As we can observe in table 1, the power consumption and delay of CNTFET based gates is much lower than the CMOS counterparts because of the phenomena of ballistic transport. This performance enhancement trend is a major motivation towards usage of CNTFET circuits to get better performance at lower power levels. However, the advantages observed above are assuming we have error free basic gates. A lot of process variations have much adverse effects on CNTFETs which can significantly lower the performance. We discuss these next. III. CHALLENGES WITH CNTFETS Power (In uw) Inverter CMOS CNT Input Nand CMOS CNT Input Nor CMOS CNT The CNTFET technology faces several challenges due to unavoidable process variations that occur. These variations may not only degrade performance but in extreme conditions may also lead to failure of CNTFET based logic circuits. It has been shown that CNTs are less sensitive [2] to conventional CMOS process variations such as oxide thickness, channel length, doping concentration and channel width etc. and possess CNT specific variations [3]. CNT process variations include CNT doping variations, variations in CNT chirality, diameter, density and CNT alignment. Imperfections such as mispositioned CNTs and presence of metallic CNTs also affect performance parameters. These imperfections may cause an increased gate delay, reduction in noise margin, excessive leakage current or incorrect functionality in logic circuits. Following are the major CNT-specific variations: 1) CNT density variation: Chemical synthesis process used for the growth of CNTs does not provide precise control on the location of grown CNTs. This results in few CNTs being placed comparatively closer to others, which leads to variation in CNT density. As a result number of CNTs present in fixed width of CNTFET may vary affecting the amount of current flowing. 2) Metallic-CNT induced count variation: CNTs display semiconducting or metallic properties; the presence of metallic CNTs result in conducting channel whose resistance cannot be controlled by Gate voltage. Metallic CNTs physically manifest themselves as a short between the drain and source. This results in excessive leakage current which causes undesirable effects of increasing power consumption and delay along with inferior noise performance and sometimes defective functionality too. 3) CNT diameter variation: Diameter variations occur due to chirality variations and depend significantly on the CNT growth process [4]. Typical CNT diameters range from 0.5 nm to 3 nm. The band-gap of a CNTFET is determined by the CNT diameter and hence diameter variations can cause variations in CNT threshold voltage. 4) CNT misalignment: This refers to misalignment in the direction of CNTs. Along with mispositioned CNTs it results in a change in the effective CNT length in the CNTFET s channel. It may also result in short between CNTs in the CNTFETs and can cause incorrect logic functionality or reduction in drive current [5]. 5) CNT doping variation: Variation in doping concentration in the source and drain regions; highly doped CNTs are required to exhibit unipolar behaviour. IV. CNT COUNT VARIATION Our attempt in this project is to model the CNT count distribution and derive the dependence it has on performance. As mentioned in the above section, after the lithography process, some intended semiconducting CNTs (s-cnts) end up as metallic CNTs (m-cnts). Various removal techniques are applied but their efficiency is not 100%. We are still left with some m-cnts and we need to incorporate those in our performance parameters estimation. The removal techniques are non-ideal and the distribution of metallic CNTs is thus non deterministic. It can, however, be estimated as a probabilistic function. We denote the probability of a given CNT as being an s-cnt by p s and the probability of a given CNT as being an m-cnt by p m; p m = 1 - p s. It has also been postulated in [6] that these random variables are independent and identically

3 distributed. Using this notation of probability we can construct models for the distribution of number of metallic and semiconducting CNTs in a given chip where they are grown. We denote N gs as the number of grown semiconducting CNTs and N gm as the number of grown metallic CNTs. It was shown by [7] that both of them follow a binomial distribution. Assume N is the total number of grown CNTs. So the probability of having n gs s-cnts and n gm m-cnts given n CNTs are grown is denoted by: Eq 4.1 Eq 4.2 [8] Mentions various removal techniques to remove m- CNTs since they are a major performance bottleneck. However, these techniques do not ensure removal of all m- CNTs; some of them still survive. Further, in an attempt to remove m-cnts, some s-cnts are removed as well. We denote p rs (p rm) as the conditional probability of removing a CNT given that it was a semiconducting (metallic) CNT. The probability that n s s-cnts (or n m m-cnts) survive after applying removal techniques from the grown n gs s-cnts (or n gm m-cnts) is given by: V. IMPACT OF METALLIC CNTS ON ON-OFF CURRENT RATIO The probabilistic models proposed above can be used to determine impact of m-cnts on the CNTFET I ON / I OFF tuning ratio. Improper I ON / I OFF can cause slow output transitions or low output swings. It is also a good indicator of the amount of transistor leakage. Practically the target value of I ON /I OFF ratio should be greater than 10 4 [8]. Let I s and I m denote the drive current of single s-cnt and m-cnt respectively as a function of its diameter and µ(i s) and µ(i m) be the corresponding mean of the currents. If the type of the CNT is unknown, let I CNT be the current of a single CNT and let µ(i CNT) be its mean. As shown below, µ(i CNT) can then be denoted in terms of µ(i s), µ(i m), p m, and p s. Taking the mean of the CNT current (from equation 5.1), Eq 5.1 Eq 5.2 From basic statistical analysis, we can relate standard deviation and mean as: Eq 4.3 Eq 4.4 Where q rs = 1 - p rs and q rm = 1 - p rm. N s and N m are the number of surviving s-cnts and m-cnts after removal. We now combine both the distributions mentioned above to construct a combined model which is the joint probability distribution of surviving m-cnt and s-cnt count if the grown CNT counts are given. = = 2 The I ON / I OFF ratio of CNTFET is given by, Eq 5.3 Eq 5.4 Where N s and N m denote the count of s-cnt and m- CNT respectively. For an n-type CNTFET, I s,on is the s-cnt current when V gs = V ds = V dd and I s,off is the s-cnt current when V gs = 0 and V ds = V dd. As mentioned before, the current in an m-cnt remains almost same throughout, irrespective of whether the CNT is ON or not. This difference can be ignored and we denote the m-cnt current I m. If we take mean of equation 5.4 we have, Eq 5.5 From the probabilistic model defined above, Eq 5.6 Eq 5.7 Eq 4.5

4 Therefore, Eq 5.8 Having an m-cnt degrades performance but reduces delay also since it provides a low resistance path between the rails and output node. In other words, having a large number of m- CNTs might actually end up decreasing the delay of the circuit. However, to keep the functionality and the power aspect in mind, we consider a high value of c m so that m-cnts do not contribute heavily. Taylor series expansion can be done on the delay equation mentioned above in the neighbourhood of the mean of the drive current, i.e. I drive = µ(i drive). This gives us the following expansion: Figure 2: Plot of µ(i ON) / µ(i OFF) v/s 1 - P rm The figure shows effect of various processing parameters on the ratio µ(i ON) / µ(i OFF). It is observed that the tuning ratio is more sensitive to p rm. To obtain target value of I ON / I OFF = 10 4 required value of p rm > % for p m = 33.33%. This implies that for proper I ON / I OFF more at least 99.99% of the metallic CNTs should be removed given that one third of all the grown CNTs were metallic. VI. DELAY VARIATIONS The mean of delay is given by: Eq 6.2 Many of the m-cnt removal techniques perform a diameter dependant removal on the entire chip initially having a probabilistic occurrence of m-cnts or s-cnts. However, as mentioned before, these removal techniques are not perfect and there is always a random number of m-cnts left behind. Moreover, these removal techniques also end up etching away some s-cnts. In this section we attempt to study the implications of such removal processes on the delay variations of a CNTFET circuit. For this we define two cut-off diameters, c s and c m. The definitions are mentioned below: All s-cnts with diameters below c s are removed. This means c s defines the error in judgement of the removal technique. Ideally, this value should be zero. All m-cnts with diameters below c m are removed. This term correlates with the efficiency of the removal technique. Ideally, this should be infinite. According to [8], a good estimate of c s is 1.4 nm and that of c m is 2 nm. To look into the repercussions of the removal process, we use a delay model defined as in [9] Eq 6.1 Consider the first order term, the mean value of is 0. The zeroth order term is a constant (hence the mean should be the same as the constant itself), the mean of the first order term is 0 and the higher order terms are small enough to be ignored. Thus, an approximation to the mean of delay is just the constant term: Eq 6.3 The standard deviation of delay is given by the first order term. is the standard deviation of I drive. Eq 6.4 When c m is sufficiently large, the contribution of m-cnts in the total current can be ignored which means that the drive current is almost the same as I s,on. So we have,

5 Eq 6.5 Now the standard deviation of delay can be rearranged as: Eq 6.6 If we consider = ( and = ( ), then from equations 5.2 and 5.3, and considering and, since c m is sufficiently large to bring the contribution of m-cnts to zero, we have: = = Eq 6.7 We plot v/s in figure 3. The figure implies that the delay variation denoted by the ratio of standard deviation and mean of the delay is initially constant but subsequently increases. We can set a maximum to a value of 0.3 for the delay of a CNTFET unit to be tolerant of current variations due to metallic CNTs. We also observe that the variations are more sensitive to when the number of CNTs is less. This is the case because when we increase the number of CNTs per CNTFET, more of them can act as parallel channels, thereby diminishing the sensitivity of on. Figure 4: variation of v/s N As observed in the set of curves above, the decreases with increasing N. Moreover, a higher value of leads to a higher since the sensitivity of delay variations increases with increase in the on-current variations. VII. NOISE MARGIN Noise margin of a circuit is the amount of voltage fluctuation that it can withstand without compromising the logic of the intended function. The simplest noise margin calculation is done for an inverter circuit. In that case, we define two voltage levels which define the minimum level of logic 1 and the maximum level of logic 0. Figure 3: Variation of v/s Figure 4 shows the plot of variation of N for different values of. v/s Figure 5: Noise Margin Assessment Given above are the output voltage v/s input voltage characteristics for CNTFET inverter. We define the maximum input voltage level that gives logic 1 at the output as V IL and

6 the minimum input voltage that gives logic 0 at the output as V IH. These two voltages are defined as the input levels when the slope of the curve becomes -1. We have derived the noise margin of a CNTFET inverter in terms of the process parameters and presented the results. A full derivation of the same can be found in the attached appendix and the reader is encouraged to go through it to get the mathematical picture of the equations presented here. Before that, we specify the process parameters of a CNTFET used in the derivation process [10]. Consider as the carrier mobility in a CNTFET and as the conversion factor for nanotube to graphite which varies between 0 and 1. C ox is the oxide capacitance between the gate and nanotube. We denote = C ox/l 2. Definition of more parameters is mentioned below [10]: I = [ ] dx Eq 7.1 m = Eq 7.2 C ox = Eq 7.3 where T ox is the the gate oxide thickness, is the dielectric constant of the gate oxide, L is the length,r is the radius of the nanotube, T is temperature and k is the Boltzmann s constant. Using these parameters, the noise margin equations were set up and the results derived. The derived results are mentioned below: Eq 7.4 For a CMOS transistor, the V IL value is approximately given by V IL = V TN (V DD V TP V TN). We assume for the simplicity of analysis V TP = V TN = V TH which gives us V IL = V TH (V DD 2V TH). For a CNTFET, if we assume β p = β n, then the approximate equation for V IL assuming same V TH values comes out as: For CMOS: Eq 7.5 Eq 7.6 has a negligible effect in Eq 7.5. Comparing it to Eq 7.6, we can state that the value of V IL for a CNTFET is greater than that of CMOS. Now for a CMOS transistor, Eq 7.7 For a CNTFET, assuming equal threshold voltages and β p = β n, we get a V IH value approximately mentioned below: For CMOS: Eq 7.8 Eq 7.9 Again from Eq 7.8 and 7.9, it is clearly visible that V IH for CMOS is greater than V IH for CNTFET. Now, noise margin NM L = V IL - 0 and NM H = V DD V IH. V IL for CNTFET is greater than that of CMOS which implies NM L of a CNTFET is greater than that of CMOS. V IH for CNTFET is less than that of CMOS, which means that NM H which is V DD V IH is greater for the CNTFET. We conclude that CNTFET provides better noise margin than the CMOS. VIII. CONCLUSION We have been able to identify how the presence of metallic CNTs affect the ratio of on and off current and hence tend to increase leakage currents. We have also shown how delay depends on the count variation. Guidelines on the requirements obtained from our analysis suggests that at least 99.99% of the m-cnts need to be removed for proper functionality. Further, to keep delay variations to a tolerable range, the deviation should be less than 30% of the mean current. Our analysis on noise margin presents equations to calculate the noise margin for given CNTFET configurations. Based on mathematical analysis, we find that CNTFETs provide better noise margin as compared to a CMOS. We kept ourselves limited to variations in diameter and CNT count because these two are the most dominant causes of errors but as we discussed before, many other issues exist. A more elaborate model would consider other issues such as misalignment and density variations. Furthermore, the noise margin analysis can be extended to incorporate the effect of changes in current due to count and diameter variations; doing that would quantify noise margin degradation and might add to the guidelines that must be followed for proper functionality. In our opinion, the fact that a CNTFET intrinsically has better delay and power capabilities makes it a good replacement option. There are faults which make the use of

7 CNTFET at this stage rather difficult but alternative technologies are required to be researched if the same growth in the field of hardware design is to be maintained. Much research needs to done in this field, but the results might be a lot more fruitful than the work required to achieve them. Integration (VLSI) Systems, IEEE Transactions on, vol.21, no.5, pp.887,900, May 2013 REFERENCES [1] Iwai H., Roadmap for 22nm and beyond, Journal of Microelectronic Engineering, Elsevier, 2009 [2] Paul, B., et al., Impact of a Process Variation on Nanowire and Nanotube Device Performance, IEEE Trans. Elec. Dev.Vol. 54, No. 9, pp , 2007 [3] Kuhn, K. J., Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS, Proc. Intl. Electronic Devices Meeting, pp , 2007 [4] Saito, R., G. Dresselhaus and M. Dresselhaus, Physical Properties of Carbon Nanotubes, Imperial College Press, 1998 [5] Patil, N., et al., Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits, IEEE Trans.Computer-Aided Design, pp , 2008 [6] Lin, A., et al., ACCNT-A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration, IEEE Trans. Electron Devices, vol. 56, no. 12, pp , 2009 [7] Rice, J. A., Mathematical Statistics and Data Analysis, 2nd edition, Duxbury Press, 1994 [8] Zhang, G., et al., Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction, Science, Vol. 314, No. 5801, pp , 2006 [9] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998 [10] Marulanda J.,et al., Transfer Characteristics and High Frequency Modeling of Logic Gates Using Carbon Nanotube Field Effect Transistors(CNT-FETs), Association for Computing Machinery SBCCI, pp , 2007 [11] Yasuda, S., et al.,"fault-tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry," Nanotechnology, NANO '08. 8th IEEE Conference on, vol., no., pp.684,687, Aug [12] Patil, N., et al., "VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs," Electron Devices Meeting (IEDM), 2009 IEEE International, vol., no., pp.1,4, 7-9 Dec [13] Geunho Cho, et al., "Assessment of CNTFET based circuit performance and robustness to PVT variations," Circuits and Systems, MWSCAS '09. 52nd IEEE International Midwest Symposium on, vol., no., pp.1106,1109, 2-5 Aug [14] Hashempour., et al., "Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs," Design, Automation & Test in Europe Conference & Exhibition, DATE '07, vol., no., pp.1,6, April 2007 [15] Ghavami, B., et al., "Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits," Very Large Scale

8 APPENDIX The derivation of noise margin equations are performed in this section. Assume an inverter made up of CNTFETs. A circuit diagram is shown below: We can derive the noise margin in two stages. Case1) Derivation of V IL Figure 6: CNTFET Based Inverter (V IL - 0) is the range of input voltages between which the output voltage is interpreted as logic 1. When in V IL voltage level, the transistor M5 is in linear region and M1 in saturation. The currents are equal through both the transistors since there is no loading on the output node. Equating the currents on both transistors, we get: Now, it is evident from figure 6 that,, and Substituting these, we have,. Differentiating with respect to Vin and substituting, we have:

9 Assuming and simplifying the equation, we have: Now consider the Point A in the figure, here and. We can thus derive an expression for as follows: Case 2) Derivation of V IH (V DD- V IH) is the input voltage range in which an output voltage is interpreted as logic 0. Hence, V IH is the minimum voltage that defines the noise margin for logic 1. At this input voltage, the transistor M1 is in linear region and transistor M5 is in saturation. The current however, is the same. Hence to derive the noise margin range, we equate the two currents. Now, it is evident from figure 6 that,, and Substituting these we have,. Differentiating with respect to Vin and substituting, we have: Assuming and simplifying the equation, we have:

10 Now consider the Point A in the figure, here and. We can thus derive an expression for as follows: