PART I - DOUBLE- PULSE GAN FET NONLINEAR CHARACTERIZATION AND MODELING

Transcription

1 Nonlinear Characteriza/on and Modelling of Microwave Electron Devices for Large Signal and Low Noise Applica/ons PART I - DOUBLE- PULSE GAN FET NONLINEAR CHARACTERIZATION AND MODELING Prof. Alberto Santarelli University of Bologna Keysight Technologies, Semiconductor Devices CharacterizaBon Seminar University of Bologna, Italy - 24 th March, 2014

2 Acknowledgement Research Group on Electronic Design and Measurement for RF and Industrial Applications EDM Lab DEI Guglielmo Marconi University of Bologna Staff F. FILICORI A. SANTARELLI P.A. TRAVERSO C. FLORIAN R. CIGNANI R. P. PAGANELLI* (*CNR IEIIT) Ph.D. Students and Post Doc D. NIESSEN G. P. GIBIINO T. CAPPELLO 2

3 EDM Lab Main research topics and services Design of RF and microwave MMIC and HMIC circuits Active and passive microwave electron device modelling On-wafer and coaxial characterization of RF and microwave circuits and electron devices Design and implementation of measurement benches for electron device characterization Design of efficient dynamic power supplies and other power electronic circuits Design of efficient dynamic power supplies in GaN technology for Envelope Tracking Behavioral modelling of front-end communication circuits for system level simulations Behavioral modelling of digital data acquisition systems (ADCs or entire A/D channels) Digital pre-distortion algorithms for HPA linearization 3

4 Outline Linear and nonlinear charge trapping (GaAs vs GaN) 50-Ω Single Pulse Measurement Setup Nonlinear Lag Function Double-Pulse Technique Empirical Nonlinear FET Modeling based on DP Techniques 4

5 Low Frequency Dispersive Effects and Pulsed I/V Measurements LF Dispersive phenomena (thermal + traps) affect DC and Pulsed I/Vs of III- V FETs I/V sets strongly dependent on present and past values of applied voltages (long memory effects) Thermal Performance degradaeon w.r.t. ideal case Slow Effects GaAs-FET Charge trapping ms µs Drain Current [ma] Pulsed Sta/c Pulse Width High- frequency charge storing phenomena ns Drain Voltage [V] Fast Effects Low- duty cycle pulsed periodic excita/on (e.g. 100ns, 1%) 5

6 Linear Charge Trapping Phenomena (e.g. GaAs-FETs) Linear relationship between charge trap state and applied voltages Charge trap state in above-cutoff operation only depending on mean value of the applied voltages Pulsed I/V from V GQ = 0 V, V DQ = 0 V (Curve I) Pulsed I/V from V GQ = V T,V DQ = 0 V (Curve II) Pulsed I/V from V GQ = V T, V DQ = V D,nom (Curve III) Corresponding to minimum amount of trapped charges (typ. assumed as NO TRAP CASE) Corresponding to a certain amount of traps due to ΔV GQ (GATE-LAG-ONLY CASE) Corresponding to extra trapped charges due to ΔV DQ (GATE- AND DRAIN LAG CASE) All curves are Iso-thermal (at base-plate temperature) 6

7 What about GaN FETs? Experience suggests that GaN FET performance not only depends on the mean values but also on the complete gate and drain voltage waveforms (peaks) Nonlinear charge trapping phenomena A recently proposed pulsed measurement setup helps in evaluating the nonlinear performance degradation due to nonlinear dispersive phenomena 7

8 50- Ω- Load Pulsed I/V Setup (1) Multiple Pulse Time Domain Network Analyzer COUPLER DUT (on wafer) R 0 1 x t x () a () t 1 t a () t 2 x () 2 t x () 2 t () b1 a AC DC BIAS-TEE DC+AC b 1( t ) BIAS SYSTEM DC DC+AC b () t 2 BIAS-TEE AC TIME DOMAIN SAMPLING SYSTEM (4-CHANNELS) a COUPLER b R 0 DC and AC paths separa/on through bias- tees V 0 independent of the wave duty cycle Meas. setup similar to typ. RF instrumentaeon (e.g. VNA, LSNA) REF: A. Santarelli et al., New pulsed measurement setup for GaN and GaAs FETs characterizaeon, Cambridge Int. J. of Micr. and Wireless Tech., Vol. 4, N. 3, pp , Apr

9 50- Ω- Load Pulsed I/V Setup (2) Multiple Pulse Time Domain Network Analyzer Pulses in a 50- Ω system: Incident and reflected waves instead of voltages and currents Improved stability due to resiseve terminaeon Improved accuracy due to reduced ringing/overshoots Shorter pulses (down to 50 ns of width) Even long, but matched, cables do not limit the meas. system bandwidth Std (VNA- like) calibraeon techniques a) Actual pulses at the FET input Voltage (mv) 0 b) Time (µs) Upper: ideal voltage pulse generator (0- Ω internal imp.) Lower: wave pulses generator (50- Ω internal imp.) 9

10 50- Ω- Load Pulsed I/V Setup (2) Multiple Pulse Time Domain Network Analyzer a) Actual pulses at the FET input Voltage (mv) 0 b) Time (µs) Upper: ideal voltage pulse generator (0- Ω internal imp.) Lower: wave pulses generator (50- Ω internal imp.) 10

11 Pulsed I/V: GaN vs GaAs FETs UMS AlGaN/GaN FET (L=0.25 µm, W=600 µm) Pulsed Drain Current vs Drain Voltage (drain- only pulsed excit. used for meas. shown in this slide) DC component of the Pulsed Drain Current vs Drain Voltage AlGaAs/GaAs PHEMT (L=0.25 µm, W=300 µm) Pulsed Drain Current (blue) DC component (red) Vs Drain Voltage Slope change in Pulsed Drain Current v G : V, V, V AC/DC CONVERSION DUE TO NONLINEAR TRAP- STATE- VS- VOLTAGE RELATIONSHIP DC Drain Current Drop GOOD SENSOR OF TRAP STATE VARIATION IN GaN FETs!!! Flat DC component of the pulsed Drain Current observed in GaAs FETs v G : V, V EXPECTED DUE TO LINEAR TRAPS 11

12 Nonlinear Lag Function (both gate and drain pulsed excitaeon) λ NLF [V GQ, V DQ, v G, v D ] = I DQ [V GQ, V DQ ] - I DC [v G, v D ] Pulsed Drain Current from V GQ = -3.1 V (I DQ = 100 ma), V DQ = 25 V, v G, v D V GQ, V DQ UMS GaN FET 8x125 um (0.25 um) DeviaEon of the DC component of Pulsed Drain Current I DC [v G, v D ] from the quiescent value I DQ [V GQ, V DQ ] gives indicaeon about TRAP STATE VARIATIONS STD PULSED I/V CURVES OF GaN FETs ARE ISO- THERMAL BUT NOT ISO- DYNAMIC!!! 12

13 HOW TO OBTAIN ISO- DYNAMIC I/V? Double- Pulse Technique Device ExcitaEon: periodic repeeeon (low- duty- cycle) of an elementary pajern made up of two sequeneal narrow pulses simultaneously applied at both the gate and drain ports Pre- Pulse toward (V T, V D,max ) acev. of fast charge trapping selng of max amount of traps (χ MAX ) Measure- Pulse toward generic (v G, v D ) with v G > V T and v D < V D,max current acquisieon during slow trap release (χ χ MAX ) Over the full I/V plane: No variaeon of the trap- state χ MAX corresponding to typical LS PA opera/on No variaeon of the internal FET temperature θ[v GQ, V DQ ] REF: A. Santarelli et al., A Double- Pulse Technique for the Dynamic I/V CharacterizaEon of GaN FETs, IEEE Microw. Wirel. Compon. LeP., Vol. 24, N. 2, pp , Feb

14 Double- Pulse Technique GaN- on- SiC FET (10x100µm, L=0.5µm) Measured Point Quiescient Point Pre- pulse Target Gate Meas- Pulse Gate Pre- Pulse v G (t) Drain Pre- Pulse v D (t) Drain Meas- Pulse Typ. Meas. CondiEons: Pulse width = 75 ns Total pulse pajern = 250 ns Total wave period = 10 us Duty cycle: 2.5% 14

15 Double- vs Single-Pulse I/V UMS GaN FET 8x125 μm (L = 0.25 μm) Std Single Pulse I/V Bias point V GQ = -2.5 V (I DQ = 200 ma), V DQ = 20 V Double- Pulse I/V Pre-pulses toward: v G = -4.5 V v D = 50 V 15

16 State Space Modeling i CH! " v G,v D, X,ϑ # $ F! CH " v G,v D,ϑ # $ + f! X " v G,v D dx dt h # $ X (t) X QS[v G (t),v D (t)]% & # $ X X M ( ) X QS [v G (t),v D (t)] w[v G (t)]+γ[v G (t)] v D (t) Quasi-static state variable Xqs directly identified from Non Linear Lag Function measurements Direct identification of model functions from double-pulse I/Vs at different baseplate temperatures Easily implementable through Keysight ADS SDDs and LUTs 16

17 GaN FET Modeling based on NLF f 0 = 5 GHz UMS 1-mm GaN FET (L=0.25 µm) V GQ = -3.1 V, V DQ = 30 V à I DQ = 80 ma/mm à Measurements à Model with std. PIV Z load (f 0, 2f 0, 3f 0 ) à Model with Double-Pulse A. Santarelli, D. Niessen, R. Cignani, G. P. Gibiino, P. A. Traverso, C. Florian, D. Schreurs, F. Filicori, GaN FET Nonlinear Modeling Based on Double Pulse I/V Characteristics, IEEE Trans on MTT, vol.62, no.12, pp.3262,3273, Dec

18 Intermodulation Test UMS 1-mm GaN FET (L=0.25 µm) V GQ = -3.1 V, V DQ = 30 V à I DQ = 80 ma/mm Fundamental Tone à Measurements à Model with Double-Pulse 3 rd order IMD Z S = Z L = 50 Ω f 0 = 1.5 GHz Δf 0 = 1 MHz 18

19 Future Work on Nonlinear Characterization and Modeling of GaN FETs Extrinsic parasitic network based on coldand hot-fet small-signal S-Parameters Gate-Source and Gate-Drain Diodes based on Single- Pulse Characterization (50-Ω set-up) LF Drain current modeling based on Single- and Double- Pulse I/V (50-Ω set-up) Semi-automated tool for GaN FET characterization and direct model extraction Gate and Drain displacement current modelling from double-pulsed dynamic biased RF measurements FUTURE WORK (Fast VNA or NVNA) 19