Precision, LowCost, High Speed, BiFET Op Amp AD711

Transcription

1 a FEATURES Enhanced Replacement for LF4 and TL8 AC PERFORMANCE Settles to.% in. s 6 V/ s min Slew Rate (J) 3 MHz min Unity Gain Bandwidth (J) DC PERFORMANCE.2 mv max Offset Voltage: (C) 3 V/ C max Drift: (C) 2 V/mV min Open-Loop Gain (K) 4 V p-p max Noise,. Hz to Hz (C) Available in Plastic Mini-DIP, Plastic SO, Hermetic Cerdip, and Hermetic Metal Can Packages MIL-STD-883B Parts Available Available in Tape and Reel in Accordance with EIA-48A Standard Surface Mount (SOIC) Dual Version: AD72 PRODUCT DESCRIPTION The is a high speed, precision monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps. The superior ac and dc performance of this op amp makes it suitable for active filter applications. With a slew rate of 6 V/µs and a settling time of µs to ±.%, the is ideal as a buffer for 2-bit D/A and A/D Converters and as a high-speed integrator. The settling time is unmatched by any similar IC amplifier. The combination of excellent noise performance and low input current also make the useful for photo diode preamps. Common-mode rejection of 88 db and open loop gain of 4 V/mV ensure 2-bit performance even in high-speed unity gain buffer circuits. The is pinned out in a standard op amp configuration and is available in seven performance grades. The J and K are rated over the commercial temperature range of C to 7 C. The A, B and C are rated over the industrial temperature range of 4 C to +8 C. The S and T are rated over the military temperature range of 4 C to +2 C and are available processed to MIL- STD-883B, Rev. C. Precision, LowCost, High Speed, BiFET Op Amp CONNECTION DIAGRAMS OFFSET NULL INVERTING NON INVERTING NC V S k V OS TRIM OFFSET NULL 8 NC INVERTING NONINVERTING V S OUTPUT V S 4 OFFSET NULL NC = NO CONNECT V Extended reliability PLUS screening is available, specified over the commercial and industrial temperature ranges. PLUS screening includes 68 hour burn-in, as well as other environmental and physical tests. The is available in an 8-pin plastic mini-dip, small outline, cerdip, TO-99 metal can, or in chip form. +V S OUTPUT OFFSET NULL NC = NO CONNECT NOTE PIN 4 CONNECTED TO CASE PRODUCT HIGHLIGHTS. The offers excellent overall performance at very competitive prices. 2. Analog Devices advanced processing technology and % testing guarantee a low input offset voltage (.2 mv max, C grade, 2 mv max, J grade). Input offset voltage is specified in the warmed-up condition. Analog Devices laser wafer drift trimming process reduces input offset voltage drifts to 3 µv/ C max on the C. 3. Along with precision dc performance, the offers excellent dynamic response. It settles to ±.% in µs and has a % tested minimum slew rate of 6 V/µs. Thus this device is ideal for applications such as DAC and ADC buffers which require a combination of superior ac and dc performance. 4. The has a guaranteed and tested maximum voltage noise of 4 µv p-p,. to Hz (C).. Analog Devices well-matched, ion-implanted JFETs ensure a guaranteed input bias current (at either input) of 2 pa max (C) and an input offset current of pa max (C). Both input bias current and input offset current are guaranteed in the warmed-up condition. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: 78/ Fax: 78/ Analog Devices, Inc., 22

2 SPECIFICATIONS (V S = T A = 2 C, unless otherwise noted.) J/A/S K/B/T C Parameter Min Typ Max Min Typ Max Min Typ Max Unit OFFSET VOLTAGE Initial Offset.3 2// mv T MIN to T MAX 3/2/2..4 mv vs. Temp 7 2/2/2 2 µv/ C vs. Supply db T MIN to T MAX 76/76/ db Long-Term Stability µv/month BIAS CURRENT 2 V CM = V 2 pa V CM = T MAX./3.2/./3.2/.6 na V CM = ± V pa OFFSET CURRENT V CM = V 2 2 pa V CM = T MAX.6/.6/26.6/.6/26.6 na FREQUENCY RESPONSE Small Signal Bandwidth MHz Full Power Response khz Slew Rate V/µs Settling Time to.% µs Total Harmonic Distortion % IMPEDANCE Differential Ω pf Common Mode Ω pf VOLTAGE RANGE Differential 3 ± 2 ± 2 ± 2 V Common-Mode Voltage 4 +4.,. +4.,. +4.,. T MIN to T MAX V S + 4 +V S 2 V S + 4 +V S 2 V S + 4 +V 2 V Common-Mode Rejection Ratio V CM = ± V db T MIN to T MAX 76/76/ db V CM = ± V db T MIN to T MAX 7/7/ db VOLTAGE NOISE µv p-p nv/ Hz nv/ Hz nv/ Hz nv/ Hz CURRENT NOISE... pa/ Hz OPEN-LOOP GAIN V/mV // V/mV OUTPUT CHARACTERISTICS Voltage +3, , , , , , 3.3 V ± 2/± 2/± , 3. ± , 3. ± , 3. V Current ma POWER SUPPLY Rated Performance ± ± ± V Operating Range ± 4. ± 8 ± 4. ± 8 ± 4. ± 8 V Quiescent Current ma NOTES Input Offset Voltage specifications are guaranteed after minutes of operation at T A = 2 C. 2 Bias Current specifications are guaranteed maximum at either input after minutes of operation at T A = 2 C. For higher temperatures, the current doubles every C. 3 Defined as voltage between inputs, such that neither exceeds ± V from ground. 4 Typically exceeding 4. V negative common-mode voltage on either input results in an output phase reversal. Specifications subject to change without notice. 2

3 ABSOLUTE MAXIMUM RATINGS Supply Voltage ±8 V Internal Power Dissipation mw Input Voltage ±8 V Output Short Circuit Duration Indefinite Differential Input Voltage V S and V S Storage Temperature Range (Q, H) C to + C Storage Temperature Range (N) C to +2 C Operating Temperature Range J/K C to +7 C A/B/C C to +8 C S/T C to +2 C Lead Temperature Range (Soldering 6 sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin Plastic Package: θ JC = 33 C/Watt; θ JA = C/Watt 8-Pin Cerdip Package: θ JC = 22 C/Watt; θ JA = C/Watt 8-Pin Metal Can Package: θ JC = 6 C/Watt; θ JA = C/Watt 3 For supply voltages less than ±8 V, the absolute maximum input voltage is equal to the supply voltage. ORDERING GUIDE Temperature Package Package Model Range Description Option* *AH 4 C to +8 C 8-Pin Metal Can H-8A AQ 4 C to +8 C 8-Pin Ceramic DIP Q-8 *BQ 4 C to +8 C 8-Pin Ceramic DIP Q-8 *CH 4 C to +8 C 8-Pin Metal Can H-8A JN C to 7 C 8-Pin Plastic DIP N-8 JR C to 7 C 8-Pin Plastic SOIC R-8 JR-REEL C to 7 C 8-Pin Plastic SOIC R-8 JR-REEL7 C to 7 C 8-Pin Plastic SOIC R-8 KN C to 7 C 8-Pin Plastic DIP N-8 KR C to 7 C 8-Pin Plastic SOIC R-8 KR-REEL C to 7 C 8-Pin Plastic SOIC R-8 KR-REEL7 C to 7 C 8-Pin Plastic SOIC R-8 *SQ/883B C to +2 C 8-Pin Ceramic DIP Q-8 *TQ/883B C to +2 C 8-Pin Ceramic DIP Q-8 *Not for new design, obsolete April 22 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 3

4 Typical Performance Characteristics VOLTAGE SWING Volts R L = 2k 2 C OUTPUT VOLTAGE SWING Volts + R L = 2k 2 C OUTPUT VOLTAGE SWING Volts p-p 2 2 V SUPPLIES 2 SUPPLY VOLTAGE Volts 2 SUPPLY VOLTAGE Volts k k LOAD RESISTANCE TPC. Input Voltage Swing vs. Supply Voltage TPC 2. Output Voltage Swing vs. Supply Voltage TPC 3. Output Voltage Swing vs. Load Resistance QUIESCENT CURRENT ma SUPPLY VOLTAGE Volts BIAS CURRENT (V CM = ) Amps TEMPERATURE C OUTPUT IMPEDANCE.. k A VCL = k k M M FREQUENCY Hz TPC 4. Quiescent Current vs. Supply Voltage TPC. Input Bias Current vs. Temperature TPC 6. Output Impedance vs. Frequency 26. BIAS CURRENT pa 7 2 V S = V 2 C MAX J GRADE LIMIT SHORT CIRCUIT CURRENT LIMIT ma OUTPUT CURRENT +OUTPUT CURRENT UNITY GAIN BANDWIDTHT MHz COMMON MODE VOLTAGE Volts AMBIENT TEMPERATURE C TEMPERATURE C TPC 7. Input Bias Current vs. Common Mode Voltage TPC 8. Short Circuit Current Limit vs. Temperature TPC 9. Unity Gain Bandwidth vs. Temperature 4

5 OPEN LOOP GAIN db R L = 2k C = pf GAIN PHASE PHASE MARGIN Degrees OPEN-LOOP GAIN db 2 2 R L = 2k 2 C POWER SUPPLY REJECTION db SUPPLY V S = SUPPLIES WITH V p-p SINE WAVE 2 C +SUPPLY 2 k k k M FREQUENCY Hz 2 M 9 2 SUPPLY VOLTAGE Volts k k k SUPPLY MODULATION FREQUENCY Hz TPC. Open-Loop Gain and Phase Margin vs. Frequency TPC. Open-Loop Gain vs. Supply Voltage TPC 2. Power Supply Rejection vs. Frequency CMR db V S = V V CM = V p-p 2 C OUTPUT VOLTAGE Volts p-p R L = 2k 2 C V S = V OUTPUT SWING FRIM V TO Volts %.%.% ERROR %.%.% k k k M FREQUENCY Hz k M FREQUENCY Hz M SETTLING TIME s TPC 3. Common Mode Rejection vs. Frequency TPC 4. Large Signal Frequency Response TPC. Output Swing and Error vs. Settling Time 7 k 2 THD db V RMS R L = 2k C L = pf NOISE VOLTAGE nv/ Hz SLEW RATE V s 2 3 k k k FREQUENCY Hz TPC 6. Total Harmonic Distortion vs. Frequency k k k FREQUENCY Hz TPC 7. Input Noise Voltage Spectral Density ERROR SIGNAL mv (AT SUMMING JUNCTION) TPC 8. Slew Rate vs. Input Error Signal

6 SLEW RATE V/ s V S 2k pf OUTPUT +V S +V S.3Mk k k TEMPERATURE C V S V S V S TPC 9. Slew Rate vs. Temperature TPC 2. T.H.D. Test Circuit TPC 2. Offset Null Configurations +V S V IN R L 2k C L pf SQUARE WAVE V S TPC 22a. Unity Gain Follower TPC 22b. Unity Gain Follower Pulse Response (Large Signal) TPC 22c. Unity Gain Follower Pulse Response (Small Signal) k +V S V IN k R L 2k C L pf SQUARE WAVE V S TPC 23a. Unity Gain Inverter TPC 23b. Unity Gain Inverter Pulse Response (Large Signal) TPC 23c. Unity Gain Inverter Pulse Response (Small Signal) 6

7 OPTIMIZING SETTLING TIME Most bipolar high-speed D/A converters have current outputs; therefore, for most applications, an external op amp is required for current-to-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is: t S Total = (t S DAC ) 2 + (t S AMP ) 2 () The settling time of an op amp DAC buffer will vary with the noise gain of the circuit, the DAC output capacitance, and with the amount of external compensation capacitance across the DAC output scaling resistor. Settling time for a bipolar DAC is typically ns to ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high-speed voltage-output D-to-A function. The introduction of the /72 family of op amps with their µs (to ±.% of final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized. In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the family assures 2-bit accuracy over the full operating temperature range. The excellent high-speed performance of the is shown in the oscilloscope photos of Figure 2. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the both photos show the worst case situation: a full-scale input transition. The DAC s 4 kω [ kω 8 kω = 4.4 kω] output impedance together with a kω feedback resistor produce an op amp noise gain of 3.2. The current output from the DAC produces a V step at the op amp output ( to V Figure 2a, V to V Figure 2b.) Therefore, with an ideal op amp, settling to ±/2 LSB (±.%) requires that 37 µv or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the summing junction) must be less than 37 µv. As shown in Figure 2, the total settling time for the /AD6 combination is.2 microseconds. BIPOLAR OFFSET ADJUST GAIN ADJUST R2 REF IN REF GND REF OUT V 9.9k 2k V CC.mA I REF R AD6A BIPOLAR OFF 9.9k DAC I OUT = 4 I REF CODE I O k k k 2V SPAN V SPAN DAC OUT pf +V K OUTPUT V TO +V V EE POWER GND MSB LSB V Figure. ± V Voltage Output Bipolar DAC a. (Full-Scale Negative Transition) b. (Full-Scale Positive Transition) Figure 2. Settling Characteristics for with AD6A 7

8 OP AMP SETTLING TIME A MATHEMATICAL MODEL The design of the gives careful attention to optimizing individual circuit components; in addition, a careful tradeoff was made: the gain bandwidth product (4 MHz) and slew rate (2 V/µs) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore stability). Thus designed, the settles to ±.%, with a V output step, in under µs, while retaining the ability to drive a pf load capacitance when operating as a unity gain follower. If an op amp is modeled as an ideal integrator with a unity gain crossover frequency of ω ο /2π, Equation will accurately describe the small signal behavior of the circuit of Figure 3a, consisting of an op amp connected as an I-to-V converter at the output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the op amp s finite slew rate and other nonlinear effects. V O I IN = R R(C f = C X ) s 2 + G N + RC ω f s + (3) ο ω ο where: ω ο =op amp s unity gain frequency 2 π G N = noise gain of circuit + R R O This equation may then be solved for C f : C f = 2 G N + 2 RC Xω ο + ( G N ) (3) Rω ο Rω ο In these equations, capacitor C X is the total capacitor appearing the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit of Figure 3a can be used directly; capacitance C X is the total capacitance of the output of the DAC plus the input capacitance of the op amp (since the two are in parallel). op amp is being simulated or it is the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled. V IN R IN C X C F R R L C L Figure 3b. Simplified Model of the Used as an Inverter In either case, the capacitance C X causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Since the value of C X can be estimated with reasonable accuracy, Equation 2 can be used to choose a small capacitor, C F, to cancel the input pole and optimize amplifier response. Figure 4 is a graphical solution of Equation 2 for the with R = 4 kω. C X G N = 4. G N = 3. G N = 2. G N =. G N = C F I O R O C X C F R R L C L Figure 3a. Simplified Model of the Used as a Current-Out DAC Buffer When R O and I O are replaced with their Thevenin V IN and R IN equivalents, the general purpose inverting amplifier of Figure 26b is created. Note that when using this general model, capacitance C X is either the input capacitance of the op amp if a simple inverting Figure 4. Value of Capacitor C F vs. Value of C X The photos of Figures a and b show the dynamic response of the in the settling test circuit of Figure 6. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A is clamped, amplified by A2 and then clamped again. The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of, amplifying the error signal output of A. 8

9 current-to-voltage converters. The use of a guarding technique such as that shown in Figure 7, in printed circuit board layout and construction is critical to minimize leakage currents. The guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the printed circuit board. Figure a. Settling Characteristics to + V Step Upper Trace: Output of Under Test ( V/Div) Lower Trace: Amplified Error Voltage (.%/Div) Figure 7. Board Layout for Guarding Inputs Figure b. Settling Characteristics to V Step Upper Trace: Output of Under Test ( V/Div) Lower Trace: Amplified Error Voltage (.%/Div) GUARDING The low input bias current ( pa) and low noise characteristics of the BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere D/A CONVERTER APPLICATIONS The is an excellent output amplifier for CMOS DACs. It can be used to perform both 2-quadrant and 4-quadrant operation. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many s, 3R for codes containing a single, and for codes containing all zero, the output impedance is infinite. For example, the output resistance of the AD74 will modulate between kω and 33 kω. Therefore, with the DAC s internal feedback resistance of kω, the noise gain will vary from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance. The K with guaranteed µv offset voltage minimizes this effect to achieve 2-bit performance. 4.99k HP k pf AD34.47 F.47 F 2 V ERROR HP283 TEXTRONIX 7A26 OSCILLOSCOPE PREAMP SELECTION M 2pF DATA DYNAMICS 9 (OR EQUIVALENT FLAT TOP PULSE GENERATOR) V IN k 2k -8pF k k V +V k.k.2-.pf pf V +V Figure 6. Settling Time Test Circuit 9

10 Figures 8 and 9 show the and AD74 (2-bit CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C provides phase compensation to reduce overshoot and ringing. V IN GAIN ADJUST R* V DD V DD V REF DB-DB *FOR VALUES R AND R2, REFER TO TABLE R2* C 33pF R FB OUT AD74 DGND AGND ANALOG COMMON + K C F Figure 8. Unipolar Binary Operation R and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD74 and are shown below. Table I. Recommended Trim Resistor Values vs. Grades of the AD74 for V DD = V TRIM RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD R Ω 2 Ω Ω 2 Ω R2 Ω 68 Ω 33 Ω 6.8 Ω compared to a series of switched trial currents. The comparison point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of A/D input current. Figures a and b show the settling time characteristics of the when used as a DAC output buffer for the AD74. a. Full-Scale Positive b. Full-Scale Negative Transition Transition Figure. Settling Characteristics for with AD74 compared to a series of switched trial currents. The comparison point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of A/D input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open loop value. Most IC amplifiers exhibit a minimum open loop output impedance of 2 Ω due to current limiting resistors. A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input NOISE CHARACTERISTICS The random nature of noise, particularly in the /f region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. The C grade is specified at a maximum level of 4. µv p-p, in a. Hz to Hz bandwidth. Each C receives a % noise test for two -second intervals; devices with any excursion in excess of 4. µv are rejected. The screened lot is then submitted to Quality Control for verification on an AQL basis. All other grades of the are sample-tested on an AQL basis to a limit of 6 µv p-p,. to Hz. DRIVING THE ANALOG OF AN A/D CONVERTER An op amp driving the analog input of an A/D converter, such as that shown in Figure, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In successive-approximation converters, the input current is V ANALOG +V V GAIN ADJUST R2 R OFFSET ADJUST ANALOG COM 2/8 CS A O R/C CE REF IN REF OUT BIP OFF V IN 2V IN ANA COM AD74 STS HIGH BITS MIDDLE BITS LOW BITS +V +V V DIG COM Figure. as ADC Unity Gain Buffer V IN GAIN ADJUST R* V DD *FOR VALUES R AND R2, REFER TO TABLE R2* V DD R FB OUT V REF AD74 AGND DGND DB-DB 2 DATA C 33pF +V K V ANALOG COMMON R4 2k % R3 k % Figure 9. Bipolar Operation R 2k % +V K V

11 voltage. If the A/D conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier s output will return to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The is ideally suited to drive high speed A/D converters since it offers both wide bandwidth and high open-loop gain. a. Source Current = 2 ma b. Sink Current = ma Figure 2. ADC Input Unity Gain Buffer Recovery Times DRIVING A LARGE CAPACITIVE LOAD The circuit in Figure 3 employs a Ω isolation resistor which enables the amplifier to drive capacitive loads exceeding pf; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the Ω series resistor and the load capacitance, C L. Figure 4 shows a typical transient response for this connection. 4.99k TYPICAL CAPACITANCE LIMIT FOR VARIOUS LOAD RESISTORS R L C L UP TO 2k pf k pf 2k pf +V S V S 3pF 4.99k C L R L OUTPUT Figure 3. Circuit for Driving a Large Capacitive Load large value input resistors, bias currents flowing through these resistors will also generate an offset voltage. In addition, at higher frequencies, an op amp s dynamics must be carefully considered. Here, slew rate, bandwidth, and open-loop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier s bandwidth in conjunction with the filter s gain will dictate the frequency response of the filter. The use of a high performance amplifier such a s the will minimize both dc and ac errors in all active filter applications. SECOND ORDER LOW PASS FILTER Figure depicts the configured as a second order Butterworth low pass filter. With the values as shown, the corner frequency will be 2 khz; however, the wide bandwidth of the permits a corner frequency as high as several hundred kilohertz. Equations for component selection are shown below. R = R2 = user selected (typical values: kω kω) (4).44 C= (2 π)( f cutoff )(R), C2 =.77 (2 π)( f cutoff )(R) Where: C and C2 are in farads. V IN R 2k R2 2k C2 28pF C 6pF +V V Figure. Second Order Low Pass Filter An important property of filters is their out-of-band rejection. The simple 2 khz low pass filter shown in Figure, might be used to condition a signal contaminated with clock pulses or sampling glitches which have considerable energy content at high frequencies. The low output impedance and high bandwidth of the minimize high frequency feedthrough as shown in Figure 6. The upper trace is that of another low-cost BiFET op amp showing 7 db more feedthrough at MHz. () Figure 4. Transient Response R L = 2 kω, C L = pf ACTIVE FILTER APPLICATIONS In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier s offset voltage and bias current contribute to output error. Offset voltage will be passed by the filter and may be amplified to produce excessive output offset. For low frequency applications requiring Figure 6.

12 9-POLE CHEBYCHEV FILTER Figure 7 shows the and its dual counterpart, the AD72, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNR). With a cutoff frequency of khz and better than 9 db rejection, it may be used as an anti-aliasing filter for a 2-bit data acquisition system with khz throughput. As shown in Figure 7, the filter is comprised of four FDNRs (A, B, C, D) having values of and.9276 farad-seconds. Each FDNR active network provides a 2-pole response; for a total of 8 poles. The 9th pole consists of a. µf capacitor and a 24 kω resistor at Pin 3 of amplifier A2. Figure 8 depicts the circuits for each FDNR with the proper selection of R. To achieve optimal performance, the. µf capacitors must be selected for % or better matching and all resistors should have % or better tolerance. +V +V V IN A V. F E.9276E.9276E 4.939E A * B * C * D * k * SEE TEXT 4.99k 28. F 24k A2 V 4.99k Figure 7. 9-Pole Chebychev Filter +V /2 AD72. F R. F k /2 AD72 V R: 24.9k FOR 4.939E 29.4k FOR.9276E 4.99k Figure 8. FDNR for 9-Pole Chebychev Filter Figure 9. High Frequency Response for 9-Pole Chebychev Filter 2

13 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP Package (N-8) Cerdip Package (Q-8). (.3) MIN. (.3) MAX PIN.7(4.44).6(4.9).(3.94).2 (3.8) MIN.23(.4).8(.46).(.38) (9.9) MAX. (2.4) TYP.33 (.84) NOM.2 (6.3).4(.4).3(.89).2(.64).2(.33).8(4.7).(3.8) SEATING PLANE..3 (7.62) REF.4(.36).(.28).8(.2) PIN.2 (.8) MAX.2 (.8).2 (3.8) 8 4. (2.4) BSC.4 (.29) MAX.23 (.8).4 (.36).3 (7.87).22 (.9).6 (.2). (.38). (3.8) MIN SEATING.7 (.78) PLANE.3 (.76).32 (8.3).29 (7.37). (.38).8 (.2) Small Outline Package (R-8).2 (.).93 (4.9).7 (4.8).8 (4.).4 (3.9). (3.8) (6.2).236 (6.).224 (.8) PIN.2 (.278).8 (.23).4 (.28) SEATING PLANE. (.27) BSC.2 (.49).7 (.42).4 (.3).4 (2.72).98 (2.49).92 (2.26).3 (.3). (.269).9 (.238). (.26).33 (.83).6 (.4) TO-99 Package (H-8).4 (.) MAX SEATING PLANE INSULATION. (.27) MAX 8 LEADS.9 (.48).6 (.4) DIA.37 (9.4).33 (8.).33 (8.).3 (7.7).8 (4.7).6 (4.9). (2.7) MIN REFERENCE PLANE.2 (.) TYP (.86).28 (.7).4 (.4).2 (.) 4 EQUALLY SPACED BOTTOM VIEW 3

14 Revision History Location Page Data Sheet changed from REV. A to. Edits to ORDERING GUIDE Deleted METALIZATION PHOTOGRAPH

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16 PRINTED IN U.S.A. C832 /2(B) 6