Finite Element Modelling and Experimental Characterisation of Paralleled SiC MOSFET Failure under Avalanche Mode Conduction

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1 Finite Element Modelling and Experimental Characterisation of Paralleled SiC MOSFET Failure under Avalanche Mode Conduction Ji Hu, Olayiwola Alatise, Jose Angel Ortiz-Gonzalez, Petros Alexakis, Li Ran and Phil Mawby School of Engineering University of Warwick Coventry, United Kingdom Tel.: +44 (0) Fax: +44 (0) URL: Acknowledgements This work was supported by the UK Engineering and Physical Science Research Council (EPSRC) through the Underpinning Power Electronics Devices Theme (EP/L007010/1) and the Components Theme (EP/K034804/1). Keywords «Device characterization», «Silicon Carbide (SiC)», «High temperature electronic», «Unclamped inductive switching» I. Abstract This paper investigates the physics of device failure during avalanche mode conduction for SiC MOSFETs. SiC devices have been shown to have superior electro-thermal ruggedness during unclamped inductive switching (UIS) compared with similarly rated silicon IGBTs [1]. Failure during UIS normally results from parasitic BJT latch-up which is exacerbated at higher temperatures [2, 3]. Measurements show that the total avalanche energy conducted by the device improves when the UIS occurs over longer avalanche duration with a smaller peak avalanche current as opposed to a higher peak avalanche current over a shorter duration. This is due to the fact that cell-to-cell (or die-todie) variations in electrical parameters are more critical during peak avalanche current conduction. Power MOSFETs are comprised to numerous FET cells internally connected to common source, drain and gate terminals and the density of which is determined by the cell pitch and die area. These FET cells are normally assumed to be uniform in electro-thermal properties, however, there are variations in parameters like thermal resistance, gate resistance, oxide thickness, body doping, etc. Finite element models of 2 FET cells within a MOSFET show how variations in gate resistance and thermal resistance (initial junction temperature) degrade the devices reliability under UIS and that this is more critical for higher avalanche currents. The finite element models are supported by experimental measurements designed to emulate the effect of inter-cell variation. II. Introduction As power semiconductor devices operate as switches in electrical systems, energy stored in inductive loads such as motors or coils may be dissipated in the device through unclamped or quasiclamped inductive switching[4, 5]. The reliability of the power device under such conditions is thus critical. There are 2 known failure modes of power devices conducting current under avalanche conditions. These are (1) BJT latch-up caused by high avalanche currents dissipated over short avalanche durations (smaller inductances)[1, 6-8] and (2) Intrinsic temperature limitations more associated with low avalanche currents dissipated by the device over longer avalanche durations (large inductances) [9-13]. Hence, UIS characterisation of power devices on manufacturer datasheets often show the maximum avalanche energy dissipated at different inductances and ambient temperatures. Parasitic BJT latch-up occurs when the BJT inherent in the structure of the power MOSFET inadvertently turns on as a result of the emitter base voltage being forward biased due to a voltage drop between the MOSFET source and the p-body [8]. This failure mode is exacerbated by variations in the electrical parameters between different cells in the MOSFET which cause non-uniform current distribution and temperature surges in the device [14, 15]. On a larger scale, different MOSFETs paralleled together for the purpose of conducting higher forward currents may also show some

2 variations in electro-thermal switching parameters. These variations will likewise cause non-uniform current and temperature distributions in the module which have the potential to limit the overall reliability. This failure mechanism is all the more pertinent to SiC power devices were small active areas mean numerous devices are required in parallel to deliver higher current ratings. In this paper, experimental measurements and simulations have been performed in order to investigate the impact of these electro-thermal non-uniformities on the overall maximum avalanche energy that the devices are capable of dissipating without failure. Non-uniformities have been investigated by connecting 2 SiC devices in parallel and forcing them into unclamped inductive switching. Variations in the electrical switching time constants are introduced between the 2 devices by using different gate resistances. Variations in the thermal resistances are also introduced between the devices by using 2 different initial junction temperatures. Simulations have also been performed using finite element models to investigate the impact of these variations. Section II describes the experimental measurements and results, section III presents the finite element simulations while section IV concludes the paper. II. Experimental Measurements Figure 1a shows the circuit diagram of the UIS test rig which comprises of a power supply, gate drive system, avalanche inductor and device-under-test (DUT). The operation of the circuit is two-fold. Firstly, the DUT is switched on to charge the inductor after which it is switched off thereby forcing the inductor to discharge current into the DUT and driving the DUT into avalanche. Figure 1b shows the typical avalanche characteristics of a power MOSFET. A 1.2kV/24A SiC Power MOSFET has been subjected to different avalanche currents, durations and temperatures using the test set-up shown in Figure (1a). When the ambient temperature is increased, the maximum current that the device can reliably conduct in avalanche reduces. This is because the headroom for conducting avalanche power is lowered since a smaller rise in temperature is capable of causing the parasitic BJT to latch-up. Figure 2(a) shows the drain source avalanche current characteristics for the SiC MOSFET at different temperatures where it can be seen that latch-up occurs at higher temperatures. These test conditions purposefully exceed the conditions stated on the device datasheets. Figure 2b shows an example of a SiC device that has failed under UIS where the burn mark due to high temperature surges can be seen. Further avalanche experiments were conducted on the SiC Power MOSFET with different avalanche inductors used to modulate the avalanche duration. The results are shown in Figure 3(a), where the maximum avalanche current is plotted as a function of temperature for different inductor sizes. It was noticed from the measurements that the maximum avalanche current reduces as the inductor size increases. Figure 3(a) shows the calculated avalanche energy for each test condition as a function of temperature where it can be seen that the total avalanche energy reliably conducted by the DUT increases with the size of the inductor. This means that the MOSFET is more avalanche rugged when the avalanche energy is in the form of a smaller avalanche current and a longer avalanche duration. Figure 3(b) shows the avalanche current as a function of time for 2 test occasions where the

3 SiC MOSFET exhibited thermal runaway. In Figure 3(b), it can be seen that the larger inductor causes thermal runaway at a lower avalanche current although the calculated avalanche energy is higher. Figure 3(c) shows the experimental circuit used to investigate the impact of variations in electro-thermal parameters affect the robustness of the MOSFETs in avalanche mode conduction. The operation of the experiment is the same as the UIS test rig shown in Figure 1(a). In the ideal case, the current should be shared equally between the DUTs since the devices have identical electro-thermal properties. In the experiments, performed, different gate resistances (10 Ω on DUT1 and 33 Ω on DUT2) and different junction temperatures (25 ⁰C on DUT1 and 50 ⁰C on DUT2) have been applied on the DUTs. Figure 3(d) shows the gate charging and avalanche characteristics derived from the measurements for both devices with one device failing. Figure 3(e) shows the avalanche current characteristics of the 2 DUTs under UIS with different gate resistances. It can be seen that the DUT with R G =33 Ω fails whereas the DUT with R G =33 Ω does not. This is due to the fact that the slower switching device (R G =33 Ω) turns off more slowly and therefore is more conductive during turn off compared to the faster switching device (R G =10 Ω). Figure 3(f) shows the avalanche current characteristics of the 2 DUTs switching with different initial temperatures (i.e. thermal resistances) where it can be seen that the DUT with the lower initial temperature surprisingly fails the test while the DUT with the higher junction temperature does not. The tests have been repeated several times for verification. It is thought that this observation is due to the fact that the breakdown voltage of the devices increase with temperature, hence, the DUT with the higher initial temperature has a higher breakdown voltage. The increase in breakdown voltage with temperature is due to increased phonon scattering and reduced carrier mean free path delaying the onset of avalanche multiplication. Since avalanche current flows through the device with the lower breakdown voltage, then the DUT with T J =25 ⁰ disproportionately conducts the avalanche current and fails. At this point, the impact of the avalanche duration (inductor size) on this observation is not clear and will be the point of further research.

4 III. Finite Element Simulations Finite element models have been performed on SiC power MOSFETs under avalanche mode conduction so as to gain a deeper insight into the physics of device failure with 2 parallel devices. Initially a single device is simulated so as to gain deeper insight into the electrothermal interactions within the device during thermal runaway. The model was simulated in ATLAS from SILVACO and included lattice-heating and impact ionization together with the traditional continuity/poisson equations for carrier transport. The drift layer doping and thickness was optimized to achieve the desired breakdown voltage in SiC. To correctly model the on-state current, Shockley-Read-Hall (SRH) recombination was used together with concentration dependent mobility for the electrons in the MOSFET channel. A p-body doping of 1 x cm -3 was used in combination with a 1 x cm -3 p+ doping for the body diode shorting the source to the body. The source and drain regions were degenerately doped with n+ and an oxide thickness of 50 nm was used for the gate dielectric. A mixed mode circuit and device simulator was used to perform the transient circuit simulations. The initial results for the single device in avalanche are shown in Figure 4(a) to 4(d). It can be seen that the device has failed in BJT latch-up during avalanche mode conduction. Figure. 4(a) shows the simulated avalanche current which is marked in 3 locations X, Y and Z. Figure 4(b) shows the 2- dimensional current density contour plot obtained from the finite element model at the point in time X (shown in Figure 4(a)). The 2D contour plot is useful for understanding the current distribution within the device. At time X, the MOSFET is in the on-state and is therefore conducting current normally through the channel adjacent to the gate dielectric. Figure 4(b) shows that the maximum current density occurs in the channel of the device just under the gate oxide which is expected since the channel in inverted. The circuit schematic in Figure 4(b) shows the equivalent circuit diagram of the MOSFET and the arrow indicates the direction the current is in. Figure 4(c) shows the 2D current density field plot of the MOSFET when the channel has been switched off and the device is conducting current in avalanche mode which corresponds to time Y in Figure 4(a). It can be seen in Figure 4(c) that the maximum current in the device occurs in the in-built body diode of the MOSFET.

5 If the device is to conduct the entire avalanche current reliably, then the current would be confined to the body diode. The equivalent circuit schematic of the MOSFET in Figure 4(c) shows the direction of the current through the body diode. Figure 4(d) shows the 2D current density plot at instant Z when the current through the device begins to rise again as a result of the parasitic internal BJT latching up. At this point, the 2D current density field plot shows that the maximum current density has been diverted from the body diode to the npn BJT which has been triggered. The circuit schematic now indicates that the current is flowing through the BJT. Although the simulations in Figure 4(a) to 4(d) show the dynamics of current flow during avalanche, they however, do not account for the impact of neighbouring cells because it simulates a single FET cell. As stated previously, cell-to-cell non-uniformity triggers BJT latch-up. Latch-up occurs when the avalanche current has a positive temperature coefficient which means it increases with temperature forming a positive feedback/regenerative process that is unstable. When this happens, current from neighbouring cells is diverted to failing cell thereby causing hot-spots and device failure. The following sub-sections show finite element simulations of 2 FET cells that investigate the impact of varying electrical parameters.

6 3.1 Variations in the initial junction temperature The temperature is critical for determining the electro-thermal behaviour of the device. In critical conditions like avalanche mode conduction, a significant amount of energy dissipates in the device causing a temperature surge hence, the uniform sharing of current is critical for reliability since BJT latch-up is temperature and current activated. As power devices operate in normal conditions, solder delamination and/or voiding due to thermo-mechanical stress cycling arising from CTE mismatch between the die and the substrate causes the thermal resistance and hence, operating junction temperature to increase. The increase in thermal resistance will often not occur uniformly; hence, paralleled devices will operate at different junction temperatures due to different thermal resistances. To investigate this effect, finite element models of power MOSFETs comprising of two different cells switching in parallel have been performed. The two parallel cells have been simulated with identical and different junction temperatures to simulate the effect of different thermal resistances. Figure 5(a) shows the simulated avalanche current characteristics for the two simulations i.e. equal and unequal junction temperatures between the devices. It can be seen from Figure 5(a) that the parallel cells with equal temperature withstands the avalanche current whereas the parallel cells with different initial temperature suffers latch-up. Figure 5(b) to (d) show the 2D current density contour field plots for the parallel FET cells at the different points in time marked in Figure 5(a). Figure 5(b) shows the 2D current density contour plot at point X (in Figure 5(a)) where is can be seen that the two channels have roughly same current conducted through the channel. This is normal mode of current conduction (drift-diffusion current through an inverted channel) with the highest current density occurring in the n+ source and in the inverted channel. It can be seen from Fig. 5(b) that the device operating with the lower junction temperature is conducting more current as a result of the reduced on-state resistance. Figure 5(c) shows the 2D current density contour plot for the case of the non-equal ambient temperature (T J1 T J2 ) marked as point Y in Figure 5(a). It can be seen in Fig. 5(c) that the bulk of the avalanche current is flowing through the body diodes of both MOSFETs as it should in devices conducting avalanche current reliably. Upon closer inspection in Fig. 5(c), it can be seen that the device with the lower junction temperature on the right has a higher avalanche current compared to the device with the higher junction temperature. This is due to the fact that the left hand MOSFET has a higher junction temperature, hence, will operate with a higher breakdown voltage since the breakdown voltage of MOSFET increases with temperature. Figure 5(d) shows the 2D current density plot of both FETs at point Z marked in 5(a). At this point, the device with the lower junction temperature is in BJT latch-up induced thermal runaway thereby diverting all the current away from the device with the higher junction temperature. It is evident from Fig. 5(d) that the avalanche current now flows through the internal BJT of the MOSFET and not the body diode. These simulations effectively explain the experimental measurements presented earlier in Figure 3(f). Figure 5(a) The simulated avalanche current is shown as a function of time for the parallel switched MOSFET cells with equal ambient temperature between both cells (T 1 =T 2 ) and non-equal ambient temperature (T 1 T 2 ).

7 3.2 Variations in the Gate Resistance Although the FET cells in power MOSFETs are connected to a common gate electrode, in reality, the cells will have different gate resistances due to the different physical distances from the gate electrode i.e. the gate electrode is made of poly-silicon, hence will have a non-negligible resistance. Hence, cells closer to the gate will have lower gate resistances compared to cells farther away. Furthermore, degradation in the mechanical integrity of the gate wire due to thermal cycling can contribute to nonuniformity in the gate resistances of power devices. This is all the more pertinent to SiC power devices where higher switching frequencies are expected to increase power density. The 2-cell power MOSFET has been simulated under avalanche conditions with (i) both gate resistances of the 2 FET cells being equal and (ii) the gate resistances of the 2 FET cells being unequal. The simulation results are shown in Figure 6(a) where it can be seen that the 2-cell MOSFET simulated with R G1 =R G2 is more avalanche rugged than that with R G1 R G2. Figures 6(b) to 6(d) show the 2D current density contour plots at points X, Y and Z respectively for the device with R G1 R G2. In Figures 6(b) to 6(d), the FET

8 cell on the left is switched with R G =10 Ω whereas that the right is switched with R G =50 Ω. It can be seen from Figure 6(b), which corresponds to point X in Figure 6(a), that the current density in the 2 channels is equal, which is expected since differences in the gate resistance will not affect the steadystate current density. In Figure 6(c), corresponding to point Y, the entire avalanche current is being conducted through the right hand cell which has the higher gate resistance. It can be seen in Figure 6(c), that the avalanche current flows through the MOSFET channel as well as through the npn BJT. This is due to the fact that the MOSFET turns off more slowly compared to the cell on the left (with R G =10 Ω), hence, as the avalanche current begins to flow, it is diverted to the right hand cell because the channel is still conductive. Figure 6(d) shows the 2D current density contour plot corresponding to point Z, where it can be seen that the device is in full BJT latch-up. The temperature build-up in the right hand cell of the device has triggered thermal runaway, hence, none of the avalanche current flows through the cell on the left with R G =10 Ω. IV. Conclusions This paper presents experimental measurements together detailed finite element electrothermal models in the analysis of paralleled power MOSFET failure under unclamped inductive switching conditions. Experiments show that the variations of gate resistance and junction temperature between paralleled MOSFET devices reduce robustness as a whole in avalanche mode conduction. These experiments have been explained by simulations explaining the internal physics of current distribution between parallel devices under UIS. In the case of the junction temperature non-uniformity (simulating different thermal resistances), cells/devices with lower initial junction temperature experience BJT latch-up first thereby reducing the total avalanche ruggedness of the power device. This is thought to be due to the positive temperature coefficient of the breakdown voltage which means that the avalanche current crowds into the lower temperature device (by virtue of its low breakdown voltage) thereby causing hot-spotting/current crowding. In the case of non-uniformity in the gate resistance, the slower switching cell conducts all the avalanche current because the cell is still conductive at the time

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