Figure 1. Package. Table 1. Order Codes V CC 1A C30 OUT1A OUT1A GND1A V CC1B C31 OUT1B OUT1B M4 13 GND1B 22 V SS REGULATORS 7 V CC2A C32 M17 OUT2A

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1 40V 3.5A QUAD POWER HALF BRIDGE 1 FEATURES MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 0mΩ R dson COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION 2 DESCRIPTION STA505 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half Figure 1. Package Table 1. Order Codes Part Number STA505 STA50513TR PowerSO3 Package PowerSO3 in Tape & Reel current capability. The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDX ) amplifier capable to deliver 50 + THD = 10% at V cc 30V output power on 8Ω load and THD = 10% at V cc 3V on 8Ω load in single BTL configuration. The input pins have threshold proportional to V L pin voltage. Figure 2. Audio Application Circuit (Dual BTL)Pin Description V CC 1A +V CC VL +3.3V CONFIG PWRDN PWRDN R57 R59 FAULT 10K 10K TRI-STATE C PROTECTIONS & LOGIC M3 M2 M C30 GND1A V CC1B C31 OUT1B L18 22µH C C52 330pF R98 R3 R100 C21 C99 C23 470nF C101 C µF 8Ω M4 13 OUT1B GND1B L19 22µH REGULATORS 7 V CC2A C58 C53 V CCSIGN 35 C0 V CCSIGN 3 IN2A IN2A 31 GND-Reg GND-Clean 19 IN2B IN2B 32 M17 M15 M C32 OUT2A OUT2A GND2A V CC2B C33 L113 22µH C110 C pF R103 R104 R102 C111 L112 22µH C107 C nF C10 8Ω GNDSUB 1 M14 5 GND2B D00AU1148B November 04 REV. 10 1/10

2 Table 2. Pin Function N Pin Description 1 GND-SUB Substrate ground 2 ; 3 Output half bridge 2B 4 Vcc2B Positive Supply 5 GND2B Negative Supply GND2A Negative Supply 7 Vcc2A Positive Supply 8 ; 9 OUT2A Output half bridge 2A 10 ; 11 OUT1B Output half bridge 1B 12 Vcc1B Positive Supply 13 GND1B Negative Supply 14 GND1A Negative Supply 15 Vcc1A Positive Supply 1 ; 17 Output half bridge 1A 18 NC Not connected 19 GND-clean Logical ground GND-Reg Ground for regulator Vdd 21 ; 22 Vdd 5V Regulator referred to ground 23 VL High logical state setting voltage 24 CONFIG Configuration pin 29 Input of half bridge 1A 25 PWRDN Stand-by pin 2 TRI-STATE Hi-Z pin 27 FAULT Fault pin advisor 28 TH-WAR Thermal warning advisor 29 Input of half bridge 1A 30 Input of half bridge 1B 31 IN2A Input of half bridge 2A 32 IN2B Input of half bridge 2B 33 ; 34 Vss 5V Regulator referred to +Vcc 35 ; 3 Vcc Sign Signal Positive Supply 2/10

3 Table 3. Functional Pin Status PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal..) FAULT (*) 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation (*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) Figure 3. Pin Connection PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130C (*) THWAR 1 Normal operation CONFIG 0 Normal Operation (**) CONFIG 1 =OUT1B ; OUT2A= (IF = ; IN2A = IN2B) V CC Sign V CC Sign IN2B IN2A FAULT TRI-STATE PWRDN CONFIG V L GND-Reg GND-Clean GND-SUB V CC 2B GND2B 31 GND2A 30 7 V CC 2A 29 8 OUT2A 28 9 OUT2A OUT1B 2 11 OUT1B V CC 1B GND1B GND1A V CC 1A N.C. D01AU1273 3/10

4 Table 4. Absolute Maximum Ratings Symbol Parameter Value Unit V CC DC Supply Voltage (Pin 4,7,12,15) 40 V V max Maximum Voltage on pins 23 to V T op Operating Temperature Range 0 to 70 C T stg, T j Storage and Junction Temperature -40 to 150 C Table 5. Thermal Data Symbol Parameter Min. Typ. Max. Unit T j-case Thermal Resistance Junction to Case (thermal pad) 2.5 C/W T jsd Thermal shut-down junction temperature 150 C T warn Thermal warning temperature 130 C t hsd Thermal shut-down hysteresis 25 C Table. Electrical Characteristcs (V L = 3.3V; V cc = 30V; T amb = 25 C; f sw = 384Khz; unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit R dson I dss Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Id=1A; mω Vcc=35V 50 µa g N Power Pchannel RdsON Matching Id=1A 95 % g P Power Nchannel RdsON Matching Id=1A 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig ns Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω Id=3.5A; see fig ns t d ON Turn-on delay time Resistive load 100 ns t d OFF Turn-off delay time Resistive load 100 ns t r Rise time Resistive load; as fig.1; 25 ns t f Fall time Resistive load; as fig. 1; 25 ns V CC Supply voltage operating voltage 10 3 V V IN-High High level input voltage V L /2 +300mV V IN-Low Low level input voltage V L /2-300mV V V I IN-H High level Input current Pin voltage = V L 1 µa I IN-L Low level input current Pin voltage = 0.3V 1 µa 4/10

5 Symbol Parameter Test conditions Min. Typ. Max. Unit I PWRDN-H V Low V High I VCC- PWRDN I FAULT I VCC-hiz High level PWRDN pin input current Low logical state voltage VLow (pin PWRDN, TRISTATE) (note 1) High logical state voltage VHigh (pin PWRDN, TRISTATE) (note 1) Supply current from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate 35 µa V L = 3.3V 0.8 V V L = 3.3V 1.7 V PWRDN = 0 3 ma Vpin = 3.3V 1 ma Tri-state=0 22 ma I VCC Supply current from Vcc in operation both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; 50 ma I VCC-q Isc (short circuit current limit) (note 2) A V UV Undervoltage protection threshold 7 V t pw-min Output minimum pulse width No Load ns Table 7. Notes: 1. The following table explains the VLow, VHigh variation with V L V L VLow min VHigh max Unit V V V Note 2: See relevant Application Note AN1994 Table 8. Logic Truth Table (see fig. 5) TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z OFF OFF ON ON DUMP OFF ON ON OFF NEGATIVE ON OFF OFF ON POSITIVE ON ON OFF OFF Not used 5/10

6 Figure 4. Test Circuit. OUTxY Vcc Low current dead time = MAX(DTr,DTf) +Vcc (3/4)Vcc (1/2)Vcc (1/4)Vcc Duty cycle = 50% INxY M58 OUTxY DTr R 8Ω DTf t M57 gnd + - V7 = vdc = Vcc/2 D03AU1458 Figure 5. +V CC Q1 Q2 INxA OUTxA OUTxB INxB Q3 Q4 GND D00AU1134 Figure. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +V CC Duty cycle=a DTout(A) Duty cycle=b DTin(A) INxA M58 Q1 OUTxA L7 22µ Iout=4.5A Rload=8Ω Q2 DTout(B) OUTxB L8 22µ Iout=4.5A M4 DTin(B) INxB M57 Q3 C9 470nF C71 470nF C70 470nF Q4 M3 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D00AU112A /10

7 Figure 7. Typical Single BTL Configuration to Obtain THD 10%, R L = 8Ω, V CC = 3V (note 1) +3.3V 10K npwrdn 10K VL GND-Clean GND-Reg CONFIG PWRDN FAULT TRI-STATE IN2A IN2B V CC SIGN N.C OUT1B OUT1B OUT2A OUT2A V CC 1A V CC 1B V CC 2A V CC 2B GND1A GND1B 22Ω 1/2W 330pF 22µH 22µH.2 1/2W.2 1/2W FILM FILM 20µF 3V 470nF FILM +3V +3V 8Ω Add. V CC SIGN GNDSUB GND2A GND2B D01AU1274 Note: 1. "A PWM modulator as driver is needed. In particular, this result is performed using the STA30X+STA50X demo board". Figure 8. Typical Quad Half Bridge Configuration V CC1P +V CC +3.3V R57 10K PWRDN R59 10K V L CONFIG PWRDN FAULT PROTECTIONS & LOGIC M3 M OUTPL OUTPL PGND1P V CC1N R41 C41 330pF L11 22µH C71 R51 C81 R1 R2 C31 8µF C91 4Ω C21 20µF C58 TRI-STATE 28 M C51 OUTNL C1 L12 22µH R3 C32 8µF REGULATORS M OUTNL PGND1N V CC2P R42 C42 330pF C72 R52 C82 R4 C92 4Ω C58 C53 V CCSIGN C0 V CCSIGN IN2A IN2A GND-Reg M17 M OUTPR OUTPR PGND2P V CC2N R43 C43 330pF L13 22µH C73 R53 C83 R5 R C33 8µF C93 4Ω GND-Clean 19 IN2B IN2B 32 GNDSUB 1 M1 M14 C52 3 OUTNR 2 OUTNR 5 PGND2N D03AU1474 C2 R44 C44 330pF L14 22µH C74 R54 C84 R7 R8 C34 8µF C94 4Ω For more information refer to the application notes AN145 and AN11 7/10

8 Figure 9. Power SO3 (Slug up) Mechanical Data & Package Dimensions DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A A A a b c D D D E E E E E e e G H h L N s 8 8 (1) D and E1 do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.00 ) (2) No intrusion allowed inwards the leads. OUTLINE AND MECHANICAL DATA PowerSO3 (SLUG UP) D 8/10

9 Table 9. Revision History Date Revision Description of Changes December 03 8 First Issue in EDOCS DMS June 04 9 Note 2: See relevant Application Note AN1994 November Changed Vcc in Electrical Characteristics from 9 min to 10 min 9/10

10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners DDX is a trademark of Apogee tecnology inc. 04 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 10/10

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) STA501A 45V 3.5A DOUBLE POWER HALF BRIDGE 1 FEATURES 2 DESCRIPTION

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) STA501A 45V 3.5A DOUBLE POWER HALF BRIDGE 1 FEATURES 2 DESCRIPTION 45V 3.5A DOUBLE POWER HALF BRIDGE 1 FEATURES MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200mΩ R dson COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION