STA506 40V 4A QUAD POWER HALF BRIDGE

Size: px

Start display at page:

Download "STA506 40V 4A QUAD POWER HALF BRIDGE"

Gilbert George
5 years ago
Views:

1 40V 4A QUAD POWER HALF BRIDGE FEATURES MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 0mΩ R dson COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION SHORT CIRCUIT PROTECTION DESCRIPTION STA50 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed MULTIPOWER BCD TECHNOLOGY Table. Order Code Part Number STA50 PowerSO3 Package PowerSO3 to make the output stage of a stereo All-Digital High Efficiency (DDX ) amplifier capable to deliver 0 + THD = 0% at V cc 3V output power on 8Ω load and THD = 0% at V CC 3V on 8Ω load in single BTL configuration. In single BTL configuration is also capable to deliver a peak of = 0% at V CC = 3V on 4Ω load (t sec). The input pins have threshold proportional to V L pin voltage. Figure. APPLICATION CIRCUIT (Dual BTL) V CC A +V CC +3.3V TH_WAR R57 0K R59 0K C58 INA INA VL CONFIG FAULT TRI-STATE TH_WAR PROTECTIONS & LOGIC M3 M M OUTA C30 OUTA GNDA V CC B OUTB C3 L8 µh C5 330pF R3 C R98 R00 C C99 C3 470nF C0 8Ω C55 000µF INB INB V DD 30 M4 3 OUTB GNDB L9 µh V DD C58 C53 C0 INA INB V CC SIGN V CC SIGN INA GND-Reg GND-Clean 9 INB 3 REGULATORS M7 M5 M V CC A OUTA C3 OUTA GNDA V CC B OUTB OUTB C33 L3 µh C09 330pF R04 C0 R03 R0 C L µh C07 C08 470nF C0 8Ω GNDSUB M4 5 GNDB D00AU48B June 04 REV. 4 /4

2 Table. PIN FUNCTION Pin n. Pin Name Description GND-SUB Substrate Ground ; 3 OUTB Output Half Bridge B 4 V CC B Positive Supply 5 GNDB Negative Supply GNDA Negative Supply 7 V CC A Positive Supply 8 ; 9 OUTA Output Half Bridge A 0 ; OUTB Output Half Bridge B V CC B Positive Supply 3 GNDB Negative Supply 4 GNDA Negative Supply 5 V CC A Positive Supply ; 7 OUTA Output Half Bridge A 8 NC Not Connected 9 GND-clean Logical Ground GND-Reg Ground for Regulator V dd ; V dd 5V Regulator Referred to Ground 3 VL Logic Reference Voltage 4 CONFIG Configuration pin 5 Stand-by pin TRI-STATE Hi-Z pin 7 FAULT Fault pin advisor 8 TH-WAR Thermal warning advisor 9 INA Input of Half Bridge A 30 INB Input of Half Bridge B 3 INA Input of Half Bridge A 3 INB Input of Half Bridge B 33 ; 34 5V Regulator Referred to +V CC 35 ; 3 V CC Sign Signal Positive Supply /4

3 Table 3. FUNCTIONAL PIN STATUS Pin name Pin n. Logical value IC -STATUS FAULT 7 0 Fault detected (Short circuit, or Thermal..) FAULT (*) 7 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE Normal operation 5 0 Low absorpion 5 Normal operation THWAR 8 0 Temperature of the IC =30 C THWAR (*) 8 Normal operation CONFIG 4 0 Normal Operation CONFIG (**) 4 OUTA = OUTB ; OUTA=OUTB (IF INA = INB; INA = INB) (*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = means connect Pin 4 (CONFIG) to Pins, (Vdd) to implement single BTL (mono mode) operation for high current. Figure. PIN CONNECTION V CC Sign V CC Sign INB INA INB INA TH_WAR FAULT TRI-STATE CONFIG VL VDD VDD GND-Reg GND-Clean GND-SUB OUTB OUTB V CC B GNDB 3 GNDA 30 7 V CC A 9 8 OUTA 8 9 OUTA 7 0 OUTB OUTB 5 V CC B GNDB GNDA V CC A 7 OUTA OUTA 9 8 N.C. D0AU73 3/4

4 Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CE DC Supply Voltage (Pin 4,7,,5) 40 V V max Maximum Voltage on pins 3 to 3 (logic reference) 5.5 V P tot Power Dissipation (T case = 70 C) 50 W T op Operating Temperature Range 0 to 70 C T stg, T j Storage and Junction Temperature -40 to 50 C Table 5. (*) RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit V CC DC Supply Voltage V V L Input Logic Reference v T amb Ambient Temperature 0 70 C (*) performances not guaranteed beyond recommended operating conditions Table. THERMAL DATA Symbol Parameter Min. Typ. Max. Unit T j-case Thermal Resistance Junction to Case (thermal pad).5 C/W T jsd Thermal shut-down junction temperature 50 C T warn Thermal warning temperature 30 C t hsd Thermal shut-down hysteresis 5 C Table 7. ELECTRICAL CHARACTERISTCS: refer to circuit in Fig. (V L = 3.3V; V CC = 3V; R L = 8Ω; fsw = 384KHz; T amb = 5 C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit R dson Power Pchannel/Nchannel Id=A 0 70 mω MOSFET RdsON I dss Power Pchannel/Nchannel leakage Idss V CC =35V 50 µa g N Power Pchannel RdsON Id=A 95 % Matching g P Power Nchannel RdsON Matching Id=A 95 % Dt_s Low current Dead Time (static) see test circuit no.; see fig. 3 0 ns Dt_d High current Dead Time (dinamic) L=µH; C = 470nF; R L = 8 Ω Id=3.5A; see fig ns t d ON Turn-on delay time Resistive load 00 ns t d OFF Turn-off delay time Resistive load 00 ns t r Rise time Resistive load; as fig.3 5 ns t f Fall time Resistive load; as fig. 3 5 ns V CC Supply voltage operating voltage 9 3 V V IN-H High level input voltage V L / +300mV V 4/4

5 TABLE. ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit V IN-L Low level input voltage V L / - 300mV I IN-H Hi level Input current Pin Voltage = V L µa I IN-L Low level input current Pin Voltage = 0.3V µa I -H Hi level pin input current V L = 3.3V 35 µa V LOW V HIGH I VCC- I FAULT I VCC-hiz I VCC Low logical state voltage VLow (pin, TRISTATE) (note ) High logical state voltage VHigh (pin, TRISTATE) (note ) Supply CURRENT from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply Current from Vcc in Tristate Supply Current from Vcc in operation both channel switching) V L = 3.3V 0.8 V V L = 3.3V.7 V = 0 3 ma Vpin = 3.3V ma V CC = 30V; Tri-state = 0 ma V CC =30V; Input Pulse width = 50% Duty; Switching Frequency = 384KHz; No LC filters; V 50 ma I VCC-q Isc (short circuit current limit) 4 8 A (note ) V OUT-SH Undervoltage protection threshold 7 V V OV Output minimum pulse width No Load ns Notes:. The following table explains the V LOW, V HIGH variation with V L Table 8. V L V LOW min V HIGH max Unit V V V Note : See relevant Application Note AN994 Table 9. LOGIC TRUTH TABLE (see fig. 4) TRI-STATE INxA INxB Q Q Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 0 0 OFF OFF ON ON DUMP 0 OFF ON ON OFF NEGATIVE 0 ON OFF OFF ON POSITIVE ON ON OFF OFF Not used 5/4

6 Figure 3. Test Circuit. OUTxY Vcc Low current dead time = MAX(DTr,DTf) +Vcc (3/4)Vcc (/)Vcc (/4)Vcc Duty cycle = 50% INxY M58 OUTxY DTr R 8Ω DTf t M57 gnd + - V7 = vdc = Vcc/ D03AU458 Figure 4. +V CC Q Q INxA OUTxA OUTxB INxB Q3 Q4 GND D00AU34 Figure 5. High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +V CC Duty cycle=a DTout(A) Duty cycle=b DTin(A) INA M58 Q OUTA Iout=4A L7 µ Rload=8Ω L8 µ DTout(B) Iout=4A OUTB Q M4 DTin(B) INB M57 Q3 C9 470nF C7 470nF C70 470nF Q4 M3 Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU57 /4

7 3 TECHNICAL INFO: The STA50 is a dual channel H-Bridge that is able to deliver more than 0W per channel (@ THD=0%) of audio output power in high efficiency. The STA50 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface, integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protection circuitry. In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary Modulation operation. In Binary Mode operation, both Full Bridge and Half Bridge Modes are supported. The STA50 includes overcurrent and thermal protection as well as an under-voltage Lockout with automatic recovery. A thermal warning status is also provided. Figure. STA50 Block Diagram Full-Bridge DDX or Binary Modes INL[:] INR[:] VL TRI-STATE Logic I/F and Decode Left H-Bridge OUTPL OUTNL FAULT TWARN Protection Circuitry Regulators Right H-Bridge OUTPR OUTNR Figure 7. STA50 Block Diagram Binary Half-Bridge Mode INL[:] INR[:] VL TRI-STATE Logic I/F and Decode LeftA -Bridge LeftB -Bridge OUTPL OUTNL FAULT TWARN Protection Circuitry RightA -Bridge OUTPR Regulators RightB -Bridge OUTNR 3. Logic Interface and Decode: The STA50 power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the Vbias input must operate at the dame voltage as the DDX control logic supply. 3. Protection Circuitry: The STA50 includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin (pin.8) is activated low (open drain MOSFET) when the IC temperature exceeds 30C, in advance of the thermal shutdown protection. When a fault condition is detected, an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an opendrain MOSFET connected to the fault pin (pin.7) is switched on. 7/4

8 There are two possible modes subsequent to activating a fault: ) SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. ) AUTOMATIC recovery mode: This is shown in the Application Circuit of fig.. The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present, the circuit operation will continue repeating until the fault condition is removed. An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design as not to exceed the protection thesholds under normal operation. 3.3 Power Outputs: The STA50 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs. All duplicate power, ground and output pins must be connected for proper operation. The or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, V L, is settled. 3.4 Parallel Output / High Current Operation: When using DDX Mode output, the STA50 outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA50 can provide 80W into 8 ohm or up to W into 4ohm. This mode of operation is enabled with the CONFIG pin (pin.4) connected to VREG and the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB, OUTRA=OUTRB. 3.5 Additional Informations: Output Filter: A passive nd-order passive filter is used on the STA50 power outputs to reconstruct an analog Audio Signal. System performance can be significantly affected by the output filter design and choice of passive components. A filter design for ohm/8ohm loads is shown in the Typical Application circuit of fig.. Figure 9 shows a filter design suitable for 4ohm loads. Figure 0 shows a filter for ½ bridge mode, 4 ohm loads. Power Dissipation & Heat Sink requirements: The power dissipated within the device will depend primarily on the supply voltage, load impedance and output modulation level. The PowerSO3 package of the STA50 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. Careful consideration must be given to the overall thermal design. See figure 8 for power derating versus Slug temperature using different heatsinks and considering the Rth-jc =.5 C/W. 8/4

9 Figure 8. STA50 power derating curve Pdiss(W) Infinite -.5C/W 3-3 C/W 4-4 C/W Slug temperature C Figure 9. Typical Single BTL Configurationto obtain THD 0%, R L = 4Ω, V CC = 3V (note )) +3.3V TH_WAR 0K n INA INB X7R 0K X7R VL GND-Clean GND-Reg V DD V DD CONFIG TH_WAR FAULT TRI-STATE INA INB INA INB V CC SIGN 3 8 N.C. 7 9 OUTA OUTA OUTB 0 9 OUTB OUTA 4 8 OUTA 8 3 OUTB OUTB V CC A V CC B 9 30 V CC A V CC B GNDA GNDB 35 3 Ω /W 330pF X7R X7R 0µH 0µH. /W. /W FILM FILM 0µF 3V X7R 470nF FILM X7R 3V 3V 4Ω X7R V CC SIGN 3 GNDA Add. GNDSUB 5 GNDB D03AU54 Note:. "A PWM modulator as driver is needed. In particular, this result is performed using the STA30X+STA50X demo board". Peak Power for t sec 9/4

10 Figure 0. Typical Quad Half Bridge Configuration V CC P +V CC +3.3V R57 0K R59 0K INA INA VL CONFIG FAULT PROTECTIONS & LOGIC M3 M OUTPL OUTPL PGNDP V CC N R4 C4 330pF L µh C7 R5 C8 R R C3 8µF C9 4Ω C 0µF TH_WAR C58 TRI-STATE TH_WAR 8 M5 0 C5 OUTNL C L µh R3 C3 8µF INB INB V DD V DD REGULATORS M4 3 7 OUTNL PGNDN V CC P R4 C4 330pF C7 R5 C8 R4 C9 4Ω C58 C53 C0 INA V CC SIGN V CC SIGN INA GND-Reg M7 M OUTPR OUTPR PGNDP V CC N R43 C43 330pF L3 µh C73 R53 C83 R5 R C33 8µF C93 4Ω INB GND-Clean 9 INB 3 GNDSUB M M4 3 5 C5 OUTNR OUTNR PGNDN D03AU474 C R44 C44 330pF L4 µh C74 R54 C84 R7 R8 C34 8µF C94 4Ω For more information refer to the application notes AN45 and AN 0/4

11 The following measures are related to the application using STA308A driver Figure. THD+N vs Frequency Figure 4. THD+N vs Output Power T THD(%) Vcc=3V Rl=8ohm 5 Vcc=3V Rl=8ohm F=KHz % k k 5k 0k k Hz m 0m 500m Pout(W) Figure. Output Power vs Vsupply Table 0. THD+N vs Output PowerRevision Po(W) Rl=8ohm F=KHz THD=0% THD(%) Vcc=3V Rl=8ohm F=KHz THD=% Vsupply (V) m 0m 500m Pout(W) Figure 3. THD+N vs Output Power THD(%) Vcc=34V Rl=8ohm F=KHz m 0m 500m Pout(W) /4

12 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A A A A a b c D D D E E E E E e e G H h L N 0 (max) s 8 (max) () D and E do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.5mm (0.00 ) () No intrusion allowed inwards the leads. OUTLINE AND MECHANICAL DATA PowerSO3 (SLUG UP) C /4

13 Table. History Date Revision Description of Changes December 03 First Issue April 04 Inserted Technical Info and Graphics April 04 3 Small changes in pag 4 and 5 June 04 4 Note : See relevant Application Note AN994 3/4

14 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 04 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States 4/4

Figure 1. Package. Table 1. Order Codes V CC 1A C30 OUT1A OUT1A GND1A V CC1B C31 OUT1B OUT1B M4 13 GND1B 22 V SS REGULATORS 7 V CC2A C32 M17 OUT2A

Figure 1. Package. Table 1. Order Codes V CC 1A C30 OUT1A OUT1A GND1A V CC1B C31 OUT1B OUT1B M4 13 GND1B 22 V SS REGULATORS 7 V CC2A C32 M17 OUT2A 40V 3.5A QUAD POWER HALF BRIDGE 1 FEATURES MULTIPOWER BCD TECHNOLOGY MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 0mΩ R dson COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION