VND670SP DUAL HIGH SIDE SWITCH WITH DUAL POWER MOS GATE DRIVER (BRIDGE CONFIGURATION)

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1 VND670SP DUAL HIGH SIDE SWITCH WITH DUAL POWER MOS GATE DRIVER (BRIDGE CONFIGURATION) TYPE R DS(on) I OUT V DSS VND670SP 30 mω 5 A 40 V OUTPUT CURRENT:5A PER CHANNEL 5V LOGIC LEVEL COMPATIBLE INPUTS GATE DRIVE FOR TWO EXTERNAL POWER MOS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN OVERVOLTAGE CLAMP THERMAL SHUT DOWN CROSS-CONDUCTION PROTECTION CURRENT LIMITATION VERY LOW STAND-BY POWER CONSUMPTION OPERATION UP TO 0 KHz PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF V CC REVERSE BATTERY PROTECTION (*) DESCRIPTION The VND670SP is a monolithic device made using STMicroelectronics VIPower technology M0-3, intended for driving motors in full bridge BLOCK DIAGRAM 0 PowerSO-0 configuration. The device integrates two 30 mω Power MOSFET in high side configuration, and provides gate drive for two external Power MOSFET used as low side switches. and allow to select clockwise or counter clockwise drive or brake;, allow to disable one half bridge and feedback diagnostic. Built-in thermal shut-down, combined with a current limiter, protects the chip in overtemperature and short circuit conditions. Short to battery protects the external connected low-side Power MOSFET. V CC Undervolt. INTERNAL SUPPLY Short to battery LOGIC Short to battery Overtemp. A Overtemp. B Current Limiter B Current Limiter A GND (*) See note at page 5 January 2003 /4

2 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit V CC Supply voltage V I max Maximum output current (continuous) 5 A I max2 Maximum output current (250 ms pulse duration) 20 A I R Reverse output current (continuous) -5 A I IN Input current +/- 0 ma I EN Enable pin current +/- 0 ma I pw pin current +/- 0 ma I gs Output gate current +/- 20 ma V ESD Electrostatic discharge (R=.5kΩ, C=00pF) 2000 V T j Junction operating temperature -40 to 50 C T STG Storage temperature -55 to 50 C CURRENT AND VOLTAGE CONVENTIONS I CC V CC I INA I INB I ENA V CC I OUTA I OUTB IgsA V OUTA I ENB GND I gsb V gsa V gsb VOUTB I pw V INA V INB V ENA V ENB V pw I GND CONNECTION DIAGRAM (TOP VIEW) INPUT B INPUT A OUTPUT B GROUND OUTPUT A V CC 2/4

3 THERMAL DATA Symbol Parameter Value Unit R thj-case Thermal resistance junction-case (per channel) (MAX).4 C/W R thj-amb (*) Thermal resistance junction-ambient (MAX) 50 C/W (*) When mounted using the recommended pad size on FR-4 board (See AN55 Application Note). ELECTRICAL CHARACTERISTICS (V CC =9V up to 8V; -40 C<T j <50 C; unless otherwise specified) POWER Symbol Parameter Test Conditions Min Typ Max Unit V CC Operating supply voltage V R ON On state resistance I LOAD =2A 50 mω I LOAD =2A; Tj=25 o C mω I s Supply current ON state 5 mα OFF state 40 µa V gate Gate output voltage V V gs,cl Gate output clamp voltage I gs =- ma V SWITCHING (V CC =3V, R LOAD =.Ω) Symbol Parameter Test Conditions Min Typ Max Unit t D(on) Turn-on delay time µs t D(off) Turn-off delay time µs t r Output voltage rise time µs Input rise time < µs (see fig. ) t f Output voltage fall time µs (dv OUT /dt) on Turn-on voltage slope V/ms (dv OUT /dt) off Turn-off voltage slope V/ms t dong V gs Turn-on delay time µs C=4.7nF t rg V gs rise time µs Break to ground configuration t doffg V gs Turn-off delay time µs (see fig. 2) t fg V gs fall time µs t del External MOSFET turn-on dead time (see fig. 3) µs PROTECTION AND DIAGNOSTIC Symbol Parameter Test Conditions Min Typ Max Unit V USD Undervoltage shut-down 5.5 V V OV Overvoltage shut-down V I LIM Current limitation A T TSD Thermal shut-down temperature V IN = 3.25 V C V ocl Output turn-off clamp voltage I LOAD =2A, L=6mH V CC -55 V CC -4 V V sat External MOSFET saturation voltage detection threshold V 3/4

4 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min Typ Max Unit V pwl low level voltage.5 V I pwl pin current V pw =.5V µa V pwh high level voltage 3.25 V I pwh pin current V pw =3.25V 0 µa V pwhhyst hysteresis voltage 0.5 V V pwcl clamp voltage I pw = ma V CC +0.3 V CC +0.7 V CC +.0 V I pw = - ma V V pwtest Test mode pin voltage V I pwtest Test mode pin current V pwtest = -2.0 V µa LOGIC INPUT ( / ) Symbol Parameter Test Conditions Min Typ Max Unit V IL Input low level voltage.5 V I INL Input current V IN =.5 V µa V IH Input high level voltage 3.25 V I INH Input current V IN =3.25 V 0 µa V IHYST Input hysteresis voltage 0.5 V V ICL Input clamp voltage I IN =ma V I IN =-ma V ENABLE (LOGIC I/O PIN) Symbol Parameter Test Conditions Min Typ Max Unit V ENL Enable low level voltage Normal operation (DIAG X /EN X pin acts as an.5 V input pin) I ENL Enable pin current V EN =.5 V µa V ENH Enable high level voltage Normal operation (DIAG X /EN X pin acts as an 3.25 V input pin) I ENH Enable pin current V EN = 3.25 V 0 µa V EHYST Enable hysteresis voltage Normal operation (DIAG X /EN X pin acts as an input pin) 0.5 V V ENCL Enable clamp voltage I EN =ma V I EN =-ma V Fault operation V DIAG I EN =.6 ma Enable output low level (DIAG X /EN X pin acts as an voltage input pin) 0.4 V 4/4 2

5 WAVEFORMS AND TRUTH TABLE TRUTH TABLE IN NORMAL OPERATING CONDITIONS In normal operating conditions the DIAG X /EN X pin is considered as an input pin by the device. This pin must be externally pulled high. Comment H H L L Brake to V CC 0 H L L H Clockwise 0 L H H L Counter cw 0 0 L L H H Brake to GND X X 0 0 L L L L Stand by X 0 H L L L HS A only 0 X 0 L L H L MOS A only X 0 L H L L HS B only X 0 0 L L L H MOS B only pin usage: In all cases, a 0 on the pin will turn-off both and outputs. When rises back to, or turn on again depending on the input pin state. TYPICAL APPLICATION CIRCUIT FOR DC TO 0KHz OPERATION +5V R V CC +5V R K K VND670SP K GND R gnd (*) K UP K M DOWN External Power Mos A External Power Mos B (*) Reverse battery protection: - series relay in V CC line: R gnd =0 Ohms - series fuse in V CC line with antiparallel diode between ground and V CC : R gnd =0 Ohms. Layout hints: The connection between GND pin of the VN670SP and the Power MOSFET SOURCE connections should be kept short enough to ensure that the dynamic difference between these two points never exceed V for the bridge to operate properly. 5/4

6 TYPICAL APPLICATION CIRCUIT FOR A 20KHZ OPERATION +5V +5V R V CC R K VND670SP K K R gnd (*) K UP K M D DOWN D2 27Ω 27Ω External Power Mos A External Power Mos B (*) Reverse battery protection: - series relay in V CC line: R gnd =0 Ohms - series fuse in V CC line with antiparallel diode between ground and V CC : R gnd =0 Ohms. 6/4

7 WAVEFORMS AND TRUTH TABLE (CONTINUED) In case of a fault condition the DIAG X /EN X pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides; - short to battery condition on the output (saturation detection on the external connected Power MOSFET). Possible origins of fault conditions may be: is shorted to ground ---> overtemperature detection on high side A. is shorted to V CC ---> external Power MOSFET saturation detection (driven by ). When a fault condition is detected, the user can know which power element is in fault by monitoring the,, DIAG A / EN A and pins. In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (GATE X or OUT X ) again, the input signal must rise from low to high level. TRUTH TABLE IN FAULT CONDITIONS (detected on ) 0 OPEN H L L 0 0 OPEN OPEN L L 0 0 OPEN H L L OPEN OPEN L L X X 0 0 OPEN OPEN L L X 0 0 OPEN OPEN L L 0 X 0 0 OPEN OPEN L L X 0 OPEN H L L X 0 0 OPEN OPEN L L Fault Information Protection Action TEST MODE The pin allows to test the load connection between two half-bridges. In the test mode (V pwm =-2V) the external Power Mos gate drivers are disabled. The or inputs allow to turn-on the High Side A or B, respectively, in order to connect one side of the load at V CC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIAD X /EN X pin corresponding to the faulty output is pulled down. 7/4

8 ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R Test Level Test Level Test Level Test Level Test Levels 7637/ I II III IV Delays and Impedance Test Pulse -25V -50V -75V -00V 2ms, 0Ω 2 +25V +50V +75V +00V 0.2ms, 0Ω 3a -25V -50V -00V -50V 0.µs, 50Ω 3b +25V +50V +75V +00V 0.µs, 50Ω 4-4V -5V -6V -7V 00ms, 0.0Ω V +46.5V +66.5V +86.5V 400ms, 2Ω ISO T/R Test Levels Result Test Levels Result Test Levels Result Test Levels Result 7637/ I II III IV Test Pulse C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 8/4

9 Figure : Test conditions for High Side switching times measurement. V OUTA, B 80% 90% (dv OUT /dt) on (dv OUT /dt) off 0% t V INA, B t d(on) t r t d(off) t f t Figure 2: Test conditions for external Power MOSFET switching times measurement. V gsa, B 80% 90% 0% 20% t V pw t dong t rg t doffg t fg t Figure 3: Definition of the external Power MOSFET turn-on dead time t del V gsa t del 9/4

10 Waveforms NORMAL OPERATION ( =, =) NORMAL OPERATION ( =, =0 and =0, =) CURRENT LIMITATION/THERMAL SHUTDOWN or SHORTED TO GROUND I LIM I OUTA T TSD T j normal operation shorted to ground normal operation 0/4

11 Waveforms (Continued) shorted to V CC and undervoltage shutdown normal operation shorted to V CC normal operation undervoltage shutdown Load disconnection test ( =, =-2V) (test mode) load connected load disconnected load connected back /4

12 PowerSO-0 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A (*) A B B (*) C C (*) D D E E E2 (*) E E4 (*) e F F (*) H H (*) h L L (*) α 0º 8º 0º 8º α (*) 2º 8º 2º 8º (*) Muar only POA P03P B A B H E E2 E4 SEATING PLANE e 0.25 B DETAIL "A" A C D A h = D= = = SEATING PLANE F A A DETAIL "A" L α P095A 2/4

13 PowerSO-0 SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) C B CASABLANCA MUAR A A C All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.) Casablanca B Muar TAPE AND REEL SHIPMENT (suffix 3TR ) REEL DIMENSIONS Base Q.ty 600 Bulk Q.ty 600 A (max) 330 B (min).5 C (± 0.2) 3 F 20.2 G (+ 2 / -0) 24.4 N (min) 60 T (max) 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 48 rev. A, Feb. 986 Tape width W 24 Tape Hole Spacing P0 (± 0.) 4 Component Spacing P 24 Hole Diameter D (± 0./-0).5 Hole Diameter D (min).5 Hole Position F (± 0.05).5 Compartment Depth K (max) 6.5 Hole Spacing P (± 0.) 2 All dimensions are in mm. End Start Top cover tape No components 500mm min Components Empty components pockets saled with cover tape. No components 500mm min User direction of feed 3/4

14 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2002 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 4/4

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