Design Application Note -- AN-061 SGA-8343 GPS Application Circuits

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1 Design Application Note -- AN-61 Abstract Sirenza Microdevices SGA-8343 is a high performance SiGe amplifier designed for operation from DC to 6. This application note illustrates application circuits for GPS (Global Positioning System) frequency band (1575 MHz). The first application circuit is optimized for noise performance; the second one is optimized for input return loss. Introduction The application circuits were designed to achieve the optimum combination of NF, input return loss, and stability. All recommended components are standard values available from well-known manufacturers. Components specified in the bill of materials (BOM) have known parasitics which in some cases are critical to the circuit s performance. Deviating from the recommended BOM may result in a performance shift due to varying parasitics. Matching component placement is critical to each circuit s performance. Circuit Details SMDI will provide the detailed layout (AutoCAD format) to users wishing to use the exact same layout and PCB material shown in the following circuits. The circuits recommended within this application note were designed using the following PCB stack up: Material: GETEK TM ML C Core thickness:.31 Copper cladding: 1 oz. both sides Dielectric constant: 4.1 Dielectric loss tangent:.89 (@ 1 ) Customers not wishing to use the exact material and layouts shown in this application note can design their own PCB using the critical transmission line impedances and phase lengths shown in the BOMs and layouts. NOTE: Many of our sample evaluation boards may come with an additional substrate & copper layer for mechanical stability. It has been assumed that the backside layer has no effect on the RF performance or circuit design. Design Considerations and Trade-offs - Biasing Techniques All HBT amplifiers are subject to device current variation due to the decreasing nature of the internal V BE with increasing temperature. In the absence of an active bias circuit or resistive feedback, the decreasing V BE will result in increased base and collector currents. As the collector current continues to increase under constant V CE conditions, the device may eventually exceed its maximum dissipated power limit resulting in permanent device damage. The designs included in this application note contain passive bias circuits that stabilize the device current over temperature and desensitize the circuit to device process variation. The passive bias circuits used in these designs include a dropping resistor in the collector bias line and a voltage divider from the collector-to-base. Using this scheme, the amplifier can be biased from a single supply voltage. The collector dropping resistor is sized to drop >% V CE, depending on the desired V CE. The voltage divider from collector-to-base, in conjunction with the dropping resistor, will stabilize the device current over temperature. The effectiveness increases with increasing voltage drop in collector bias line. Configuring the voltage divider such that the shunt current is 5-1 times larger than the desired base current desensitizes the circuit to beta variation. These two feedback mechanisms are sufficient to insure consistent performance over temperature and device process variations. Note that the voltage drop is clearly dependent on the nominal collector current and can be adjusted to generate the desired V CE from a fixed supply rail. The user should test the circuit over the operational extremes to guarantee adequate performance. An active bias circuit can be implemented if the user does not wish to sacrifice the voltage required by the aforementioned passive circuit. There are various active bias schemes suitable for HBTs. The user should choose an active bias circuit that best meets his/her cost, complexity, and performance requirements. Other Application Circuits Available (see AN-44) MHz, single-ended with series feedback, optimized for NF and S11< MHz, single-ended, optimized for NF and S11< MHz, single-ended, optimized for NF and S11< -1. The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 3 Sirenza Microdevices, Inc. All worldwide rights reserved. 33 Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC 1 EAN-131 Rev A

2 Design Application Note -- AN-61 Vcc + V DROP - I SHUNT I B I c + V CE - Passive Bias Circuit Topology Vs 6 Q1a 1 R4 C4 R3 R 5 R5 R6 R1 3 4 Q1b C5 C3 C6 L L1 SGA-8343 Active Bias Circuit Topology 33 Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC EAN-131 Rev A

3 Optimal NF Application Circuit (V S =3.3V, V CE =.7V, I CQ =1mA) Design Application Note -- AN-61 Vs=+3.3V (1mA) GND 6Ω 1KΩ.KΩ.1uF.1uF.KΩ 1Ω 39nH 1.8nH.1uF 3.9nH 1.pF ECB B SOT FB C1, 5, 7 ROHM MCH185A15J 15 pf C ROHM MCH185A1RC 1.pF C3, 4, 6 Samsung CL1B14KONC.1 uf L1 TOKO LL168-FS39NJ 39 nh L TOKO LL168-FS1N8S 1.8 nh L3 TOKO LL168-FS3N9S 3.9 nh R1, 3 ROHM MCR3J.K Ω R ROHM MCR3J1 1.K Ω R4 ROHM MCR3J6 6 Ω R5 ROHM MCR3J1 1 Ω Optimal NF Schematic Z1 non-critical 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z6 non-critical 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 6 Ω R R3 R4 C4 Vs=3.3V C1 Z1 C3 L1 Z C L Z3 R1 R5 C5 Z9 C6 L3 C7 Z4 Z5 Z6 SGA-8343 pin 4 - Pad edge to via center Z8 Z7 33 Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC 3 EAN-131 Rev A

4 Design Application Note -- AN-61 Typical Performance: Optimal NF Application Circuit (V S =3.3V, I CQ=1mA, 5C) Gain vs. Frequency NF vs. Frequency m P1 vs. Frequency OIP3 vs. Frequency m 6 4 m 6 4 S11 vs. Frequency S vs. Frequency Freq () P1 (m) OIP3 (m) Gain () S11 () S () NF () Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC 4 EAN-131 Rev A

5 Optimal S11 Application Circuit (V S =3.3V, V CE =.7V, I CQ =1mA) Design Application Note -- AN-61 Vs=+3.3V (1mA) GND 6Ω 1KΩ.KΩ.1uF.1uF 1Ω 39nH 1.3KΩ.1uF 1.8nH.pF 3.9nH ECB B SOT FB C1, 5, 7 ROHM MCH185A15J 15 pf C ROHM MCH185ARC. pf C3, 4, 6 Samsung CL1B14KONC.1uF L1 TOKO LL168-FS39NJ 39 nh L TOKO LL168-FS1N8S 1.8 nh L3 TOKO LL168-FS3N9S 3.9 nh R1 ROHM MCR3J13 1.3K Ω R ROHM MCR3J1 1.K Ω R3 ROHM MCR3J.K Ω R4 ROHM MCR3J6 6 Ω R5 ROHM MCR3J1 1 Ω Optimal S11 Schematic Z1 non-critical 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z7 non-critical 5 Ω Z MHz 5 Ω Z MHz 5 Ω Z MHz 6 Ω R R3 R4 C4 Vs=3.3V C1 Z1 Z C L Z3 C3 L1 Z4 R1 pin - Pad edge to grounding strip Z1 Z5 SGA-8343 C6 Z6 R5 C5 L3 Z7 C7 pin 4 - Pad edge to via center Z9 Z8 33 Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC 5 EAN-131 Rev A

6 Design Application Note -- AN-61 Typical Performance: Optimal S11 Application Circuit (V S =3.3V, I CQ =1mA, 5C) Gain vs. Frequency NF vs. Frequency P1 vs. Frequency 3 OIP3 vs. Frequency 8 8 m 6 4 m 6 4 S11 vs. Frequency S vs. Frequency Freq () P1 (m) OIP3 (m) Gain () S11 () S () NF () Technology Court, Broomfield, CO 81 Phone: (8) SMI-MMIC 6 EAN-131 Rev A