ECE, Box 7914, NCSU, Raleigh NC ABSTRACT 1. INTRODUCTION

Transcription

1 header for SPIE use Molectronics: A circuit design perspective David P. Nackashi a, Paul D. Franzon* a a Dept. of Electrical and Computer Engineering, North Carolina State University ECE, Box 7914, NCSU, Raleigh NC ABSTRACT Recently, several mechanisms have been proposed as a basis for designing molecular electronic logic switching elements. Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to silicon devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A series of logic gates and a memory element are simulated based on the voltagecontrolled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). HSPICE simulation results are used to illustrate the performance of these devices and to quantify additional component and interconnect requirements. Finally, future system design approaches using molecular components are discussed. Keywords: Computer architecture, molecular circuit design, molecular electronics, negative differential resistance, resonant tunneling diode 1. INTRODUCTION Molecular electronic devices have the potential to offer many advantages over their silicon counterparts, including integration into much smaller areas and faster response times. 1 Although these advantages are substantial when comparing molecular devices directly with silicon devices, other physical factors such as interconnect performance must also be quantified in order to compare a molecular electronic system s response with that of a silicon technology. Although it is clear that several types of two terminal non-linear molecular elements can be chemically synthesized today, 2,3,4 it is unclear as to whether they can be integrated into larger circuits based upon current architectures. Any logical operation can be implemented from only NAND, and NOR logical elements. Layout tools and design libraries allow circuit designers to decompose complex functions into these basic logical elements, then systematically instantiate and interconnect these elements many times over to produce the original function on a set of masks. Lithographic techniques used to create the masks and pattern the films on a wafer allow for as much order or disorder within the positioning of these logical elements as the designer requires. It is unclear as to whether chemical synthesis will allow IC designers to assemble logical elements with as much freedom as they are permitted today. In systems constructed purely of molecular elements, the ability to perform logical operations at a system level is important if integration with standard digital design practices is desired. The necessity of these operations to be assembled from the most simple NAND and NOR logical elements has not been proven. A majority of molecular electronic devices being synthesized and characterized today contain two terminals and function predominately as diodes. Molecular electronic devices displaying both rectifying diode and resonant tunneling diode (RTD) characteristics have been demonstrated. 2,3,4 Diode-based logic families have been well understood for many years, and a large number of logic gates and digital systems based on diodes have been designed and fabricated since their conception. Logic gates such as the AND and OR functions have been constructed using only rectifying diodes connected to the input terminals and a resistor connected to either a power rail or ground. 5 RTDs have proven useful in the design and fabrication of logic families, memories, oscillators and other devices. 6,7,11,12 Although the usefulness and scalability of these diodes fabricated in current CMOS technology is proven in many applications, the scalability of molecular devices exhibiting similar current-voltage responses is not well understood. The purpose of this work is to explore the feasibility of constructing logic gates, memories and more advanced systems based upon current circuit architectures using a molecular diode. In addition, the impact of parasitic effects such as device-to-device capacitance and how they might affect the performance of these systems is investigated. Finally, future system design approaches with other molecular devices are explored. * Correspondence: paulf@eos.ncsu.edu; WWW: Telephone: (919) ; Fax: (919)

2 2. CIRCUIT ELEMENTS AND SYSTEMS The focus of this work is based upon the two-terminal current-carrying performance of a Tour-Reed molecular diode with a current-voltage response similar to that of the RTD. 2 The primary characteristic of the RTD current-voltage (I-V) response is the appearance of a region known as negative differential resistance (NDR). This area is observed as a segment on the I-V curve where the slope is negative. The usefulness of these devices has been well known for almost four decades in applications such as oscillators, memories and digital logic elements. 7,11,12 When a device exhibiting NDR is placed in series with a resistor and voltage source, a bistable latch can be created. The resistor must be sized such that its value is greater than the average NDR of the device. In this case, the load line will intersect the I-V curve of the NDR device in three locations as shown in Figure 1. The intersection with the NDR region is unstable, leaving only two stable operating points. Although loading with a resistor is the simplest method for creating a bistable latch, previous research has shown that an RTD can be loaded with a depletion-mode FET or another RTD to form bistable latches. 8 Area and performance improvements have been demonstrated through the integration of these latches into CMOS technologies. Current-voltage characteristics of the Tour-Reed molecular diode were provided by Jia Chen and Mark Reed of Yale University. As shown in Figure 1, the data points of the molecular NDR device are plotted and superimposed with a potential load line illustrating the two stable points of operation. The molecular device has a peak current of approximately 1nA, a valley current of approximately 1pA and a peak-to-valley current ratio of 1030:1. 2 Figure 1. I-V characteristic of the Tour-Reed molecular NDR device and load line with schematic The peak current for this device occurs at 2.12V as measured by Chen and Reed. In the region from 0 to 1.5V, the device conducts only the valley current, or 1pA. Although the magnitude and position of the current peak differs from device to device 2, these differences do not result in large variations in the required loading resistors. The I-V characteristic taken from this particular device was therefore used to construct an HSPICE model for circuit simulations. Variations in peak current position from device to device could, however, have a significant impact on the assembled circuits. The tolerence of each circuit presented with respect to peak shift is addressed.

3 2.1 A Bistable Latch In simulation, a resistor was chosen to load the NDR device and form a bistable latch for three reasons. First, the I-V characteristics and area of the molecular devices do not lend themselves to simple integration with FETs. A peak current of 1nA is several orders of magnitude lower than what would be required to intersect the load line of a depletion-mode FET. In addition, the feasibility of an all-molecular device solution is of principal interest. Second, loading the NDR device with another molecular NDR device exhibiting a similar I-V characteristic would not necessarily result in two distinct stable operating points. If two of these devices were placed in series with a bias voltage as previously shown 8, the resulting load lines would intersect at a large number of points. This is due to the long, flat conducting regions of the I-V curve from 0V to 1.5V and above 2.4V. A trait common to silicon RTDs that makes this type of loading possible is the continual increase in conductivity at voltages above the NDR region of the device. Finally, it has been demonstrated that molecules exhibiting a large linear resistance can be synthesized and possibly integrated with the molecular NDRs. 9,10 As previously mentioned, the value of the load resistor will determine the slope of the load line. This will impact the location of the two stable points of intersection with the molecular NDR, determining the high and low voltages for each of the two states of the bistable latch. In the high voltage state, the molecular device will operate in the low conduction region. In the low voltage state, the molecular device will operate in the high conduction region. The x-intercept of each load line shown in Figure 2 is set by the voltage source, Vdd. The y-intercept of the load line is set by the voltage source divided by the load resistor, or Vdd/R. In Figure 2, the impact of several load resistance values on the bistable points is illustrated. For these three load lines, the voltage source (Vdd) and resistances (R) are 2.41V and 373MΩ, 575MΩ and 1.31GΩ respectively. Note the values of these load resistors are quite large. If the load resistor is much below 373MΩ, there is a risk the latch will not set in the low voltage state. Figure 2. The effect of different load resistors values on the two stable point of operation for the latch As the two stable intersections are moved further apart, the loading resistance becomes greater than 1GΩ. This illustrates a trade-off when determining the appropriate value for the load resistor. If too small, the latch could only have one stable state if the device current peak shifts slightly to the left. In addition, a small resistor will result in minimal separation between the high and low voltage states in the latch. In order to increase the separation between these two states, a much larger resistor is

4 required, one that might not be chemically synthesizeable. Because of the shape of this I-V curve in the region just before the NDR, the cost of increasing the separation between the two operating voltages of the latch becomes quite high in terms of resistances required to load. If these molecular devices exhibiting NDR are to be assembled into bistable latches with consistent voltage states across an entire chip, molecular resistive elements on the order of several hundred megaohms will need to be synthesized and integrated into the circuits. In addition, variances in current peak magnitude and position should be kept to a minimum in order to ensure that two stable points of operation occur, and that those two points are consistent from latch to latch. Avant! STAR-HSPICE 98.2 was used simulate the performance of the latch circuit shown in Figure 3. A model was created using a voltage-controlled current source, defined as a G element in HSPICE. The voltage and current data points supplied by Chen and Reed were captured within the piecewise linear (PWL) function available in the G element of HSPICE. Because the current-voltage data was collected using DC no-load conditions, this model does not take into account AC responses of the molecular devices. The time constants associated with each transition will be captured and modeled in future work. Figure 3. Latch simulation when loaded with a 373MΩ resistor and a 2.41V source The schematic in Figure 3 displays the input and output terminals on the latch. Figure 4 illustrates the input and output waveforms of a latch loaded in series with a 373MΩ resistor and a 2.41V source. Toggling between the two stable points is achieved by pulsing the voltage source, Vbias, above and below the 2.41V steady state value. As shown in Figure 4, this latch results in two stable points of operation separated by 0.32V. Note that transitions from the low voltage state to the high voltage state require a smaller Vbias pulse than from high to low. This is because the low voltage stable point of operation is closer to the NDR region than the high voltage stable point. With larger resistor values, the two stable points could be placed equidistant from the NDR segment, resulting in the same Vbias pulse magnitudes required to transition between the states.

5 Figure 4. Waveforms for a latch loaded with a 373Ω resistor and a 2.41V source 2.2 A Latched NAND and NOR gate The bistable latch can be used as a basis for both a NAND and a NOR gate. Inspired from a design presented by Chow in 1964, 7 two bistable latches can be chained together by a bridge resistor to form either logic element. Shown in Figure 5 are the schematics for both gates, which perform current-mode logic. A current of 500pA at either the input or output terminal is defined as logic 1, and a current of 0pA is defined as logic 0. The gates are synchronously latched; therefore the inputs are evaluated only during a clock pulse, shown in the waveforms in Figure 6. Operation of the NAND gate begins with a reset pulse, which places both molecular diodes in the low voltage/high current state and forces a 500pA logic 1 current to the output. If both inputs are supplied with a 500pA current at the time of a clock pulse, the output will transition to 0pA. If neither input or only one input is supplied with a 500pA current at the time of a clock pulse, the output will remain at 500pA with little fluctuation. The design is based upon a chain of two bistable latches, each loaded with a voltage source and a resistor or series of resistors. The resistors placed in series with the two inputs, INA and INB, are used in simulation to model the interconnect resistances. Before the initial reset pulse, both diodes are in a low current/high voltage state. The resistors are balanced such that no voltage difference exists across the bridge resistor to prevent the flow of current from one diode to the other. After the reset pulse is applied, both diodes transition to a high current/low voltage state. At this point, a small voltage difference exists across the bridge resistor. As logic 1 is applied to both inputs of the NAND gate, the input currents increase. As these currents increase, the voltage across the bridge resistor increases adding more current to the second NDR stage. The resistors are sized such that when the input threshold current is reached, it results in a bridge current that forces a transition of the second diode to a low current/high voltage state. Once both diodes have changed states, the voltage difference across the bridge resistor returns to 0V; therefore no current flows in either direction.

6 Figure 5. Schematic of NAND (left) and NOR (right) logic gates Although the implementation of both gates could potentially be realized with molecular elements, the complexity of these gates is high. Both the NAND and the NOR implementations described above require a minimum of four resistors and two diodes assembled in a highly irregular pattern. These gates must then be assembled into more complex, irregular structures to create high-level logical operations. Sizing of the resistors is important for each gate to function identically; therefore the molecular resistors must be synthesized with a high degree of precision. As previously stated for the bistable latch, variances in each molecular diode must be kept to a minimum. RESET RESET IN A IN A IN B IN B OUT OUT Figure 6. Waveforms illustrating the operation of NAND (left) and NOR (right) gates

7 2.3 Memories An advantage of memory elements is their regular structure. Inspired from Chow 7 and Chang, 11 a simple 4x4 memory array was created based upon the function of the bistable latch previously described. Shown in Figure 7 is the schematic for this memory array. Each memory cell is created from two resistive elements, the Tour-Reed molecular diode with NDR and two capacitive elements. The resistor values are all 373MΩ and the capacitors all 1pF. A logic 0 is stored in the memory cell as a low voltage/high current state, and a logic 1 is stored as a high voltage/low current state. Data to written into the memory is placed on the horizontal write lines W0 and W1. Data to be read is taken from the lower read lines RD0 and RD1. Read/Write instructions for each of the words are applied on the RW lines. The capacitors allow voltage coupling from the write and read lines into the bistable latch without adding an additional load. In this way, memory cells may be added without affecting the bias points for every other memory cell in the array. To reset the memory, a reset signal is applied by lowering the RW line to 2.0V. A write signal is applied by raising the RW line to 2.6V. A reset will place all the bistable latches that make up a given word into the low voltage/high current state. As shown in Figure 8, an input voltage placed on the write line of a particular bit at the time of a write pulse will result in the bistable latch transitioning into the high voltage state. Figure 7. Schematic of a 4x4 memory array Although memory arrays based upon the bistable latches described above still require a highly resistive element for loading, the overall structure of these memories is far more ordered than logic circuits based on discrete NAND and NOR functions. If molecular memories can be chemically synthesized, an option exists to realize logical functions within these memories by implementing them in lookup tables. Architectures based upon memories have been presented in the past, and the potential density advantages molecular devices offer could make extremely large-scale implementations of entire systems within memory possible.

8 RW0 W0 W1 Bit 0 Bit 1 Figure 8. Read and Write operations of the 4x4 memory array 3. FUTURE SYSTEM APPROACHES The gates and memories described above rely on the availability of a guided molecular synthesis process to realize discrete circuits from diodes, resistors and capacitors. A large number of components such as resistors, capacitors and two-terminal non-linear devices must be synthesized with a high degree of precision. These components must then be assembled into regular structures with varying degrees of complexity. As evident through the simulations, construction of logical elements from molecular two-terminal devices presents a large number of design and fabrication challenges. Other architectures, which implement logical functions without the need for precise molecular devices and complex synthesis techniques, would lend themselves to molecular electronic design. An architecture that could benefit from the randomness associated with device variations and pseudo-random interconnect would be beneficial. Such architectures are the subject of future investigation. 4. CONCLUSIONS In conclusion, the feasibility of integrating molecular diodes into current circuit architectures has been explored. A series of logic gates and a 4x4 memory array were simulated based on the voltage-controlled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). Although functionally the gates required to implement any logical expression were generated, their complexity may make realization of these circuits through molecular devices difficult. A 4x4 memory was designed and simulated using a bistable latch. Although the regularity of these elements might make memories better targets for chemical synthesis, the requirement for consistent, precise molecular components will also prove challenging. Architectures that are more tolerant of device interconnect and variation could lead to more robust circuit architectures.

9 ACKNOWLEDGEMENTS The authors have benefited from many useful discussions with Prof. James Tour, Prof. Mark Reed, their colleagues and students, Stephen Mick, John Damiano and John Wilson. Special thanks to Prof. John Reif of Duke University, Dept. of Computer Science. This work was funded under the ONR/DARPA grant award number N Infrastructure and support was provided by the NSF under grant number EIA REFERENCES 1. J. Tour, M. Kozaki, J. M. Seminario, Molecular Scale Electronics: A Synthetic/Computational Approach to Digital Computing, J. Am. Chem. Soc. 120, pp , J. Chen, M. A. Reed, A. M. Rawlett, J. M. Tour, Large On-Off Ratios and Negative Differential Resistance in a Molecular Electronic Device, Science 286, pp , R. M. Metzger et al., Unimolecular electrical rectification in hexadecylquinolinium tricyanoquinodimethanide, J. Am. Chem. Soc. 119, pp , C. Zhou, M. R. Deshpande, M. A. Reed, L. Jones II, J. M. Tour, Nanoscale metal/self-assembled monolayer/metal heterostructures, Appl. Phys. Lett. 71, pp , Wakerly, Digital Design Principles and Practices, pp , Prentice-Hall Inc., New Jersey, J. L. Huber et al., An RTD/Transistor Switching Block and Its Possible Application in Binary and Ternary Adders, IEEE Trans. Electron. Devices 44, pp , W. F. Chow, Principles of Tunnel Diode Circuits, Chapters 8 and 11, John Wiley & Sons Inc., New York, R. H. Matthews et al., A New RTD-FET Logic Family, Proc. IEEE 87, pp , P. S. Weiss et al., Probing electronic properties of conjugated and saturated molecules in self-assembled monolayers, Ann. NY Acad. Sci. 852, pp , J. C. Ellenbogen, J. C. Love, Architectures for Molecular Electronic Computers: 1. Logic Structures and an Adder Designed from Molecular Electronic Diodes, Proc. IEEE 88, pp , Kern K. N. Chang, Parametric and Tunnel Diodes, Chapters 11 and 12, Prentice-Hall Inc., New Jersey, J. M. Carroll, Tunnel-Diode and Semiconductor Circuit, Chapters 5-7, McGraw-Hill Inc., New York, 1963.