Implementation of User Defined Models in a Real- Time Cyber Physical Test-Bed

Transcription

1 Implementation of User Defined Models in a Real- Time Cyber Physical Test-Bed Amarsagar Reddy Ramapuram Matavalam Department of Electrical & Computer Engineering Iowa State University, Ames, IA, amar@iastate.edu Venkataramana Ajjarapu Department of Electrical & Computer Engineering Iowa State University, Ames, IA, vajjarapu@iastate.edu Abstract Online tools that can assess the state of the power system have been recommended in order to reduce the occurrences of large scale blackouts. Testing these novel methods on a real system is not recommended as the reliability of the system is at stake. Instead, a better way to judge the performance of the algorithm is to test it on a Cyber-Physical Real-Time Test-Bed. This paper describes the necessary components in a Real-Time Test-Bed and explains the different kinds of simulations possible. Next, the application of characterizing delayed voltage recovery is taken as an example to demonstrate the thought process on how to implement a Real-Time algorithm. The proposed algorithm can quantify the delayed voltage recovery at a load bus in real time based on voltage measurements from PMU s. This approach uses the idea of utilizing the Kullback-Leibler Divergence between the Probability Distributions of the delayed voltage response and the reference waveform as a way to quantify it. An implementation of the method in a real time cyberphysical test bed, using User-Defined models created in Modelica is described. Keywords Delayed Voltage Recovery, Phasor Measurement Units, Voltage Stability, Real Time Test Bed, Opal-RT, Modelica I. INTRODUCTION One of the main reasons for the major blackouts worldwide, including the one in North America in 2003 and in India in 2012 is the lack of visibility of the operator into the system. Blackout analysis reports always recommend the evaluation and adoption of better real-time tools for operators and reliability coordinators [1]. In order to support the development of new tools and reduce the occurrence of large scale blackouts, the energy independence and security act of 2007 has included as one of its main provisions the development of the smart grid initiative to support the modernization of the electricity transmission and distribution systems in North America [2]. This has led to the deployment and integration of renewable resources and supports increased use of digital information and technology to improve reliability, security, and efficiency of the grid. However, while developing real time tools to address aforementioned issues to the bulk power system has been an important issue for power system analysis and control, actually understanding the new tools and testing them rigorously has been a problem in this area of study. It is necessary to take advantage of the state-of-the-art techniques from fields such as dynamical systems but the industry do not want to take a chance of implementing these novel schemes on their systems. This is logical as there can be no chance of mis-operation of the new method. In order to test novel schemes that use new devices (PMUs, etc.), communicating using different communication channels (fiber optics, cloud, etc.) and triggering novel controls (demand response, etc.), there is a need to develop a Real-Time Cyber Physical Test-Bed [3]. The Test-Bed will enable us to test various configurations of an idea without changing much of the infrastructure and will allow the industry to view the method in action on a reasonable sized test-system. These tests can help in determining the bottlenecks in the proposed methodology and provide the industry with confidence to deploy novel methodologies at their sites. Hence, implementing a realistic Test-Bed will be of immense use to demonstrate the feasibility of a proposed algorithm. An important application of PMU s is to use their measurements to determine the voltage stability of the region being monitored. This is still an untested application and is ideal for implementation in a Real-Time Test-Bed. The rest of the paper is organized as follows: Section II describes the Cyber-Physical Real-Time Test-Bed at Iowa State University (ISU) in detail, Section III describes the voltage stability phenomenon of interest, Section IV describes the proposed real-time algorithm to detect the phenomenon along with simulation results in PSSE (a Phasor based power system solver), Section V describes the construction of models for simulating the phenomenon of interest in the Test-Bed and presents preliminary results, Section VI details the future work necessary for making the idea implementable and testable. II. CYBER-PHYSICAL TEST-BED AT ISU The Real-Time Cyber-Physical Test-Bed at ISU is used to simulate the power system in real-time along with the actual hardware used in the industry (PMU s, relays, etc.) [4*]. When using a real-time power system simulator, it is always important to keep the phenomenon of interest in mind. These test-beds provide quite a bit of flexibility to implement a system and it is easy to get consumed by the details while trying to simulate a system. This is because of the fact that the largest system that can be simulated in hardware is limited due to the real-time nature of the simulation. In contrast, a conventional time domain simulation program running on a workstation does not have this limitation. For example, if the phenomenon of interest has a time scale of hundreds of milliseconds (voltage stability) to seconds, then there is no need for EMTP scale simulations.

2 These phenomena can be captured reasonably well with phasor based simulations and this enables us to simulate larger systems as the time step can be increased to tens of milliseconds (ms). On the other hand, if the phenomenon of interest is in timescales less than 1 millisecond (analyzing harmonics due to power converters, etc.), then there is a need for EMTP simulations. This will limit the number of nodes in the system as the time step needs to be in tens of microseconds The main components of the Cyber Physical Test-Bed are the following 1. Real time Power System Simulator 2. Phasor Measurement Units (PMU s) with GPS 3. Network Simulator 4. Phasor Data Concentrator to aggregate the data 5. Historian database to store the data 6. Analytics Program/EMS (Matlab, Python, etc) A schematic displaying the interfaces between the various components is shown in the Fig. 1. A brief description of the two power system simulators in the test bed is given below 1. Real Time Digital Simulator (RTDS): This simulator uses an Electro Magnetic Transient Program (EMTP) algorithm with short time steps (50 micro sec) to simulate the power system, making it closer to the field than phasor based programs like PSSE or PSLF. It has Analog and Digital cards that output the actual signal at various nodes in the simulation model and allow hardware to be connected. It can also process digital packets of data as input to trip or close lines in the model while running in real-time. 2. Opal-RT Simulator: This is another real time simulator for power systems. The specialty of this simulator is that we can simulate systems either in EMTP representation, with short time steps (50 µs) and in Phasor representation, with coarse time steps (10 ms). This feature allows us to simulate comparatively large systems (1000 bus systems) in real time using the Phasor representation. Opal-RT also has Analog and Digital cards that output the signal at various nodes in the simulation and allow hardware to be connected. 3. Phasor Measurement Units (PMU s) with GPS: 3 Schweitzer Relays with PMU capability (SEL-421) Fig. 1. Schematic of the Real-Time Cyber Physical Test-Bed are present in the lab and are interfaced to the Real- Time simulators using the low-level interface detailed in [10]. The Real-Time simulators also have the provision for directly streaming out simulated PMU data from a few nodes in the power system onto the network (called as virtual PMUs). This is convenient as we want to simulate systems with large nodes and it is unrealistic to have all the data from physical PMUs. A GPS is present to give the clock signal to the Physical and Virtual PMUs. 4. Network Simulator: One of the main issues that occur while dealing with PMU s in the field is the delay between the PMU and the control center. The communication infrastructure can cause data packets to be received out-of-order or a few of them to be dropped as well. A network simulator is necessary to simulate this behavior of the actual system and we use open source simulator (NS-3) in the setup [5]. 5. Phasor Data Concentrator (PDC) & Historian: A Phasor Data Concentrator is necessary to time align the various samples from different PMU s and to put the data packets in order. Furthermore, we need to store the data that is being streamed from the PMU s in a reliable manner. The usual standard is to store the data in a Historian database and this is programmed right in the PDC. Simple filtering schemes can also be implemented right at the PDC. The open source program OpenPDC is used the setup. 6. Analytics Program/ EMS: The final component in the Test-Bed and also the one with which the user can understand and view the results in real time. Presently, we have programmed and interface between PDC and Matlab to analyze the data and display it as plots in a Matlab window. We are in the process of acquiring a commercial EMS to interface to the PDC. In order to make sure that the entire setup works as expected and to validate the results from the test-bed, the WECC 9 Bus system is simulated and the voltage waveform corresponding to the fault at Bus 5 for 0.05 sec (3 cycles) are compared between PSSE, RTDS, PMU and Matlab and shown below in Fig. 2.

3 (a) V (b) stalling. They continue to demand high reactive power even after the fault is cleared, leading to a delayed increase in the voltage. Finally, a few of the induction motors trip due to their thermal protection settings and this helps in recovering the bus voltage and eventually, the system voltage. Depending on the system parameters and trip settings of the motors, the sustained low voltages in the system can lead to cascading events towards a blackout. A typical delayed voltage response after a fault along with the various features is shown in Fig. 3 [7]. (c) Fig. 2. Comparison between the voltage at Bus 5 in (a) PSSE, (b) RTDS, (c) PMU and (d) Matlab. It can be observed that the all the voltage waveforms agree very well with one another, confirming that all the components in the setup are properly configured. The difference between the RTDS and the PMU voltage is that it does not go to zero during the fault and also has a voltage spike when the fault is cleared. This is due to the analog electronics present in the PMU that do not allow sudden changes in the voltage input to the internal Digital to Analog converter. Another difference is that the sharp voltage spikes present in the PMU data after the fault is cleared are reduced in the Matlab data. This is due to the filtering done in the PDC to filter out high frequency noise. Thus, the setup seems to perform as expected The studies that have been done using this test bed include testing vulnerabilities of AGC Control [6] & testing Lyapunov Exponent Calculation [4]. We are interested in the monitoring and control of Fault Induced Delayed Voltage Recovery (FIDVR) Phenomenon. More information about this phenomenon and our proposed method to monitor it is detailed in the next section. III. FAULT INDUCED DELAYED VOLTAGE RECOVERY Fault Induced Delayed Voltage Recovery (FIDVR) is the phenomena where the recovery of the voltage after a disturbance is delayed by a few seconds and results in sustained low voltages for several seconds. This is an increasing concern for utilities because of the increasing penetration of induction motor (IM) and electronically controlled loads. FIDVR is caused by stalling of single phase motors, primarily residential air-conditioners (particularly highefficiency ACs) during transmission level faults. Single phase AC motors can stall for normally cleared 3-phase faults and they lack the under voltage relay (UVR) that is required for large induction motors. The absence of UVR causes the motors to remain connected to the grid even at low voltage and demand a large amount of reactive power from the grid due to (d) Fig. 3. Delayed voltage recovery waveform at a bus In order to simulate the FIDVR phenomenon in a time domain power system simulation, the WECC Model Validation Working Group has been releasing several models that aggregate the effect of IM in the distribution feeders on the transmission side. Their most recent model, called the Composite Load Model, is shown in Fig. 4 [8]. Fig. 4. WECC model of the Composite Load Model that emulates FIDVR Phenomenon in a time domain phasor simulator The composite load model is an extremely complicated load model with around 130 parameters to specify its behavior. The main components in the model are the three 3-Phase IM and the 1-Phase AC Motor. Increasing the percentage of load represented by the IM will lead to severe FIDVR phenomena. Several FIDVR events have been observed in the US utilities, especially during the summer peak operation. An event in Southern California Edison (SCE) is shown below in Fig. 5 [9]. System voltages on the transmission side recovered to 0.95 p.u. within 25 seconds of fault clearing but then overshot due to the excess load of approximately 3500 MW in Southern California Edison area being tripped in the distribution side.

4 Probability Density Functions (PDFs) derived from the delayed voltage response were used to quantify FIDVR. The PDF of the delayed voltage response is compared to a reference PDF using the idea of statistical-distance between two PDFs. The Kullback-Leibler (KL) Divergence between two PDFs is used as the statistical distance due to its properties and has been defined so that a positive distance implies a violation of the FIDVR criteria. The steps involved in the quantification of FIDVR are summarized below Fig. 5. PMU recording of FIDVR event in SCE for a 500kV bus To characterize the performance of the voltage response, WECC has provided guidelines for the voltage performance after a fault. The guidelines for an 1 contingency are [7] 1. The voltage should not exceed 25% at load buses and 30% at non-load buses from the nominal voltage. 2. The voltage should not deviate more than 20% from the nominal voltage for more than 20 cycles at load buses. This criterion is a pointwise condition on the voltage waveform and it can be seen that the voltage response in Fig. 3 violates the WECC criteria. It is usually represented by utilities using a box criterion which provides the allowable region for the voltage at a given time. The box criterion provides a voltage recovery envelope above which the voltage waveform should lie [10*]. Figure 6 shows the graphical representation of the WECC voltage performance represented by a box criterion. 1. Observe voltage response from fault clearing instant (t = 1.1s) to the final observation time (t = 5s) in PSSE/PSLF. 2. Partition the voltage axis into N subintervals and count time spent by voltage response in each subinterval and divide by total time. This is the PDF of voltage response. 3. Compare the PDF of voltage with the Reference PDF using the KL Divergence metric (also called KL-index) using the formula ln, Where is the value of the voltage response PDF in interval and, is the value of the Reference PDF in interval. A pictorial representation of the PDF s is shown in Fig. 7 [11]. V* V3 V2 V1 0 Tcl T1 T2 Tf Fig. 6. WECC voltage performance represented by a box criterion These criteria are used by the utilities to plan and operate the amount and location of reactive support. The box criteria representation is a more adaptable version of the WECC criteria and the values of,,,, & can be configured by the planner and operator depending on the system. The WECC guidelines are based on experience and heuristics and are conservative and so using the WECC criteria for a system can lead to over designing of reactive resources during planning or excess control during operation. Furthermore, these guidelines provide only pass/fail criteria without actually providing any quantification of the phenomenon. A systematic method to quantify FIDVR will be useful for both planning and in control for real time operations. IV. QUANTIFYING FIDVR & MONITORING IN REAL TIME A simplistic method to quantify FIDVR would be using the difference between the delayed voltage response and the box criteria. A better quantification was done in [11], in which the Fig. 7. The Voltage time series and the PDF for the voltage series in along with a voltage reference PDF. This particular PDF is for the time after the fault (1.1 sec) to the end (5 sec) The methodology processes a time series of voltage responses for 5 seconds and outputs a single number for each time series that indicates the amount of FIDVR present. It was shown that a KL-index greater than 5 is an indication of severe FIDVR. This quantification enabled the effective planning of reactive reserves in the IEEE 162 Bus system under various contingencies and scenarios to prevent FIDVR [11]. However, In order to monitor the FIDVR phenomenon in real time, waiting for 5 seconds is not realistic. Hence, we convert the above algorithm to process a moving window of measurements as the input and calculate the KL divergence in that specific time-window. The reference PDF is no longer fixed but varies based on the time-window. A virtual voltage reference is generated at the PMU/PDC and the corresponding PDF of the reference in the time-window is used to calculate the KL-index. The virtual reference can be seen as a continuous approximation of the WECC box criterion. The expression for a generic reference voltage can be written as

5 1 / A voltage reference is shown in Fig. 8 illustrating the various parameters whose values can be set depending on the system. The parameters that decide the waveform can be determined for a given system by doing offline studies. Fig. 8. A generic voltage reference for determining FIDVR. This methodology is tested on the FIDVR response in PSSE at a bus with increasing percentage of IM load (from 5% to 30%) for faults of 3 cycles. The increasing amounts of IM load increased the delay in the recovery of voltage and this lead to the KL-index increasing for the increasing amount of IM load. The results are presented below in Fig. 9 and Fig. 10. Fig. 9. The voltage timeseries at the bus with increasing percentage of induction motor load. The dashed line is the reference voltage. The higher the IM percent, the longer they take to recover to their pre-fault voltage. amount of IM is the least Negative and goes positive for a small amount of time. Hence, the moving KL-index can differentiate between the various scenarios and can quantify the FIDVR in real-time. To test if the algorithm can indeed run in real-time and see what controls could be possible using this methodology, we need to simulate this in the Real-Time Test Bed. Default load models in OPAL-RT/RTDS are not capable of demonstrating the FIDVR phenomenon and so we need to construct detailed load models that can achieve this purpose. V. MODEL CREATION IN MODELICA FOR TEST BED As explained in Section III, simulating the FIDVR phenomena requires us to model a complicated load. The complicated nature of the load model makes it susceptible to numerical divergence as the motors are tightly coupled and are very sensitive to input parameters. Instead of modeling the entire model in a single go, it makes sense to build each model and then connect them after validating each one independently. Since the main components in the model are the Three 3-Phase IM and the 1-Phase AC Motor, we will be constructing them first. In this paper we will be focusing on the 3-Phase IM model. There are several kinds of models (3 rd order, 5 th order, etc.) and several means to model the IM model (Matlab, Simulink, etc.). Modeling in Open source software is preferred the models created can be tested and reused by others. Recent papers [12,13] have demonstrated the use of Modelica [14] for modeling the power system components in detail. The reason for using Modelica is the flexibility it provides and the ease of interfacing it with OPAL-RT. Components can be modelled using either block diagrams (suitable for Control Components ) or using code to write the differential algebraic equations that the variables internal to a model should satisfy (suitable for IM Loads & Generators). These components can then be combined to form a single Unit which can then be imported into Opal-RT or into other software as a Functional Mockup Unit (FMU). Figure 11 shows the general process of creating high fidelity models of power system components in Modelica. Fig. 11. Process of creating user defined high fidelity models of power system components in Modelica Fig. 10. The Moving Divergence based Index of the delayed voltage waveforms. It can be observed that the response with the least amount of IM is the most negative while the response with the largest Another reason for using Modelica is that there is an open source software, OpenModelica, that has the editor to create the models and simulate them using various standard DAE solvers such as DASSL, etc. This helps in quickly validating a model and identifying errors in the model.

6 The 5 th order Type-2 Induction Motor model is modelled in Modelica and is interfaced with OPAL-RT to test if it performs without errors and can demonstrate the stalling condition under stressed loading conditions. A Generator is connected to an IM load through a transmission line and a fault of 3 cycles is applied and cleared at the load bus. The voltage response and the slip of the IM are plotted below in Fig. 12. Fig. 12. The Voltage response and the Slip of the IM after clearing a fault of 3 cycles. The voltage settles to 0.82 p.u. and the slip rises to 0.85 denoting a stalled motor after the fault is cleared. It can be observed that the pre-fault voltage is around 0.97 p.u. and the post-fault voltage immediately after fault clearing is around 0.9 p.u. which is reasonable. However, the voltage falls and settles to a value around 0.82 p.u. which is a violation of the WECC criteria. The slip also rises to 0.85 after the fault and this indicates that the motor has stalled which is the reason for the low voltage. The KL-index for this voltage waveform rose very quickly to +1 indicating very severe FIDVR. Hence, we have successfully demonstrated the model running in real time and the KL-calculation running in real time. There are several steps necessary for complete validation and they are identified in the section below. VI. FUTURE STUDIES NECESSARY In order to validate the applicability of the method to a generic FIDVR voltage response, we need to first model the detailed composite load model in Modelica and verify the method on a reasonable sized system (~200 buses). In order to make the method implementable on a real system, guidelines to select the various parameters of the reference waveform should be provided to the system operator. Since, the control has to mitigate delayed voltage response, the control action needs to be activated in a few seconds. In the particular case of the FIDVR, load shedding at locations with the large number of small induction motors can be a viable option as most of them would nevertheless trip due to the thermal protection after 20s. The criticality of the loads connected to the same feeder and also the amount of load to be shed need to be considered before pursuing this control scheme. One of the main reasons for pursuing this method is the promise it shows in applying for other voltage stability phenomenon. We need to do more studies to show how the methods developed can help characterizing and understanding general stability phenomenon in power systems. CONCLUSION In this paper, the Cyber Physical Test-Bed setup is described in detail and the difference between EMTP and Phasor based simulation along with the reasons to use them were also explained. As a case study on using the Real-Time testbed, the FIDVR phenomenon is introduced and a method to monitor and quantify the FIDVR phenomena at a bus based on PMU measurements is described. This approach uses the idea of utilizing the Kullback-Leibler Divergence between the Probability Distributions of the delayed voltage response and the reference waveform as a way to quantify FIDVR. The method makes use of the streaming data from the PMU and compares the PDF of a moving window of samples with the reference waveform samples. The importance of building models is described and the Modelica modeling framework is introduced. The IM model is described and simulations results in OPAL-RT showing stalling are presented. Finally, future studies are identified to make the method implementable in the field. References [1] North American Reliability Corporation, "Final Report on the August 14, 2003 Blackout in the United States and Canada: Causes and Recommendations," April 5, 2004 [2] Energy Independence and Security Act - dbname=110_cong_bills&docid=f:h6enr.txt.pdf, [3] A. Hahn, A. Ashok, S. Siddharth, and G. Manimaran, "Cyber- Physical Security Testbeds: Architecture, Application, and Evaluation for Smart Grid," IEEE Trans. on Smart Grid, June 2013 [4] Reddy, A.; Ekmen, K.; Ajjarapu, V.; Vaidya, U., "PMU based real-time short term voltage stability monitoring Analysis and implementation on a real-time test bed," NAPS, 2014, vol., no., pp.1,6, 7-9 Sept [5] [6] S. Sridhar, and G. Manimaran, "Model-Based Attack Detection and Mitigation for Automatic Generation Control," IEEE Trans. on Smart Grid, March 2014 [7] Diaz de Leon, J.A.; Taylor, C.W., "Understanding and solving short-term voltage stability problems," Power Engineering Society Summer Meeting, 2002 IEEE, vol.2, no., pp.745,752 vol.2, July [8] WECC Model Validation Working Group, WECC Dynamic Composite Load Model Specifications, Jan [9] NERC SMS & NASPI EATT, Fault Induced Delayed Voltage Recovery (FIDVR) Advisory, July [10] PJM Transmission Planning Department, "EXELON Transmission Planning Criteria", March 11, [11] M. Paramasivam, S. Dasgupta, V. Ajjarapu and U. Vaidya, "Contingency Analysis and Identification of Dynamic Voltage Control Areas," in IEEE Transactions on Power Systems, vol. 30, no. 6, pp , Nov [12] T. Bogodorova et al., "A modelica power system library for phasor time-domain simulation," IEEE PES ISGT Europe 2013, Lyngby, 2013, pp [13] Franke, Rüdiger, and H. Wiesmann. "Flexible modeling of electrical power systems--the Modelica PowerSystems library." Proc. of 10 th Int. Modelica Conference; March 2014 [14]