A LOW JITTER LOW PHASE NOISE WIDEBAND DIGITAL PHASE LOCKED LOOP IN NANOMETER CMOS TECHNOLOGY

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1 International Journal of Electronics and Communication Engineering and (IJECET) Volume 9, Issue 3, May-June 2018, pp. 1 12, Article ID: IJECET_09_03_001 Available online at ISSN Print: and ISSN Online: IAEME Publication A LOW JITTER LOW PHASE NOISE WIDEBAND DIGITAL PHASE LOCKED LOOP IN NANOMETER CMOS TECHNOLOGY Nilesh D. Patel Research Scholar, Department of EC Institute of, Nirma University, Ahmedabad, India Dr. Amisha P. Naik Associate Professor, Department of EC Institute of, Nirma University, Ahmedabad, India ABSTRACT In this article innovative low jitter low phase noise 7.47 GHz DPLL with self-aligned DLL in 180 nm CMOS technology is implemented and analyzed. Based on proposed innovative concept, phase difference between injection signal and SILVCO in PLL can be aligned to reduce jitter and phase noise over all variations. Hence it can be achieved low phase noise and low jitter. At 7.47 GHz, the measured phase noise of proposed DPLL with self-aligned injection at 1-MHz offset is dbc/hz with a rms jitter of 110 fs. The total dc power consumption is mw. With self-aligned injection, proposed DPLL features the lowest jitter, phase noise, and best figure of merit among reported CMOS PLLs. Keywords: PLL, CMOS, DLL, PFD, VCO, Phase Noise, TSPC, VCDL Cite this Article: Nilesh D. Patel and Dr. Amisha P. Naik, A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos. International Journal of Electronics and Communication Engineering and, 9(3), 2018, pp INTRODUCTION The Phase locked loops (PLLs) find wide applications in many areas such as communication systems, wireless systems, digital circuits, power systems and disk drives. PLL is most likely useful building block as a high frequency clock generator circuit for ASIC designers, which gives timing flexibility to cancel out clock distribution delays, adjust setup and hold times, correct clock duty cycles and minimize clock skew & jitter. Different ranges of frequency, wide tuning range, low jitter and its attenuation, lock time, low power and low phase noise are the key characteristics of a PLL [2][6][8]. 1 editor@iaeme.com

2 A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos In today s era jitter, phase noise, power dissipation in phase locked loop is very important specifications for high frequency applications. Major sources of phase noise in PLL are VCO, PFD and input reference signal. It is known that phase noise is removed by high pass filter at input, while output of PFD is a low pass response. For a design of low jitter with less phase noise, selection of loop bandwidth is very important. If frequency of VCO is increases, phase noise becomes worst for PLL. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. Main issues for such design are locking range & phase matching between injected signal & oscillator [2] [6] [8] [10]. The Phase locked loops (PLLs) find wide applications in many areas such as communication systems, wireless systems, digital circuits, power systems and disk drives. PLL is most likely useful building block as a high frequency clock generator circuit for ASIC designers, which gives timing flexibility to cancel out clock distribution delays, adjust setup and hold times, correct clock duty cycles and minimize clock skew & jitter. Different ranges of frequency, wide tuning range, low jitter and its attenuation, lock time, low power and low phase noise are the key characteristics of a PLL [4][8][19]. 2. SILPLL CONCEPT & PROPOSED ARCHITETURE To achieve wide tuning range, power consumption and jitter is compromised. To achieve high frequency, other parameters are also compromised. Based on advance literature survey, following specifications are proposed for Phase Locked Loop. Table 1 Proposed Design Specification for DPLL Parameters Value 180 nm Supply Voltage 1.8 V Output Frequency 7 10 GHz Tuning Range 5 10 GHz Power Consumption < 20 mw RMS Jitter < 700 fs Phase Noise < -110 dbc / Hz To reduce the jitter and phase noise, a proposed new technique can be used in the PLL. Such design has more potential for the high speed applications. The key issues for DPLLs are the locking range and the phase synchronization between the injection signal and the SILVCO [1] [13] [14]. In this article, it has been presented new architecture with low jitter, low phase noise, low power 7.47 GHz Digital Phase Locked Loop with Self Aligned Delay Locked Loop in 180 nm CMOS technology using sub harmonic injection technique.. The measured phase noise of the proposed PLL with self-aligned injection at 1 MHz offset is dbc/hz and rms jitter is 110 fs. The total dc power consumption is mw. This article represents all possible analysis over the variations. Figure 1 Conventional Vs. Proposed DPLL [14][15][21] 2 editor@iaeme.com

3 Nilesh D. Patel and Dr. Amisha P. Naik The basic difference between conventional and proposed DPLL is shown above Figure 1. Here the VCO is replaced by sub harmonically injected VCO. The delay element is also introduced between input and SILVCO. Here DLL is used as a delay element for better accuracy and for optimum jitter [14] [15] [21]. Proposed DPLL consists of a third order PLL for 7.5 GHz clock generator and a first order DLL for self-aligned injection. The third order PLL is composed by SILVCO, a divide by N frequency divider, a PFD, and an LPF. Figure 2 Block Diagram of Proposed 7.5 GHz DPLL with Self Aligned DLL [15][21] The output phase and frequency are first locked to the input reference signal using the third order PLL, and then the injection phase for the sub harmonically injection locked VCO is automatically aligned using the first order DLL. In this proposed design, the loop bandwidth of the PLL is selected higher than the DLL. The phase and frequency of the sub harmonically injection locked VCO would be relocked to the reference signal again as the multiple frequency. The proposed self-aligned method features excellent robustness, high speed, and simple circuitry [15][16][21]. The phase and frequency can be automatically adjusted over variations. First output phase or frequencies are locked to input reference signal using PLL. Then injected phase of sub harmonically injection locked VCO is automatically aligned using DLL. Oscillator locks to an external signal whose frequency is close to natural frequency. This phenomenon is known as Injection Locking. It is also possible for oscillator to lock at a frequency that integral sub multiple frequency of applied signal. Phase of PLL & VCO must align precisely to minimize Jitter. As VCO Frequency increases, Phase noise is also increases. To reduce jitter & phase noise, DLL can be introduced. Reference signal is also injected into SILVCO to further suppress the jitter. Improved PLL Locking reduces Jitter, phase noise & increases locking range [14][15][16][21]. 3. PROPOSED DPLL DESIGN & SIMULATIONS 3.1. Phase Frequency Detector PFD is designed with Clocked Inverter & D Flip Flop using TSPC Logic. Such design of flip flop has less number of transistors. In this flip flop design only one transistor is being clocked by short pulse train which is known as True Single Phase Clocking flip flop [3][5][9]. Figure 3 Schematic of Modified PFD [3][5] 3 editor@iaeme.com

4 A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos The reset path of PFD is modified. The inputs signals data and dclock are directly connected to the reset signal of another D flip flop as shown in the Figure 3. The reset path is eliminated; hence it reduces the dead zone. The circuit of D flip flop is also modified. When clock and reset signals are low, node 1 will be connected to V DD through M2 and M5 devices. At rising edge of clock, node 2 will connect to ground through M6 & M7 devices. As node 1 is connected to V DD, turn off M3 keeping node 2 from charging high. Reset signal is charge up, node 1 is connected to ground through M5 and it pulls up node 2 due to switching M3 ON. The job of M2 is to prevent short circuit between M1, M2 & M5. Getting flipped value of Q, So one inverter has been added at output. Figure 4 Output of Phase Frequency Locked Condition Figure 5 Output of Phase Frequency 50 MHz Data Leg 3.2. Charge Pump & LPF Figure 6 Average Power Measurement at PFD Figure 7 Schematic of Charge Pump [6][20] 4 editor@iaeme.com

5 Nilesh D. Patel and Dr. Amisha P. Naik The Charge pump is the next block to the phase frequency detector. As shown in Figure 7, the output signals UP signal and DOWN signal generated by the PFD are directly connected to the charge pump [6][20]. In this design replica charge pump circuit is composed using M18, M19, M23 & M28. Here leakage current I 1 is almost equal to I 2. Hence leakage current is eliminated using this concept. This circuit is also referred as leakage compensation circuit. M28 & M29 provides high output impedance, where M28 always put higher or equal in size than M29. Such charge pump design provides full swing, so clock can be fully varied. Figure 8 Combine Output Waveform of PFD, Charge Pump & Loop Filter Figure 9 Average Power Measurement at PFD, CP & LPF 3.3. SILVCO VCO design is shown in Figure 10. Here, the coupling pair of M 3 - M 4 receives the single ended pulses at the gate of M 4, and injects a corresponding current into the LC tank. The dimensions of M 1 - M 2 & M 3 - M 4 pairs as well as the bias circuit I b1, M 5, and R b define the overall injection strength [13-16]. When nmos switch connect to differential node of VCO, the injected pulse become high. The switch turns ON and node is shorted. The pulse width should be less than rise/fall time of output for suitable injection. The injection is achieved by connecting a differential pair to differential output of VCO. Odd harmonics are injected to VCO. Excitations of either M3 or M4 will decide odd or even harmonic injection. The other side is grounded [13-16]. Figure 10 Schematic of SILVCO[13-16] 5 editor@iaeme.com

6 A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos 3.4. Divide by N Network The output of VCO again used as a one input of the PFD. This output is provided by Voltage Divider network. Where VD converts high frequency in close to reference frequency. Here same voltage divider circuit is used, which was used in earlier chapter Open Loop PLL Configuration Figure 11 Schematic of Voltage Divider Figure 12 Output of Digital PLL Figure 13 Average Power Measurement at VCO Figure 14 Phase Noise Plot versus offset Frequency of PLL at 1MHz 6 editor@iaeme.com

7 Nilesh D. Patel and Dr. Amisha P. Naik Figure 15 Slew Rate Measurement Table 2 Performance Parameters of Digital PLL Parameter Digital PLL 180 nm Power Supply 1.8 V Type of PLL Type II Third Order Reference Frequency MHz Centre Frequency 900 MHz Transistor Count 78 Frequency Tuning Range 1 GHz GHz Power Consumption 9.77 mw Slew Rate MEG Delay Ps Jitter 1.09 ns Figure of Merit db Phase Noise Open Loop & Closed Loop DLL Figure 16 Combine Output Waveform of PFD, Charge Pump Figure 17 Delay Measurement of PFD 7 editor@iaeme.com

8 A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Figure 18 Output Waveform of VCO Closed Loop DPLL Results Figure 19 Total Power Dissipation Measurement of DLL Table 3 Performance Parameters of DLL Parameter Power Supply Type of PLL Reference Frequency Centre Frequency DLL 180 nm 1.8 V Type II Third Order MHz 650 MHz Transistor Count 55 Frequency Tuning Range 500 MHz GHz Power Consumption Locking Range Jitter 2.76 mw 5-15 Cycles ps Figure 20 Combination of PLL+DLL 8 editor@iaeme.com

9 Nilesh D. Patel and Dr. Amisha P. Naik Figure 21 SILPLL Output 1.8 V Figure 22 SIL PLL Phase MHz - 1 GHz Figure 23 Power Measurement of VCO The phase noise analysis is also carried out at different stages as shown in mentioned results. It also concludes that the impact of phase noise is also optimum as compared to existing architectures. Proposed DPLL provide very wide tunning range. It can vary from approximately 7.25 GHz to 8.24 GHz after post layout results. It is very wide as compared to existing architectures. Table 4 Performance Comparisons of Proposed SILPLL Specifications Proposed DPLL 180 nm Supply Voltage 1.8 V Type of PLL SIL PLL Output Frequency GHz Ref. Frequency 250 MHz Frequency Tuning 7.25 GHz 8.24 GHz Range 9 editor@iaeme.com

10 A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Lock Range Settling Time Integrated Jitter Power Consumptions Figure of Merit Phase 1 MHz RMS AC / TRAN Noise 50 MHz (13 Cycle) ns 110 fs mw db dbc/hz uv 4. MONTE CARLO ANALYSIS Monte Carlo analysis is carried out for different blocks of proposed DPLL. Simulations are carried out using Tanner Tool. Total 500 iterations are taken for analysis. For PFD, dead zone analysis, for CP, maximum voltage swing and for VCO, output frequency analysis is performed. Figure 24 Monte Carlo Simulations of PFD Figure 25 Monte Carlo Simulations of CP Figure 26 Monte Carlo Simulations of DLL 10 editor@iaeme.com

11 Nilesh D. Patel and Dr. Amisha P. Naik Figure 27 Monte Carlo Simulations of Proposed DPLL Figure 28 Eye Diagram of VCO for Jitter Measurements 5. CONCLUSION The general D flip flop cannot be used with PFD as the reset signal makes the output of PFD oscillating. Modified TSPC Logic based D flip flop is designed for the requirement. PFD is to be designed to reduce the dead zone & also provides adaptability. LC Base Oscillator is used for the Sub Harmonic Injection purpose to achieve High Frequencies. Achieved optimum Jitter & Phase Noise for the design using a new architecture. A modified model of DPLL can be significantly improved using the self-aligned sub harmonically injection locked technique. At 7.47 GHz, resultant phase noise of proposed PLL with self-aligned injection at 1-MHz offset is dbc/hz with a rms jitter of 110 fs. Total dc power consumption is mw. This work demonstrates excellent performance, Low Power / Low Noise / Low RMS Jitter / High Frequency and Good results over the variations, and it can also be compared with recently developed state of the art sub harmonically injection locked PLLs. A powerful technique substantially reducing the phase noise of general PLLs has been proposed and simulated. REFERENCES [1] Kenta Sogo, Akihiro Toya, A Ring VCO Based Sub Sampling PLL CMOS Circuit with 0.73 ps Jitter and 20.4 mw Power Consumption, IEEE, [2] Jeng-Han Tsai, Shao-Wei Huang, and Jian-Ping Chou, A 5.5 GHz Low-Power PLL using 0.18-μm CMOS technology, IEEE [3] Jen-Chieh Chih, Ching Te-Chiu, Piecewise Linear Phase Frequency Detector for Fast Lock Phase Locked Loop, IEEE [4] S. Moorthi, D. Meganathan, M. Shankar, R. Sridhar and J. Raja Paul Perinbam, A Low- Jitter Phase-Locked Loop Architecture for Clock Generation in Analog to Digital Converters, IEEE [5] Ms. Vaijayanti Lule, Prof. (Ms.) Vrushali Nasre, Area efficient 0.18um Cmos phase frequency detector for high speed PLL, International Journal of Scientific and Research Publications, Volume 2, Issue 2, February 2012, ISSN editor@iaeme.com

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