Programmable Low-Jitter Precision CMOS Oscillator

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1 DSC8121 General Description The DSC8101 & DSC8121 series of high performance fieldprogrammable oscillators utilizes a proven silicon MEMS technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures. Using the TIMEFLASH programmer, the end user can easily program the oscillators frequency in the field for immediate testing or use in advance prototype development or production. DSC8101 has a standby feature allowing it to completely powerdown when EN pin is pulled low; whereas for DSC8121, only the outputs are disabled when EN is low. Both oscillators are available in industry standard packages, including the small 3.2x2.5 mm 2, and are dropin replacement for standard 4pin CMOS quartz oscillators. Block Diagram Features Low RMS Phase Jitter: <1 ps (typ) High Stability: ±10, ±25, ±50 ppm Wide Temperature Range o Automotive: 55 to 125 C o Ext. Industrial: 40 to 105 C o Industrial: 40 to 85 C o Ext. commercial: 20 to 70 C High Supply Noise Rejection: 50 dbc Short Lead Time: 2 Weeks Wide Freq. Range: 10 to 170 MHz Small Industry Standard Footprints o 3.2x2.5, 5.0x3.2, and 7.0x5.0 mm Excellent Shock & Vibration Immunity o Qualified to MILSTD883 High Reliability o 20x better MTF than quartz oscillators Low Current Consumption Supply Range of 2.25 to 3.6 V Standby & Output Enable Function Lead Free & RoHS Compliant Applications Output Enable Modes EN Pin DSC8101 DSC8121 High Output Active Output Active NC Output Active Output Active Low Standby Output Disabled Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 10GEPON, GPON, 10GPON Ethernet o 1G, 10GBASET/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express DisplayPort Page 1

2 Absolute Maximum Ratings Item Min Max Unit Condition Supply Voltage V Input Voltage 0.3 V DD +0.3 V Junction Temp +150 C Storage Temp C Soldering Temp +260 C 40sec max. ESD HBM MM CDM Note: years of data retention on internal memory V Ordering Code Enable Modes 0: Enable/Standby 2: Enable/Disable DSC C I 5 Package A: 7.0x5.0mm B: 5.0x3.2mm C: 3.2x2.5mm Temp Range E: 20 to 70 I: 40 to 85 L: 40 to 105 M: 55 to 125 Stability 1: ±50ppm 2: ±25ppm 5: ±10ppm Packing T: Tape & Reel : Tube T Specifications Parameter Condition Min. Typ. Max. Unit Supply Voltage 1 V DD V Supply Current Frequency Stability Ext Comm. & Ind. only All temp ranges All temp ranges I DD f 1. Pin 6 V DD should be filtered with 0.1uf capacitor. 2. t su is time to 100PPM of output frequency after V DD is applied and outputs are enabled. 3. Output Waveform and Test Circuit figures below define the parameters. 4. Output is enabled if pad is floated or not connected. EN pin low output is disabled DSC8101 DSC Includes frequency variations due to initial tolerance, temp. and power supply voltage Aging f 1 C ±5 ppm Startup Time 2 t SU T=25 C 5 ms Input Logic Levels Input logic high Input logic low 0.75xV DD V IH V V IL 0.25xV DD Output Disable Time 3 t DA 5 ns Output Enable Time t EN DSC8101 DSC8121 Enable PullUp Resistor 4 Pullup resistor exist 40 kω Supply Current 4 Output Logic Levels Output logic high Output logic low Output Transition time 3 Rise Time Fall Time I DD V OH V OL t R t F Frequency f 0 CMOS Output output is enabled C L =15pF, F 0 =125 MHz I=±6mA 20% to 80% C L =15pF All temp range except Auto Auto temp range 0.9xV DD ±10 ±25 ± ma ppm ms ns ma 0.1xV DD Output Duty Cycle SYM % Period Jitter J PER Fout=125MHz 3 Integrated Phase Noise J PH 200kHz to 125MHz 100kHz to 125MHz 12kHz to 125MHz V ns MHz ps RMS ps RMS Page 2

3 Nominal Performance Parameters (Unless specified otherwise: T=25 C, V DD =3.3 V) Phase Jitter (ps RMS) MHz CMOS 50MHz CMOS 106MHz CMOS 125MHz CMOS Rejection (dbc) mv 100 mv Lowend of integration BW: x khz to 20 MHz Phase jitter (integrated phase noise) Supply Noise Frequency (khz) Power supply rejection ratio Output Waveform t R t F V OH Output V OL 1/f o t EN t DA V IH Enable V IL Typical Termination Scheme V DD 0.1uF Rs Ω Rs = 0 Ω for test C L CMOS load capacitance Rs serves to match the trace impedances. Depending on board layout, the value may rangefrom0to 30ohms. Page 3

4 Test Circuit I DD V DD 0.1uF pF V DA Board Layout (recommended) Solder Reflow Profile Temperature ( C) 260 C 217 C 200 C 150 C 25 C 3C/Sec Max Sec Pre heat 8 min max 3C/Sec Max Sec Sec Reflow 6C/Sec Max. Cool Time MSL 260 C refer to JSTD020C RampUp Rate (200 C to Peak Temp) 3 C/Sec Max. Preheat Time 150 C to 200 C Sec Time maintained above 217 C Sec Peak Temperature C Time within 5 C of actual Peak 2040 Sec RampDown Rate 6 C/Sec Max. Time 25 C to Peak Temperature 8 min Max. Page 4

5 Package Dimensions 7.0 x 5.0 mm Plastic Package 5.0 x 3.2 mm Plastic Package Page 5

6 3.2 x 2.5 mm Plastic Package DISCERA, Inc Concourse Drive, San Jose, California USA Phone: +1 (408) Fax: +1 (408) sales@discera.com Page 6

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