Programmable Low-Jitter Precision LVDS Oscillator
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1 General Description The & series of high performance fieldprogrammable oscillators utilizes a proven silicon MEMS technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures. Using the TIMEFLASH programmer, the end user can easily program the oscillators frequency in the field for immediate testing or use in advance prototype development or production. has a standby feature allowing it to completely powerdown when EN pin is pulled low; whereas for, only the outputs are disabled when EN is low. Both oscillators are available in industry standard packages, including the small 3.2x2. mm 2, and are dropin replacement for standard 6pin LVDS quartz oscillators. Block Diagram Features Low RMS Phase Jitter: <1 ps (typ) High Stability: ±10, ±2, ±0 ppm Wide Temperature Range o Industrial: 40 to 8 C o Ext. commercial: 20 to 70 C High Supply Noise Rejection: 0 dbc Wide Freq. Range: 10 to 460 MHz Small Industry Standard Footprints o 2.x2.0, 3.2x2.,.0x3.2, & 7.0x.0 mm Excellent Shock & Vibration Immunity o Qualified to MILSTD883 High Reliability o 20x better MTF than quartz oscillators Low Current Consumption Supply Range of 2.2 to 3.6 V Standby & Enable Function Lead Free & RoHS Compliant LVPECL & HCSL Versions Available Applications Enable Modes EN Pin High s Active s Active NC s Active s Active Low Standby s Disabled Storage Area Networks o SATA, SAS, Fibre Channel Passive Optical Networks o EPON, 10GEPON, GPON, 10GPON Ethernet o 1G, 10GBASET/KR/LR/SR, and FCoE HD/SD/SDI Video & Surveillance PCI Express: Gen 1 & Gen 2 DisplayPort Page 1
2 Absolute Maximum Ratings Item Min Max Unit Condition Supply Voltage V Input Voltage 0.3 V DD +0.3 V Junction Temp +10 C Storage Temp +10 C Soldering Temp +260 C 40sec max. ESD HBM MM CDM Note: years of data retention on internal memory V Ordering Code Enable Modes 0: Enable/Standby 2: Enable/Disable DSC81 0 Package A: 7.0x.0mm B:.0x3.2mm C: 3.2x2.mm D: 2.x2.0mm 3 C I Temp Range E: 20 to 70 I: 40 to 8 Stability 1: ±0ppm 2: ±2ppm : ±10ppm Packing T: Tape & Reel : Tube T Specifications Parameter Condition Min. Typ. Max. Unit Supply Voltage 1 V DD V Supply Current Frequency Stability I DD Notes: 1. Pin 6 VDD should be filtered with 0.1uf capacitor. 2. tsu is time to 100ppm of output frequency after VDD is applied and outputs are enabled. 3. Waveform and Test Circuit figures below define the parameters. 4. is enabled if pad is floated or not connected. Δf EN pin low outputs are disabled 20 Includes frequency variations due to initial tolerance, temp. and power supply voltage Aging Δf 1 C ± ppm Startup Time 2 t SU T=2 C ms Input Logic Levels Input logic high Input logic low V IH V IL 0.7xV DD ±10 ±2 ±0 0.2xV DD Disable Time 3 t DA ns Enable Time t EN Enable PullUp Resistor 4 Pullup resistor exist 40 kω LVDS s Supply Current I DD Enabled, R L =0Ω ma offset Voltage V OS R=100Ω Differential V Delta Offset Voltage V OS 0 mv Pk to Pk Swing V PP SingleEnded 30 mv Transition time 3 Rise Time Fall Time t R t F 20% to 80% R L =0Ω, C L = 2pF 20 ma ppm V ms ns 200 ps Frequency f 0 Single Frequency MHz Duty Cycle SYM Differential 48 2 % Period Jitter J PER 2. ps RMS Integrated Phase Noise J PH 200kHz to 100kHz to 12kHz to ps RMS Page 2
3 Rejection (dbc) Phase Jitter (ps RMS) Nominal Performance Parameters (Unless specified otherwise: T=2 C, V DD =3.3 V) mV 100mV MHzLVDS 212MHzLVDS 320MHzLVDS 410MHzLVDS Supply Noise Frequency (khz) Power supply rejection ratio Lowend of integration BW: x khz to 20 MHz Phase jitter (integrated phase noise) Waveform t R t F 80% 0% 20% mv mv 1/f o t EN t DA V IH Enable V IL Typical Termination Scheme V DD 0.1uF Ω 100 Ω Page 3
4 Temperature ( C) Test Circuit Solder Reflow Profile 260 C 217 C 200 C 10 C 2 C 3C/Sec Max Sec Pre heat 8 min max 3C/Sec Max Sec 6010 Sec Reflow 6C/Sec Max. Cool Time MSL 260 C refer to JSTD020C RampUp Rate (200 C to Peak Temp) 3 C/Sec Max. Preheat Time 10 C to 200 C Sec Time maintained above 217 C 6010 Sec Peak Temperature 2260 C Time within C of actual Peak 2040 Sec RampDown Rate 6 C/Sec Max. Time 2 C to Peak Temperature 8 min Max. Page 4
5 Package Dimensions x.0 mm Plastic Package No Pin terminal Enable nc GND VDD.0 x 3.2 mm Plastic Package Page
![3.2 x 2. mm Plastic Package 2. x 2.0 mm Plastic Package 2.±0.0 [0.098±0.002] 0.82 [.032 ] 0.7±0.10 [0.028±0.004] 0.9 [.03] REF 0.1 [.004] REF 0.37 [0.01] 2.0±0.0 [0.079±0.002] 0.6±0.0 [0.026±0.002] 0.2±0.](/docs-images/75/72047570/images/6-5.jpg "0 [0.099±0.002] 0.8 [0.033] 0.70 [0.028] 0.6 [0.026] 0.2 [0.")
6 3.2 x 2. mm Plastic Package 2. x 2.0 mm Plastic Package 2.±0.0 [0.098±0.002] 0.82 [.032 ] 0.7±0.10 [0.028±0.004] 0.9 [.03] REF 0.1 [.004] REF 0.37 [0.01] 2.0±0.0 [0.079±0.002] 0.6±0.0 [0.026±0.002] 0.2±0.0 [0.099±0.002] 0.8 [0.033] 0.70 [0.028] 0.6 [0.026] 0.2 [0.0098] Disclaimer: Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. MICREL, Inc Fortune Drive, San Jose, California 9131 USA Phone: +1 (408) Fax: +1 (408) hbwhelp@micrel.com Page 6
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PL XIN CLK XOUT VCON. Xtal Osc. Varicap. Low Phase Noise VCXO (17MHz to 36MHz) PIN CONFIGURATION FEATURES DESCRIPTION BLOCK DIAGRAM
FEATURES PIN CONFIGURATION VCXO output for the 17MHz to 36MHz range Low phase noise (-130dBc @ 10kHz offset at 35.328MHz) LVCMOS output with OE tri-state control 17 to 36MHz fundamental crystal input Integrated
OE CLKC CLKT PL PL PL PL602-39
PL602-3x XIN VDD / * SEL0^ / VDD* SEL^ FEATURES Selectable 750kHz to 800MHz range. Low phase noise output -27dBc/Hz for 55.52MHz @ 0kHz offset -5dBc/Hz for 622.08MHz @ 0kHz offset LVCMOS (PL602-37), LVPECL
SiT MHz to 725 MHz Ultra-low Jitter Differential VCXO
SiT3373 220 MHz to 725 MHz Ultra-low Jitter Differential VCXO Features Any frequency between 220.000001 MHz and 725 MHz accurate to 6 decimal places Widest pull range options: ±25, ±50, ±80, ±100, ±150,
MIC5501/2/3/4. General Description. Features. Applications. Typical Application. Single 300mA LDO in 1.0mm 1.0mm DFN Package
Single 300mA LDO in 1.0mm 1.0mm DFN Package General Description The is an advanced general-purpose LDO ideal for powering general-purpose portable devices. The family of products provides a highperformance
PARAMETER SYMBOL CONDITIONS VALUE UNIT
Page 1 of 6 FEATURES APPLICATIONS ±0.28 ppm Holdover Stability Mobile Phones ±4.6 ppm accuracy over all conditions Base Stations including 20 years aging Mobile Radios Miniature 5x7 mm SMD GPS Devices
VT-802 VT-802. Temperature Compensated Crystal Oscillator. Description
T-802 Temperature Compensated Crystal Oscillator T-802 Description ectron s T-802 Temperature Compensated Crystal Oscillator (TCXO) is a quartz stabilized, CMOS output, analog temperature compensated oscillator,
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMMENDED FOR NEW DESIGNS ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER FEATURES - Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL
MIC5317. Features. General Description. Applications. Typical Application. High-Performance Single 150mA LDO
High-Performance Single 150mA LDO General Description The is a high performance 150mA low dropout regulator offering high power supply rejection (PSRR) in an ultra-small 1mm 1mm package for stringent space
Features. Truth Table (1)
3.3V/5V, 4GHz PECL/ECL 2 Clock Generator Precision Edge General Description The is an integrated 2 divider with differential clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small
Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom
MIC5365/6. General Description. Features. Applications. Typical Application. High-Performance Single 150mA LDO
High-Performance Single 150mA LDO General Description The is an advanced general purpose linear regulator offering high power supply rejection (PSRR) in an ultra-small 1mm 1mm package. The MIC5366 includes
Features. Applications
Teeny Ultra-Low Power Op Amp General Description The is a rail-to-rail output, operational amplifier in Teeny SC70 packaging. The provides 4MHz gain-bandwidth product while consuming an incredibly low
Features. Applications
High PSRR Low Noise 300mA µcap Ultra-Low Dropout LDO Regulator General Description The is a high-performance, 300mA LDO regulator, offering extremely high PSRR and very low noise while consuming low ground
7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH TERNAL I/O TERMATION Precision Edge FEATURES - Precision 1:2, 400mV CML fanout buffer - Low jitter performance: 49fs RMS phase jitter (typ) - Guaranteed AC performance
Features. 1 CE Input Pullup
CMOS Oscillator MM8202 PRELIMINARY DATA SHEET General Desription Features Using the IDT CMOS Oscillator technology, originally developed by Mobius Microsystems, the MM8202 replaces quartz crystal based
SiT9003 Low Power Spread Spectrum Oscillator
Features Frequency range from 1 MHz to 110 MHz LVCMOS/LVTTL compatible output Standby current as low as 0.4 µa Fast resume time of 3 ms (Typ)