RF Signal Processing Servo Amplifier for CD Player

Transcription

1 CA2542Q RF Signal Processing Servo Amplifier for C Player escription The CA2542Q is a bipolar IC developed for C player RF signal processing and servo control. 48 pin QFP (Plastic) Features Automatic focus bias adjustment circuit Automatic tracking balance and gain adjustment circuits RF level control circuit Interruption countermeasure circuit Anti-shock circuit efect detection and prevention circuits RF -V amplifier, RF amplifier APC circuit Focus and tracking error amplifier Focus, tracking and sled servo control circuits Focus OK circuit Mirror detection circuit Single power supply and dual power supplies Absolute Maximum Ratings (Ta = 25 C) Supply voltage 2 V Operating temperature Topr 2 to +75 C Storage temperature Tstg 65 to +5 C Allowable power dissipation P 4 mw Recommended Operating Conditions Operating supply voltage V 3. to 5.5 V Applications C players Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 96Y3-PS

2 CA2542Q Block iagram F F IV AMP F AMP IV AMP FO. BIAS WINOW COMP. V V TGFL TRK. GAIN WINOW COMP. -F BALANC WINOW COMP. IIL ATA RGISTR INPUT SHIFT RGISTR ARSS COR SNS SLCTOR OUTPUT COR FCT TM TG TRACKING PHAS COMPNSATION FCTO IFB-6 BAL-4 TOG-4 FS-4 TG-2 TM-7 PS-4 V FI FFCT FG FLB F_O F_M SRCH TGU TG2 FST TA_M P P L RFTC RF_M RF_O RF_I CP CB CC CC2 FOK V P IV AMP RF SUMMING AMP P2 37 P2 IV AMP APC 24 SNS2 38 V LASR POWR CONTROL IIL TTL 23 SNS 39 IFB IFB2 IFB3 IFB4 IFB5 IFB6 V FCT 22 C. OUT 4 TO 4 BAL TOG TOG2 TOG3 BAL2 TOG4 BAL3 BAL4 V V LVL S V MIRR IIL TTL 2 2 RST ATA FOK TTL IIL LPFI 42 ATSC 43 TZC 44 ATSC WINOW COMP. FOH FOL TGH TGL BALH BALL ATSC TZC FZC LON LPCL LPC TGFL MIRR FCT CC LT CLK TFCT 45 TZC COMP. IST 6 IST VC 46 TM4 TM6 5 SL_O FZC 47 TM7 4 SL_M FO 48 FZC COMP. FOCUS PHAS COMPNSATION FS TM3 TM5 3 SL_P FCT FS2 FST V V TM2 FS4 TG2 V TA_O 2

3 CA2542Q Pin escription Pin No. Symbol I/O quivalent circuit escription FI I 47 k Focus error input. 2 FFCT I µ Connects the capacitor for defect time constant. 3 FG I k 3k 4µ Ground this pin through a capacitor for cutting the focus servo highfrequency gain. 4 FLB I 4 4k 33k 47k xternal time constant setting pin for boosting the focus servo lowfrequency. 5 F_O O Focus drive output. 2 TA_O O 5 2 Tracking drive output. 5 5 SL_O O 25µ Sled drive output. 9k 47 6 F_M I 6 Focus amplifier inverted input. 5k 2µ 7 SRCH I k xternal time constant setting pin for generating focus search waveform. 5k µ 3

4 CA2542Q Pin No. Symbol I/O quivalent circuit escription 8 TGU I k k 82k xternal time constant setting pin for switching tracking highfrequency gain. 9 TG2 I 9 47k xternal time constant setting pin for switching tracking high-frequency gain. FST I 47k 5k 5k Peak frequency setting pin for focus and tracking phase compensation amplifier. k 47 TA_M I Tracking amplifier inverted input. µ 3 SL_P I 3 47 Sled amplifier non-inverted input. 2µ 4 SL_M I 4 47 Sled amplifier inverted input. 22µ 6 IST I µ Connects the external capacitor to set the current which determines the Focus search, Track jump, and Sled kick levels. 4

5 CA2542Q Pin No. Symbol I/O quivalent circuit escription 7 I 7 Positive power supply. 8 CLK I 2µ Serial data transfer clock input from CPU. (no pull-up resistance) 8 47 k 2 ATA I 2 Serial data input from CPU. (no pull-up resistance) 9 LT I 2µ Latch input from CPU. (no pull-up resistance) k 2 RST I 2 2.5p Reset input; resets at Low. (no pull-up resistance) 22 C. OUT O Track number count signal output. 23 SNS O 24 SNS2 O k k Outputs FZC, FCT, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU. Outputs FCT2, MIRR, BALL, TGL, FOL, and others according to the command from the CPU. 2k FOK O 25 4k Focus OK comparator output. k 5

6 CA2542Q Pin No. Symbol I/O quivalent circuit escription 26 CC2 I 27 CC O Input for the defect bottom hold output with capacitance coupled. efect bottom hold output. Connected internally to the interruption comparator input. 28 CB I 2k k 47 43k 26 Connects the defect bottom hold capacitor. 29 CP I 29 k.5k Connects the MIRR hold capacitor. MIRR comparator non-inverted input. 3 RF_I I Input for the RF summing amplifier output with capacitance coupled. 3 RF_O O 3 47 RF summing amplifier output. yepattern check point. 32 RF_M I 3 47 k 47 k 32 RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin. 33 RFTC I µ 5µ xternal time constant setting pin during RF level control. µ 6

7 CA2542Q Pin No. Symbol I/O quivalent circuit escription k k 34 L O 34 APC amplifier output. 8µ 2µ 35 P I 47 55k 35 APC amplifier input. k k.2p 8k P P2 I I µ 2k 7.5k RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + pins. 2p F I I k µ 5 F I-V and I-V amplifier inverted input. Connects these pins to photo diodes F and. 4 V 4 V Negative power supply. 7

8 CA2542Q Pin No. Symbol I/O quivalent circuit escription 4 TO O k 2k 32k 5k 5k 6.6k 3k Tracking error amplifier output. -F signal is output. 5k 45 TFCT I k 3µ Connects the capacitor for defect time constant. 42 LPFI I Comparator input for balance adjustment. (Input from TO through LPF) 7µ k k 43 ATSC I Window comparator input for ATSC detection. k k µ µ µ 44 TZC I Tracking zero-cross comparator input. 75k 8

9 CA2542Q Pin No. Symbol I/O quivalent circuit escription 2 k 46 VC O 5 ( + V)/2 direct voltage output k VC µ 5k FZC I 47 Focus zero-cross comparator input. 75k 9k 48 FO O p 74k 3µ µ µ Focus error amplifier output. Connected internally to the window comparator input for bias adjustment. 9

10 CA2542Q lectrical Characteristics ( =.5V, V =.5V, Topr = 25 C) TST Item SW conditions (ON switches) S Input pin Measurement pin Measurement conditions Min. Typ. Max. Unit T Current consumption 9 (OFF) RST ma T2 Current consumption 2 9 (OFF) RST ma T3 Center amplifier output offset 9 (OFF) RST 46 T4 Offset RST T5 T6 RF amplifier Voltage gain Max. output amplitude - High, 3, 3 RST RST khz I/O ratio V2 =.2VC V T7 Max. output amplitude - Low, 3 RST V2 =.2VC.6.3 V T8 Offset 39F 48 FB6: ON 2 2 T9 Voltage gain 39F khz I/O ratio T Voltage gain F khz I/O ratio T Voltage gain difference 39F 3 3 T2 Max. output voltage High 3 39F V2 = C.3 V T3 T4 T5 F amplifier Max. output voltage Low BIAS BIAS 39F 3BF 3B V2 = C IFB, 2, 3, 4, 5, 6: OFF IFB: ON, BIAS: reference V T6 BIAS2 3B 48 IFB2: ON, BIAS: reference Output gain difference with T T7 BIAS3 3BB 48 IFB3: ON, BIAS: reference Output gain difference with V T8 BIAS4 3B7 48 IFB4: ON, BIAS: reference Output gain difference with V T9 BIAS5 3AF 48 IFB5: ON, BIAS: reference Output gain difference with V T2 BIAS6 39F 48 IFB6: ON, BIAS: reference Output gain difference with V

11 CA2542Q TST Item SW conditions (ON switches) S Input pin Measurement pin Measurement conditions Min. Typ. Max. Unit T2 T22 F amplifier FOH threshold FOL threshold 39F 39F IFB6: ON Pin voltage when SNS (Pin 23) goes from High to Low IFB6: ON Pin voltage when SNS2 (Pin 24) goes from High to Low T23 Offset 34F TOG: OFF, BAL, 2, 3: ON T24 GAIN UP (F) 4 36F V = 2 khz, I/O ratio TOG: OFF, BAL, 2, 3: ON T25 GAIN UP () 5 36F V = 2 khz, I/O ratio TOG: OFF, BAL, 2, 3: ON T26 Voltage gain F 4 34F 38 4 V = 2kHz, TOG: OFF I/O ratio T27 Voltage gain F F 38 4 V = 2kHz, TOG: ON Reference to F T28 Voltage gain F V = 2kHz, TOG2: ON Reference to F T29 T3 T3 T amplifier Voltage gain F3 Voltage gain F4 Voltage gain B F 3F V = 2kHz, TOG3: ON Reference to F V = 2kHz, TOG4: ON Reference to F V = 2kHz, BAL: OFF I/O ratio T32 Voltage gain V = 2kHz, BAL: ON Reference to T33 Voltage gain V = 2kHz, BAL2: ON Reference to T34 Voltage gain 3 5 3B 39 4 V = 2kHz, BAL3: ON Reference to T35 Voltage gain V = 2kHz, BAL4: ON Reference to T36 Max. output voltage High 34F V = VC, TOG: OFF, BAL, 2, 3: ON.5.7 V T37 Max. output voltage Low 34F V = VC, TOG: OFF, BAL, 2, 3: ON.8.5 V T38 Output voltage 3C I = 364µA T39 Output voltage 2 3C I = 439µA T4 APC Output voltage 3 3C I = 55µA T4 Output voltage 4 9 3C mA sink T42 L OFF 3C I = 55µA, L: OFF..3 V

12 CA2542Q TST Item SW conditions (ON switches) S Input pin Measurement pin Measurement conditions Min. Typ. Max. Unit T43 5% limit 8 3C I = 273µA Output difference with LPC ON/OFF T44 T45 T46 RF level controll 7% limit 5% limit 7% limit 8, 3, 3 3C5 3C7 3C I = 394µA Output difference with LPC ON/OFF 476 I = 742µA 42 Output difference with LPC ON/OFF I = 62µA 83 Output difference with LPC ON/OFF T47 irect voltage gain T48 FCS total gain T9 + T T49 Feed through 8 5 I/O gain difference between S = and S = 8. 3 T5 T5 Focus servo FZC threshold Max. output voltage High Pin 47 voltage when SNS (Pin 23) goes from Low to High V = 2C V T52 Max. output voltage Low 8 5 V = 2C.3 V T53 Search voltage ( ) T54 Search voltage (+) T55 irect voltage gain C gain between TO and TA_O T56 TRK total gain T26 + T T57 Feed through Output gain difference between S = 2 and S = T58 Max. output voltage High V =.3VC.3 V T59 T6 Tracking servo Max. output voltage Low Jump output voltage ( ) C V =.3VC V T6 Jump output voltage (+) T62 ATSC threshold ( ) 5, Input voltage when TG2 (Pin 9) goes from Vcc/2 to Vcc T63 ATSC threshold (+) 5, Input voltage when TG2 (Pin 9) goes from Vcc/2 to Vcc T64 TZC threshold Pin 44 voltage when SNS (Pin 23) is V 2 2 2

13 CA2542Q TST Item SW conditions (ON switches) S Input pin Measurement pin Measurement conditions Min. Typ. Max. Unit T65 BAL COMP threshold High Pin 42 voltage when SNS (Pin 23) goes from High to Low T66 T67 Tracking servo BAL COMP threshold Low GAIN COMP threshold High F Pin 42 voltage when SNS2 (Pin 24) goes from High to Low Pin 4 voltage when SNS (Pin 23) goes from High to Low T68 GAIN COMP threshold Low F 38 4 Pin 4 voltage when SNS2 (Pin 24) goes from Low to High T69 FOK FOK threshold Pin 3 voltage when Pin 25 is V T7 Voltage gain 6, V = Hz, I/O ratio 5 T7 Feed through Output gain difference between S = 2 and S = T72 T73 Sled servo Max. output voltage High Max. output voltage Low V = 4C V = 4C.3.3 V V T74 Kick voltage 2 5 RV T75 Kick voltage FW T76 Max. operating frequency Measures at SNS2 pin. 3 khz T77 T78 MIRROR Min. input operating voltage Max. input operating voltage Measures at SNS2 pin. Measures at SNS2 pin..8.3 Vp-p Vp-p T79 Min. operating frequency,, 2, Measures at SNS pin. khz T8 T8 FCT Max. operating frequency Min. input operating voltage,, 2, 3,, 2, Measures at SNS pin. Measures at SNS pin khz Vp-p T82 Max. input operating voltage,, 2, Measures at SNS pin..8 Vp-p 3

14 FFCT FG FLB F_O F_M SRCH TGU TG2 FST TA_M TA_O CA2542Q V2 AC C S3 GN R2 39k S4 R 39k S5 39 GN C2 33µ V 4 R26 k 4 GN S6 42 GN S7 43 GN S8 44 GN GN GN C P S9 S GN R3 k V AC C GN I µa V I2.8mA R8 33 R M V C5 µ R4 k GN R3 22k GN GN GN S8 C6 C7.µ.µ C9 33p R9 k F V TO LPFI ATSC TZC TFCT VC FZC SNS2 SNS C. OUT RST ATA LT CLK Vcc IST SL_O SL_M SL_P S S2 R9 47k S3 C4.µ R2 k R 3k S5 R5 k R6 5k R7 k C8.µ R8 3k GN GN GN C3 P GN GN GN R23 6k S7 R22 k R2 k R2 k RST C 33µ R26 2k R25 3k R24 5.k LT CLK GN C 47µ GN ATA V GN GN S6 FI P P L RFTC RF_M RF_O RF_I CP CB CC CC2 FOK lectrical Characteristics Measurement Circuit R5 24k R6 24k S2 S R4 k R7 k 48 S S P2 FO

15 FFCT FG FLB F_O F_M SRCH TGU TG2 FST TA_M TA_O P L RFTC RF_M RF_O RF_I CP CB CC CC2 FOK FI FFCT FG FLB F_O F_M SRCH TGU TG2 FST TA_M TA_O P P L RFTC RF_M RF_O RF_I CP CB CC CC2 FOK CA2542Q Application Circuit (±2.5V power supply) µ Vcc Vcc 22 µ k 3.3µ A C B V 5 L µh P V V M µ 22k.µ.33µ.µ.33µ MICRO COMPUTR SP F 37 P2 38 F SNS2 24 SNS C. OUT 22 V 4 V RST 2 k 5k.µ.µ 4 TO 42 LPFI ATA 2 LT 9 43 ATSC.47µ 47k 33k 47p 44 TZC.22µ 45 TFCT.µ 46 VC 47 FZC.22µ 48 FO CLK 8 Vcc 7 IST 6 SL_O 5 SL_M 4 SL_P 3 6k k Vcc V RIVR.5µ 8.2k 3.3µ Application Circuit 2 (Single +5V power supply) k k.µ 4.7µ k.µ k 5k k.33µ.µ.5µ 22p RIVR Vcc RIVR 82k 22µ 5k Vcc µ Vcc 22 µ k 3.3µ A C B 5 µh P L M µ 22k.33µ.µ.µ.33µ MICRO COMPUTR SP FI P 37 P2 F 38 F 39 4 V 4 TO k 5k 42 LPFI.µ.µ 43 ATSC.47µ 47k 33k.22µ Vcc 47p µ 44 TZC.µ 45 TFCT 46 VC µ 47 FZC.22µ 48 FO SNS2 24 SNS 23 C. OUT 22 RST 2 ATA 2 LT 9 CLK 8 Vcc 7 IST 6 SL_O 5 SL_M 4 SL_P 3 6k k Vcc RIVR.5µ 8.2k 3.3µ k k µ 68k.µ 4.7µ k 5k k 22p.33µ.µ.5µ RIVR 5 Vcc RIVR 82k 22µ 5k Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

16 CA2542Q escription of Functions RF Amplifier The photodiode currents input to the input pins (P and P2) are each I-V converted through a 58kΩ equivalent resistor by the P I-V amplifiers. These signals are added by the RF summing amplifier, and the photodiode (A + B + C + ) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin. k 3.3µ A 58k 22k RF_M RF_O 32 3 C P 36 ip VA k B P2 37 ip2 VC P IV AMP 58k VB k VC RF SUMMING AMP VC P2 IV AMP The low frequency component of the RFO output voltage is VRFO = 2.2 (VA + VB) = 27.6kΩ (ip + ip2). 6

17 IFB IFB2 IFB3 IFB4 IFB5 IFB6 CA2542Q Focus rror Amplifier P2 B + P A + C VC VC R3 58k R2 58k VB P2 IV AMP VA P IV AMP R5 32k R4 32k R7 74k F AMP R6 74k 48 FO FI R9 k GN R k GN C 22p R 6k 6 F_M VC FOCUS PHAS COMPNSATION R8 k 5 F_O R k RIVR 32 25/STP RST : IFB to IFB6 ON VH VIN > VH L VIN < VH H FOH VC 23 SNS V VC 2 2 VL VIN FOL VIN > VL H VIN < VL L SNS SLCTOR 24 SNS2 VC The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and output current-voltage converted voltage of the photodiode (A + C B ). The FO output voltage: 74kΩ VFO = 32kΩ (VA VB) = 74kΩ 32kΩ {( 58kΩ ip) ( 58kΩ ip2)} = 35.4kΩ (ip2 ip) The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB to IFB6) ON and OFF. The 6-bit focus bias adjustment switches are controlled with commands. IFB to IFB6 are all ON after a reset. The voltage is varied by approximately 25 per step. 7

18 CA2542Q Focus error amplifier offset adjustment (when adjusting the IC offset) The offset adjustment is performed by comparing the FO when the focus servo is OFF with the reference level. The FO and reference level are compared by the window comparator, and the comparison results are output from SNS and SNS2. (ARSS 6 ) Adjust the offset so that SNS and SNS2 are both High. Set the reference level to the center ±2. 25 < 4 < 5 Reference level width Variable voltage per step Variable voltage per 2 steps Focus bias fine adjustment Fine adjustment is performed by turning the focus bias adjustment switches (IFB to IFB6) ON and OFF while monitoring a SP jitter meter with the microcomputer. The 6-bit focus bias adjustment switches are controlled with commands. When performing conventional focus bias adjustment Fix the focus bias adjustment switches to the desired settings. (for example, IFB6 ON) In this condition, adjust the focus bias by turning a volume connected to F_BIAS (Pin 4). 8

19 BAL BAL2 BAL3 BAL4 R6 75k R7 k R 56k R 27k R5 3k TOG TOG2 TOG3 TOG4 R7 2k R9 32k R2 5k R2 6.6k R22 3k CA2542Q Tracking rror Amplifier R23 k R24 5k C3.µ C4.µ F C2 2p VC F I-V AMP VC I-V AMP R2 26k C 2p VF VC R 26k V R5 3k R3 26k R4 6.8k R8 7k T AMP NORMAL R4 3k R9 7k R3 3k V R2 96k GAIN UP GAIN UP VC TGFL R6 96k TGFL NORMAL R R8 5k VC TO GN GN LPFI VC VH 2 VIN VIN > VH L VIN < VH H BALH BALL VL VIN > VL H 2 VIN < VL L SNS VC VIN > VH L SLCTOR VIN < VH H VH TGH 2 VC 5 VC VIN TGL VL VIN > VL H VIN < VL L SNS 23 SNS2 24 RST 2 CPU VC COMAN CONTROL ATA LT CLK The difference between I-V amplifier output V and F I-V amplifier output VF is taken and output from TO. The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at the I-V amplifier. I-V AMP feedback resistance = R + R4 + F I-V AMP feedback resistance = R2 + R5 + R R4 R R2 R5 R3 = 43kΩ Vary the combined resistance value of the I-V amplifier's feedback resistance by using the balance adjustment switches (BAL to BAL4). The gain adjustment is performed by resistance dividing the T AMP output by the gain adjustment switches (TOG to TOG4). The balance and gain adjustment switches are controlled with commands. Set the cut-off frequency of the external LPF between Hz to Hz. 9

20 CA2542Q Balance adjustment The balance adjustment is performed by passing the tracking error signal (TO signal) through the external LPF, extracting the offset C, and comparing it to the reference level. However, the TO signal frequency distribution ranges form C to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete offset C can not be extracted. To extract it, monitor the TO signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the LPF. Use the C.OUT output to check this frequency. The offset C and reference level are compared by the window comparator. The comparison signal is output from the SNS and SNS2 pins. (ARSS 6 ) Adjust the balance so that the SNS and SNS2 pins are both High. VIN < VL < VH VL < VIN < VH VL < VH < VIN SNS pin BALH H H L SNS2 pin BALL L H H VH: High level threshold value VIN: Window comparator input signal VL: Low level threshold value Gain adjustment Gain adjustment is performed by passing the TO signal through the HPF and comparing the AC component to the reference level. The AC component is generated by taking the difference between T and the offset C input to Pin 42. The AC component and reference level are compared by the window comparator. The comparison signal is output from the SNS and SNS2 pins. (ARSS 6 ) The comparison signal is as follows. () (2) (3) VH VL VIN SNS pin TGH H H SNS pin TGL L The gain should be adjusted so that the SNS and SNS2 pins are as shown in status (2). When the TO signal level is low and TGH (SNS pin) does not go Low, the gain should be raised with the TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL (SNS2 pin). 2

21 RFTC CA2542Q APC & Laser Power Control R 22 C2 µ L 34 R6 k L µh 3 P 35 R8 k R 56k LON C µ L R2 5 P R3 R4 k R5 55k R k R2 56k VRF GN V RF_I 3 V.Vpp VL R4 2.5k V LPC ON/OFF 5%/7% C3.µ RF_O 3.47V RF R7 39.5k R9 23.5k 67 VC VC 33 R3 M C4 µ APC When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. The APC circuit is used to maintain the optical power output at a constant level. The laser diode current is controlled according to the monitor photodiode output. V V Laser power control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR. This signal is then compared with the reference level. The laser power is controlled by attaching an offset to VL according to the results of comparison with the reference level. Set the reference level to 67. (center voltage reference) LPC ON/OFF and L ON/OFF control is performed with commands. The laser power control limit can also be switched between ±5% and ±7% with commands. LPC OFF ON ON LPCL ±5% ±7% VL variable range Approximately.27V Approximately.27V ± 625 Approximately.27V ± 28 2

22 CA2542Q Center Voltage Generation Circuit (The figure below shows a single voltage application; Connect to GN for dual power supplies.) Maximum current is approximately ±3mA. Output impedance is approximately 5Ω. 3k VC 5 VC 46 3k V GN Connected internally to the V pin. 22

23 CA2542Q Focus Servo 9k k k.22µ FZC 47 22p.µ FO 48 F FI k 2 FFCT 5k 75k FCT FS3 FS4 FZC 68k SNS SLCTOR Focus phase Compensation k 23 F_O 5 SNS FOCUS COIL 68k.µ 3 FG 4k 5k µ 22µ F_M 6 k IST 6 6k FS2 FLB FST 4 7 5k SRCH FS Charge up.µ 5k.5µ 4.7µ The above figure shows a block diagram of the focus servo. Ordinarily the F signal is input to the focus phase compensation circuit through a 68kΩ resistance; however, when FCT is detected, the F signal is switched to pass through a low-pass filter formed by the internal kω resistance and the capacitance connected to Pin 2. When this FCT prevention circuit is not used, leave Pin 2 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 4 and GN is a time constant to boost the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately.2khz when a resistance of 5kΩ is connected to Pin. The focus search height is approximately ±.Vp-p when using the constants indicated in the above figure. This height is inversely proportional to the resistance connected between Pin 7 and V. However, changing this resistance also changes the height of the track jump and sled kick as well. The FZC comparator inverted input is set to 5% of Vcc and VC (Pin 46); (Vcc VC) 5%. 5kΩ resistance is recommended for Pin. 23

24 33k 47p.µ 2k.5µ.µ.µ CA2542Q Tracking and Sled Servo 4 TO T + GAIN WINOW COMPARATOR TGH TGL SNS SLCTOR SNS2 SNS k 5k BUFFR AMP 42 LPFI BALANC WINOW COMPARATOR BALH BALL T FCT TM 68k TG SL_O 5 SL MOTOR M.47µ 47k k TFCT 45 ATSC 43 k k k 68k ATSC 66p TM6 TM5 22µA 22µA TM2 SL_M 4 SL_P 3 8.2k 3.3µ.22µ TZC µ 9 TGU TG2 TZC 47k TG2 k 2k Tracking Phase Compensation TM4 TM3 k TM7 µa µa 9k TA_M TA_O 2 82k k 22µ 5k TRACKING COIL FST 5k.5µ The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately.2khz when a 5kΩ resistance is connected to Pin. In the CA2542Q, TG and TG2 are inter-linked switches. To jump tracks in FW and RV directions, turn TM3 or TM4 ON. uring this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin. To be more specific, Track jump peak voltage = TM3 (or TM4) current feedback resistance value The FW and RV sled kick is performed by turning TM5 or TM6 ON. uring this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 4; Sled kick peak voltage = TM5 (or TM6) current feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 6 and V. When this resistance is 6kΩ : TM3 (or TM4) = ±µa, and TM5 (or TM6) = ±22µA. As is the case with the F signal, the T signal is switched to pass through a low-pass filter formed by the internal resistance (kω) and the capacitance connected to Pin

25 CA2542Q The IST pin is used to connect external resistance. This external resistance sets the current which determines the focus search, track jump, and sled kick heights. Focus search current I I2 VBG I = R 2 (VBG: approximately.27v) FS I2 = 2I Track jump current (TM3 and TM4 current) VBG I = R 2 Sled kick current (TM5 and TM6 current, when = = during $ commands) I = VBG R Use external resistance of between 3kΩ to 24kΩ. Using external resistance outside this range may cause oscillation. 25

26 CA2542Q Focus OK Circuit RF C5.µ RF_O 3 3 RF_I VG 54k 2k 25 FOK 5k 92k.63V FOCUS OK AMP FOCUS OK COMPARATOR The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 3 from Pin 3 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output is inverted when VRFI VRFO.37V. Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to.µf selected, the fc is equal to khz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. efect circuit After inversion, RF_O signal is bottom held by means of the long and short time constants. The long timeconstant bottom hold keeps the mirror level prior to the defect. The short time-constant bottom hold responds to a disc mirror defect in excess of.ms, and this is defferentiated and level-shifted through the AC coupling circuit. The long and short time-constant signals are compared to generate at mirror defect detection signal. CC 27.33µ 26 CC2 RF_O 3 a 2 b FCT AMP c d FLIP FLOP e FCT2 FCT FCT SW SNS SLCTOR SNS2 SNS 28 CB.µ FCT BOTTOM HOL FCT COMPARATOR f INTRRUPTION COMPARATOR a RFO b FCT AMP c e f BOTTOM HOL () solid line FCT INT d H L H L BOTTOM HOL (2) solid line 26

27 CA2542Q Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time constant can follow a 3kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. RF_O 3 3 RF_I RF.4 G MIRROR AMP PAK & BOTTOM HOL H I J MIRROR HOL AMP MIRR K SNS SLCTOR.33µ 29 CP 24 SNS2 MIRROR COMPARATOR RF_O V G (RF_I) V H (PAK HOL) V I (BOTTOM HOL) V J K (MIRROR HOL) MIRR H L The C playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal. 27

28 CA2542Q SNS Selector FZC HIGH-Z FCT FCT2 TZC MIRR BALH TGH BALL 23 SNS 24 TGL SNS2 FOH FOL ATSC What is output to the SNS and SNS2 pins varies according to the address input to the ATA pin. ATA (Pin 2) 8-bit transfer ARSS ATA SNS SNS FZC H (HIGH-Z) FCT FCT2 TZC MIRR H (HIGH-Z) H (HIGH-Z) ATA (Pin 2) 2-bit transfer ARSS ATA SNS SNS BALH BALL TGH TGL FOH FOL ATSC H (HIGH-Z) Notes) 2-bit transfer should be performed during $3 commands. When 8 bits are transferred, SNS and SNS2 are switched according to the 3 and 2 data. SNS and SNS2 are switched without latching. 28

29 CA2542Q Commands The input data to operate this IC is configured as 8-bit/2-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $, where is a hexadecimal numeral between and F/$ for 2-bit. Commands for the CA2542Q can be broadly divided into four groups ranging in value from $, $, $2, $3.. $ (FZC at SNS pin (Pin 23), H (Hi-Z) at SNS2 pin (Pin 24)) These commands are related to focus servo control. The bit configuration is as shown below FS4 FS2 FS Four focus related switches exist: FS, FS2, FS4 and FCT. $ When FS =, Pin 7 is charged to (22µA µa) 5kΩ =.55V. If, in addition, FS2 =, this voltage is no longer transferred, and the output at Pin 5 becomes V. $2 From the state described above, the only FS2 becomes. When this occurs, a negative signal is output to Pin 5. This voltage level is obtained by equation below. resistance between Pins 5 and 6 (22µA µa) 5kΩ... quation 5kΩ The SRCH OWN speed can be increased by the charge up circuit. $3 From the state described above, FS becomes, and a current source of +22µA is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as shown in Fig. below. V Fig.. Voltage at Pin 7 when FS goes from This time constant is obtained with the 5kΩ resistance and an external capacitor. By alternating the commands between $2 and $3, the focus search voltage can be constructed. (Fig. 2) V $ Fig. 2. Constructing the search voltage by alternating between $2 and $3. (Voltage at Pin 5) 29

30 CA2542Q -. FS4 This switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $ $8 Focus off Focus on -2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 5) is changing from negative to positive; and c) The focus S-curve is varying as shown below. A t Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANed with the focus OK signal. In this IC, FZC (Focus Zero Cross) signal is output from the SNS pin (Pin 23) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart. (2ms) (2ms) $2 ($) $3 $8 rive voltage Focus error The broken lines in the figure indicate the voltage assuming the signal is not in focus. SNS (FZC) The instant when the signal is brought into focus. Focus OK Fig. 4. Focus ON timing chart 3

31 CA2542Q Note that the time from the High to Low transition of FZC to the time command $8 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A. FZC? NO Transfer $8 YS F. OK? NO F. OK? NO YS YS Transfer $8 FZC? NO YS Latch Latch (A) (B) Fig. 5. Poor and good software command sequences 2. $ (FCT at SNS pin (Pin 23), FCT2 at SNS2 pin (Pin 24)) These commands deal with switching TG/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows: TG, TG2 Break Sled kick circuit height ON/OFF ON/OFF Sled kick height (PS) (PS) Relative value ± ±2 ±3 ±4 TG, TG2, TM7 The purpose of TG and TG2 is to switch the tracking servo gain Up/Normal. TG and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely -track jump has been performed actually though a -track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a or -track jump. For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 8 out-of-phase to cut the unneeded portion of the tracking error and apply braking. 3

32 CA2542Q RF_I TZC 3 44 [ A] dge etection [ ] Waveform Shaping [ B] [ ] Waveform Shaping dge etection (MIRR) [ C] (Latch) [ F] 2 [ G] Q BRK CK TM7 Low: open High: make [ H] CA2542Q Fig. 6. TM7 movement during braking operation From inner to outer track From outer to inner track [ A] [ B] [ C] ("MIRR") [ ] [ ] ("TZC") [ F] [ G] [ H] V Braking is applied from here. Fig. 7. Internal waveform 3. $2 (TZC at SNS pin (Pin 23), MIRR at SNS2 pin (Pin 24)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations Tracking Sled control control off off Servo ON Servo ON F-JUMP F-FAST FORWAR R-JUMP R-FAST FORWAR TM, TM3, TM4, TM2, TM5, TM6 32

33 CA2542Q 4. $3 These commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. In the initial resetting state, BAL to BAL4 switches and TOG to TOG4 switches are ON. Also, the IFB to 6 switches are ON. Balance adjustment The balance adjustment switches BAL to BAL4 can be controlled by setting 6 = and 7 =. The switches are set using to 3. At this time, SNS outputs BALH and SNS2 outputs BALL. ata is set by specifying switch conditions to 3 and sending a latch pulse with 6 = and 7 =. Sending a latch pulse with 6, 7 does not change the balance switch settings. START BAL to BAL4 Switch Control C.OUT is the frequency high enough? YS NO SNS/2 Balance OK? Adjustment Completed Balance adjustment Gain adjustment The gain adjustment switches TOG to TOG4 can be controlled by setting 6 = and 7 =. These switches are set using to 3. At this time, SNS outputs TGH and SNS2 outputs TGL. In a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions to 3 and sending a latch pulse with 6 = and 7 =. START TOG to TOG4 Switch control NO SNS/2 GAIN OK? YS Adjustment Completed Gain adjustment 33

34 CA2542Q Focus bias adjustment The focus bias adjustment switches IFB to 6 can be controlled by setting 6 = and 7 =. The switches are set using to 5. At this time, SNS outputs FOH and SNS2 outputs FOL. ata is set by specifying switch conditions to 5 and sending a latch pulse with 6 = and 7 =. START IFB to 6 Switch Control NO SNS/2 BIAS OK? YS Adjustment Completed Focus bias adjustment method TGFL The tracking gain can be switched by setting 5 with 6 = and 7 =. The tracking gain is GAIN UP with 5 = and NORMAL GAIN with 5 =. The TO signal level can be made higher by approximately 6 for GAIN UP. When the TO signal level is low and TGH (SNS pin) does not go Low during tracking adjustment, the gain should be raised with the TGFL command for adjustment. LPC The laser power control circuit can be turned ON and OFF by setting with 6 = and 7 =. The circuit is ON with = and OFF with =. LPCL The laser power control limit can be switched between ±7% and ±5% by setting with 6 = and 7 =. The control limit is ±7% with = and ±5% with =. LON The laser diode can be turned ON and OFF by setting 2 with 6 = and 7 =. The laser diode is ON with 2 = and OFF with 2 =. 34

35 CA2542Q ATSC The anti-shock function can be controlled by setting 3 with 6 = and 7 =. This function is disabled with 3 = and enabled with 3 =. At this time, SNS outputs ATSC. ven if ATSC is disabled, ATSC is output to SNS. When an anti-shock signal is generated during the enable status, TG and TG2 switch to GAIN UP mode. (In the Block iagram, TG is set to the side and TG2 is OFF. ven if TG and TG2 are NORMAL mode, they switch to GAIN UP mode in conjunction with ATSC.) When the anti-shock function is not used, Pin 43 (ATSC) should be connected to VC. RFCT2 FCT2 can be reset by setting 4 with 6 = and 7 =. FCT2 is reset with 4 =. After a reset, High is held when FCT rises. uring $ commands, FCT2 is output from SNS2. FCT2 operates even if FCT is disabled. Whether or not FCT rises at the proper timing for the microcomputer can also be confirmed. INT The interruption (scratched disc) countermeasure circuit can be set to operating status by setting 5 with 6 = and 7 =. This circuit is enabled when 5 = and disabled when 5 =. ven if FCT does not rise, this circuit is effective for scratched discs which cause MIRR to rise. When MIRR rises, the FCT switch is routed through the low-pass filter. The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC) ven if FCT is disabled, the interruption countermeasure circuit operates when INT is enabled. 35

36 CA2542Q CPU Serial Interface Timing Chart ATA twck twck tsu th CLK /fck tc LT t twl ( = 3.V) Item Symbol Min. Typ. Max. Unit Clock frequency fck MHz Clock pulse width fwck 5 ns Setup time tsu 5 ns Hold time th 5 ns elay time t 5 ns Latch pulse width twl ns ata transfer interval tc ns Low level input voltage VIL. ( V). V High level input voltage VIH ( V).9 V 36

37 CA2542Q System Control Item ARSS FOCUS CONTROL TRACKING CONTROL TRACKING SL MO TRACKING MO 3 2 OFF ON FW JUMP RV JUMP ATA (Pin 2) 8-bit transfer ATA 3 2 FS4 Focus = ON = OFF FS2 SRCH ON = ON = OFF FS2 SRCH UP = UP = OWN TG, TG2 = GAIN UP = NORMAL BRAK = NABL = ISABL SL KICK + 2 SL KICK + TRACKING MO SL MO 2 2 SL MO OFF ON FW MOV RV MOV SNS FZC FCT TZC SNS2 H (HIGH-Z) FCT2 MIRR 37

38 CA2542Q ATA (Pin 2) 2-bit transfer Item ARSS ATA -F BALANC TRACKING GAIN FOCUS BIAS FCT = ISABL = NABL TGFL = GAIN UP = NORMAL IFB6 = OFF = ON INT IFB5 = OFF = ON RFCT2 BAL4 = OFF = ON TOG4 = OFF = ON IFB4 = OFF = ON ATSC BAL3 = OFF = ON TOG3 = OFF = ON IFB3 = OFF = ON LON BAL2 = OFF = ON TOG2 = OFF = ON IFB2 = OFF = ON LPCL BAL = OFF = ON TOG = OFF = ON IFB = OFF = ON LPC Others = NABL = ISABL = RST = NORMAL = ISABL = NABL = ON = OFF = ±5% = ±7% = ON = OFF Notes) When ATSC is enabled, even if TG and TG2 are NORMAL mode, TG and TG2 switch to GAIN UP mode in conjunction with ATSC. INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC) When reset SNS = FZC SNS2 = High (Hi-Z) RFCT2 = (Reset) IFB to IFB6 = (switch ON) TOG to TOG4 = (switch ON) BAL to BAL4 = (switch ON) Other data is "". SNS BALH TGH FOH ATSC SNS2 BALL TGL FOL H (HIGH-Z) 38

39 CA2542Q Serial ata Truth Table Serial ata H Functions FOCUS CONTROL FS4 FS2 FS $ $ $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $ $ $F Notes) FS : OFF : ON FS2 : ON : OFF FS4 In the Block iagram: :SW side :SW side BRAK SL KICK TRACKING CONTROL $ $ $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $ $ $F TG TG2 Fig. 6 2 KICK +2 KICK + Notes) TG In the Block iagram: :SW side :SW side TG2 : OFF : ON BRAK When 2 in Fig. 6 is: : : Sled kick height Relative value ± ±2 ±3 ±4 39

40 CA2542Q Serial ata H Function TRACKING/SL MO TM6 TM5 TM4 TM3 TM2 TM $2 $2 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2 $2 $2F Notes) TM/TM2 In the Block iagram: :SW side :SW side TM3/TM4/TM5/TM6 : ON : OFF 4

41 4 CA2542Q Serial ata $3 $3 $3 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3 $3 $3F $3 $3 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3 $3 $3F $32 $32 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32 $32 $32F H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

42 42 CA2542Q Serial ata $3 $33 $33 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33 $33 $33F $34 $34 $342 $343 $344 $345 $346 $347 $348 $349 $34A $34B $34C $34 $34 $34F $35 $35 $352 $353 $354 $355 $356 $357 $358 $359 $35A $35B $35C $35 $35 $35F H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

43 43 CA2542Q Serial ata $3 $36 $36 $362 $363 $364 $365 $366 $367 $368 $369 $36A $36B $36C $36 $36 $36F $37 $37 $372 $373 $374 $375 $376 $377 $378 $379 $37A $37B $37C $37 $37 $37F $38 $38 $382 $383 $384 $385 $386 $387 $388 $389 $38A $38B $38C $38 $38 $38F H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

44 44 CA2542Q Serial ata $3 $39 $39 $392 $393 $394 $395 $396 $397 $398 $399 $39A $39B $39C $39 $39 $39F $3A $3A $3A2 $3A3 $3A4 $3A5 $3A6 $3A7 $3A8 $3A9 $3AA $3AB $3AC $3A $3A $3AF $3B $3B $3B2 $3B3 $3B4 $3B5 $3B6 $3B7 $3B8 $3B9 $3BA $3BB $3BC $3B $3B $3BF H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

45 45 CA2542Q Serial ata $3 $3C $3C $3C2 $3C3 $3C4 $3C5 $3C6 $3C7 $3C8 $3C9 $3CA $3CB $3CC $3C $3C $3CF $3 $3 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3 $3 $3F $3 $3 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3 $3 $3F H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

46 Notes) means OFF and means ON for TOG SW and BAL SW. These are not equal to the setting values of each bit for serial data. "" in the Truth Table indicates that the status does not change. TGFL In the Block iagram: :SW side :SW side ATSC : enable/: disable FCT : enable/: disable 46 CA2542Q Serial ata $3 $3F $3F $3F2 $3F3 $3F4 $3F5 $3F6 $3F7 $3F8 $3F9 $3FA $3FB $3FC $3F $3F $3FF H BAL SW TOG SW IFB SW INT RF CT2 ATSC LON LPCL LPC FCT TGFL

47 CA2542Q Initial State (resetting state) Item FOCUS CONTROL ARSS ATA H $ TRACKING CONTROL $ TRACKING SL MO $2 Item ARSS ATA 3 2 H -F BALANC $3 TRACKING GAIN $34 FOCUS BIAS $38 Others $3 The above data means the following operation modes. FOCUS CONTROL : FOCUS OFF, FOCUS SARCH OFF, FOCUS SACH OWN TRACKING CONTROL : TG-TG2 NORMAL, BRAK ISABL, SL KICK relative height value ± TRACKING SL MO : TRACKING OFF, SL OFF -F BALANC : BAL to BAL4 = (switch ON). FCT NABL TRACKING GAIN : TOG to TOG4 = (switch ON), TGFL NORMAL FOCUS BIAS : IFB to IFB6 = (switch ON) Others : INT ISABL, FCT2 RST, ATSC NABL, LON OFF, LPCL ±7%, LPC OFF 47

48 CA2542Q Notes on Operation. Focus OK circuit ) Refer to the "escription of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF. 2) The equivalent circuit for the output pin (FOK) is shown in the diagram below. 2k FOK 4k 25 The FOK and comparator output are as follows: RL Output voltage High : VFOKH near Vcc k Output voltage Low : VFOKL Vsat (NPN) + V V V 2. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately Focus/Tracking internal phase compensation and reference design material Item S Measurement pin Conditions Typ. Unit FCS.2kHz gain.2khz phase CFLB =.µf CFG =.µf deg.2khz gain 25 3 TRK.2kHz phase 2.7kHz gain CTGU =.µf deg 2.7kHz phase deg 4. Laser Poser Control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The laser life is shortened by increasing the laser power when the less light is reflected from the disc. It is recommended that the typical laser power value is set lower to maintain the laser life. Take care of the laser maximum ratings when using the laser power control circuit. 48

49 .9 ± CA2542Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 5.3 ± ±.2 M PACKAG STRUCTUR PACKAG MATRIAL POY RSIN SONY CO IAJ CO QFP-48P-L4 QFP48-P-22-B LA TRATMNT LA MATRIAL SOLR / PALLAIUM PLATING COPPR / 42 ALLOY JC CO PACKAG WIGHT.7g 49