RF Signal Processing Servo Amplifier for CD players

Transcription

1 RF Signal Processing Servo Amplifier for CD players Description The CXA782CQ/CR is a bipolar IC with built-in RF signal processing and various servo ICs. A CD player servo can be configured by using this IC, DSP and driver. CXA782CQ 48 pin QFP (Plastic) CXA782CR 48 pin LQFP (Plastic) Features Low operating voltage (VCC VEE = 3.0 to.0v) Low power consumption (39mW, VCC = 3.0V) Supports pickup of either current output, voltage output Automatic adjustment comparator for tracking balance gain Single power supply and positive/negative dual power supplies Applications RF I-V amplifier, RF amplifier Focus and tracking error amplifier APC circuit Mirror detection circuit Defect detection and prevention circuits Focus servo control Tracking servo control Sled servo control Comparators of tracking adjustment for balance and gain Absolute Maximum Ratings (Ta = 25 C) Supply voltage VCC 2 V perating temperature Topr 20 to +75 C Storage temperature Tstg 65 to +50 C Allowable power dissipation PD 833 (CXA782CQ) mw 457 (CXA782CR) mw Recommended perating Condition perating supply voltage VCC VEE 3.0 to.0 V Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. E95908C78

2 FE FEI FDFCT FGD FLB FE_ FE_M SRCH TGU TG2 FSET TA_M F SET TG TG2 TG3 BAL BAL2 BAL3 PHD2 PHD PHD LD RF_M RF_ RF_I CP CB CC CC2 FK CXA782CQ/CR Block Diagram APC LEVEL S I IL 24 SENS TTL 23 C.UT RF IV AMP FK MIRR DFCT 22 XRST TTL 2 DATA FE_BIAS 37 RF IV AMP2 TTL I IL DATA REGISTER INPUT SHIFT REGISTER ADRESS.DECDER I IL 20 XLT F 38 FE AMP I IL UTPUT DECDER 9 CLK F IV AMP E EI E IV AMP FZC CMP TG to 3 BAL to 3 FS to 4 TG to 2 TM to 7 PS to 4 8 TE AMP HPF CMP LPF CMP TRACKING PHASE CMPENSATIN I SET 7 ISET VEE 4 TE 42 LPFI 43 TEI 44 ATSC 45 WINDW CMP. TZC CMP DFCT TM TG FCS PHASE CMPENSATIN FS TM6 TM5 TM4 TM3 TM7 TM SL_ SL_M SL_P TA_ TZC 46 TDFCT 47 VC 48 ATSC DFCT FS4 FS2 TG The switch state in Block Diagram is for initial resetting. Switch turns to side for and to side for 0 in Serial Data Truth Table. DFCT switch turns to side when defect signal generates for DEFECT = E in Serial Data Truth Table. TG switch turns to side and TG2 switch is left open when TG and TG2 (address : D3) is. 2

3 Pin Description Pin No. Symbol I/ Equivalent circuit Description 25p FE 300µ 74k 5k 9k Focus error amplifier output. Connected internally to the FZC comparator input. 2 FEI I 2 Focus error input. 3 FDFCT I 3 Capacitor connection pin for defect time constant. 4 FGD I 4 68k 30k 20µ Ground this pin through a capacitor when decreasing the focus servo high-frequency gain. 5 FLB I 5 40k External time constant setting pin for increasing the focus servo lowfrequency. 6 FE_ Focus drive output. 3 TA_ 6 3 Tracking drive output. 6 6 SL_ 250µ Sled drive output. 90k 7 FE_M I 7 Focus amplifier inverted input. 50k 3

4 Pin No. Symbol I/ Equivalent circuit Description 8 SRCH I 8 50k µ External time constant setting pin for generating focus servo waveform. 9 TGU I 9 20k 82k External time constant setting pin for switching tracking high-frequency gain. 0 TG2 I 0 470k 2µ External time constant setting pin for switching tracking high-frequency gain. FSET I k 5k 5k High cut-off frequency setting pin for focus and tracking phase compensation amplifier. 2 TA_M I 2 Tracking amplifier inverted input. µ 4 SL_P I 4 Sled amplifier non-inverted input. 5 SL_M I 5 Sled amplifier inverted input. 22µ 4

5 Pin No. Symbol I/ Equivalent circuit Description 7 ISET I 7 Setting pin for Focus search, Track jump, and Sled kick current. 9 CLK I 20 XLT I 2 DATA I 22 XRST I k 5µ Serial data transfer clock input from CPU. (no pull-up resistance) Latch input from CPU. (no pull-up resistance) Serial data input from CPU. (no pull-up resistance) Reset input; resets at Low. (no pull-up resistance) 23 C. UT 23 20k Track number count signal output. 24 SENS 24 utputs FZC, DFCT, TZC, gain, balance, and others according to the command from CPU. 20k 25 FK 25 40k Focus K comparator output. 26 CC2 I Input for the DEFECT bottom hold output with capacitance coupled. 27 CC DEFECT bottom hold output CB I Connection pin for DEFECT bottom hold capacitor. 5

6 Pin No. Symbol I/ Equivalent circuit Description 29 CP I 29 Connection pin for MIRR hold capacitor. MIRR comparator non-inverted input. 30 RF_I I Input for the RF summing amplifier output with capacitance coupled. 3 RF_ 30 RF sunning amplifier output. Eye-pattern check point. 32 RF_M I 3 32 RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RF pin. k 33 LD 33 APC amplifier output. 7µ 34 PHD I 34 APC amplifier input PHD PHD2 I I µ.6k RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins. 6

7 Pin No. Symbol I/ Equivalent circuit Description 32k 37 FE_BIAS I 37 64k Bias adjustment of focus error amplifier. 25p 8µ 2p F E I I k 0µ 53 F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E. 40 EI k 6.8k 02k 57k 20.3k 28k I-V amplifier E gain adjustment. (When not using automatic balance adjustment) 42 TE 42 2k 23k k 4.8k 50k Tracking error amplifier output. E-F signal is output. 50k 43 LPFI I 43 Comparator input for balance adjustment. (Input from TE through LPF) 7

8 Pin No. Symbol I/ Equivalent circuit Description 44 TEI I 44 Tracking error input. 47 TDFCT I 47 Capacitor connection pin for defect time constant. k 45 ATSC I 45 Window comparator input for ATSC detection. k 46 TZC I 46 Tracking zero-cross comparator input. 75k 48 VC (VCC + VEE)/2 DC voltage output. VC 8

9 Electrical Characteristics Item T Current consumption T2 Current consumption 2 T3 ffset TE amplifier FE amplifier RF amplifier T4 T5 T6 Voltage gain Max. output voltage-high Max. output voltage-low T7 ffset T8 Voltage gain T9 T0 T Voltage gain Voltage gain difference Max. output voltage-high T2 Max. output voltage-low T3 ffset T4 Voltage gain F0 T5 Voltage gain F T6 T7 Voltage gain F2 Voltage gain F3 T8 Voltage gain E0 T9 Voltage gain E T20 Voltage gain E2 SW conditions SD RST 3F 3E 3D 3B Measurement pin (VCC =.5V, VEE =.5V, Ta = 25 C) Measurement conditions Ratings Min. Typ. Max. Unit ma ma khz input ratio V = 00DC.2.3 V V = 00DC V V = khz I/ ratio V = khz I/ ratio V = 00DC.0.3 V V = 00DC.3.0 V V = khz TG, 2, 3: FF V = khz TG: N Reference to F0 V = khz TG2: N Reference to F0 V = khz TG3: N Reference to F0 V = khz TG, 2, 3: FF V = khz BAL: N Reference to E0 V = khz BAL2: N Reference to E0 9

10 V = khz BAL3: N Reference to E0 3F V = VDC BAL2: N F V = VDC BAL2: N V2 = V2 = V2 = mA sink T29 + T8 (or T9) utput gain difference between 00 SD = 00 and SD = V = 200DC V = 200DC Pin threshold (preliminary) T37 + T utput gain difference between SD = 20 and SD = V = 0.5VDC.0.3 V V V V V TRK servo FCS servo APC TE amplifier T2 T22 T23 T24 T25 T26 T27 T28 T29 T30 T3 T32 T33 T34 T35 T36 T37 T38 T39 T40 Item Voltage gain E3 Max. output voltage-high Max. output voltage-low utput voltage utput voltage 2 utput voltage 3 utput voltage 4 Center amplifier output offset DC voltage gain FCS total gain Feed through Max. output voltage-high Max. output voltage-low Search voltage ( ) Search voltage (+) FZC threshold DC voltage gain TRK total gain Feed through Max. output voltage-high SW conditions Ratings Measurement SD Measurement conditions pin Min. Typ. Max. Unit 0

11 25 3 V = +0.5VDC.3.0 2C utput gain difference between 20 SD = 20 and SD = V = +0.4VDC.0.3 V = 0.4VDC Measures at C. UT pin. 30 Measures at C. UT pin. 0.3 Measures at C. UT pin Measures at SENS pin. Measures at SENS pin. 2.5 Measures at SENS pin. 0.5 Measures at SENS pin..8 V V V khz Vp-p Vp-p khz khz Vp-p Vp-p DEFECT MIRR Sled TRK Servo T4 T42 T43 T44 T45 T46 T47 T48 T49 T50 T5 T52 T53 T54 T55 T56 T57 T58 T59 T60 T6 T62 Item Max. output voltage-low Jump output voltage ( ) Jump output voltage (+) ATSC threshold ( ) ATSC threshold (+) TZC threshold BAL CMP threshold GAIN CMP threshold FK threshold DC open gain Feed through Max. output voltage-high Max. output voltage-low Kick voltage ( ) Kick voltage (+) Max. operating frequency Min. input operating voltage Max. input operating voltage Min. operating frequency Max. operating frequency Min. input operating voltage Max. input operating voltage SW conditions Ratings Measurement SD Measurement conditions pin Min. Typ. Max. Unit

12 5 0.05µ S0 0.µ 47k S3 FE FEI FDFCT FGD FLB FE_ 200k FE_M SRCH TGU TG2 FSET TA_M 60k PD2 PD PD LD RF_M RF_ RF_I CP CB CC CC2 FK S5 3000p 000p S2 S S7 S6 CXA782CQ/CR Electrical Characteristics Measurement Circuit VEE V2 3300p 22k S3 S4 390k 390k FE_BIAS F E EI 24 SENS C. UT 23 XRST 22 DATA 2 XRST DATA VEE A 4 VEE XLT 20 XLT V AC DC V S8 S5 S6 S7 S8 0.µ S9 42 TE 43 LPFI TEI ATSC TZC TDFCT VC CLK 9 8 ISET 7 SL_ 6 SL_M 5 SL_P 4 TA_ 3 CLK A 240k VEE 3k S4 5.k S2 S 200k 2

13 Driver 2200p 0.µ µ 0.µ 680k 0.µ 4.7µ 82k FE FEI FDFCT FGD FLB FE FE M SRCH TGU TG2 FSET TA M 8.2k 0.022µ 0.05µ 0.0µ 0.0µ PD2 PD PD LD RF M RF RF I CP CB CC CC2 FK 0.033µ 0.0µ MICR CMPUTER 00µ/6.3V Driver 2200p 0.µ µ 0.µ 680k 0.µ 4.7µ 82k FE FEI FDFCT FGD FLB FE FE M SRCH TGU TG2 FSET TA M 8.2k 0.022µ 0.05µ 0.0µ 0.0µ PD2 PD PD LD RF M RF RF I CP CB CC CC2 FK 0.033µ 0.0µ MICR CMPUTER 00µ/6.3V CXA782CQ/CR Application Circuit (Dual ±5V power supplies) k µ/0.3v µ/6.3v 0 A 0µH C B VEE k 0.0µ 0.033µ D F 47k 37 FE_BIAS VEE 38 F 24 SENS C. UT 23 DSP DSP E 39 E XRST 22 MICR CMPUTER 40 EI DATA 2 DSP 4 VEE XLT 20 DSP VEE 42 TE 50k 43 LPFI 44 TEI BPF 45 ATSC CLK 9 8 ISET 7 SL 6 DSP 20k VEE Driver 46 TZC SL M 5 47 TDFCT 0.µ 48 VC 0µ k 0.033µ SL P 4 TA 3 3.3µ 22µ 5k Driver Application Circuit (Single +3V power supply) k µ/0.3v µ/6.3v 0 A 0µH C B k 0.0µ 0.033µ D F 47k 37 FE_BIAS 38 F 24 SENS C. UT 23 DSP DSP E 39 E XRST 22 MICR CMPUTER 40 EI DATA 2 DSP 4 VEE XLT 20 DSP 42 TE 50k 43 LPFI 44 TEI CLK 9 8 ISET 7 20k DSP BPF 45 ATSC SL 6 Driver 46 TZC SL M 5 0µ 47 TDFCT SL P 4 0.µ TA 48 VC 3 0µ k 0.033µ 3.3µ 22µ 5k Driver Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 3

14 Description of Functions RF Amplifier The photo diode currents input to the input pins (PD and PD2) are each I-V converted via a 58kΩ equivalent resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode (A + B + C + D) current-voltage converted voltage is output to the RF pin. An eye-pattern check can be performed at this pin. k 3.3µ A 58k 22k RF_M RF_ 32 3 C PD 35 ipd VA B D PD2 36 ipd2 VC PD IV AMP 58k VB VC RF SUMMING AMP VC PD2 IV AMP The low frequency component of the RF output voltage is VRF = 2.2 (VA + VB) = 27.6kΩ (ipd + ipd2). Focus Error Amplifier The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and output current-voltage converted voltage of the photo diode (A + C B D). 25p 74k (B + D) (A + C) VB VA 32k 32k 25p 87k 64k FE AMP FE VC 37 FE_BIAS VEE 47k VCC The FE output voltage (low frequency) is VFE = 5.4 (VA VB) = (ipd2 ipd) 35kΩ. Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC. 4

15 BAL BAL2 BAL3 RE3 20.3k 02k 57k 28k 6.8k RE2 TG TG2 TG3 26k RF3 22k 4.8k 96k 2k 3k RF2 CXA782CQ/CR Tracking Error Amplifier The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V amplifiers. k 3.3µ if F 38 RF 260k 2p VF 30k TE AMP 96k F I-V AMP VC 30k 42 TE RE VC VC ie E k 2p VE VC E I-V AMP VC VC 40 EI The CXA782 tracking block has built-in circuits for balance and gain adjustments to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at E I-V AMP. F I-V AMP feedback resistance = RF + RF2 + E I-V AMP feedback resistance = RE + RE2 + RF x RF2 RF3 RE x RE2 RE3 = 403kΩ Vary the value of RE3 in the formula above by using the balance adjustment switches (BAL to BAL3). For the gain adjustment, the TE AMP output is resistance-divided by the gain adjustment switches (TG to TG3), and it is output at Pin 42. These balance and gain adjustment switches are controlled through software commands. 5

16 0.0µ 0.0µ CXA782CQ/CR Tracking Automatic Adjustment for Gain/Balance µ-cn TZC DFCT FZC 42 TE 50k LPF 43 LPFI BUFFER AMP LPF HPF SENS C. UT Balance K Gain K Frequency check + Balance Gain Resistance switching The CXA782 has balance control, gain control, and comparator circuits required to perform tracking automatic adjustment. LPF is set externally at approximately 00Hz. Balance adjustment This adjustment is performed by routing the tracking error signal (TE signal) through the LPF, extracting the offset DC, and comparing it to the reference level. However, the TE signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete DC offset can not be extracted. To extract it, monitor the TE signal frequency at all times, and perform adjustment only when, a frequency that can lower a sufficient gain appears on the LPF. Use the C. UT output to check this frequency. Gain adjustment This adjustment is performed by passing the TE signal through the HPF and comparing the AC component to the reference level. The HPF signal is implemented by taking the difference between the TE signal and the LPF component input to Pin 43. The comparison signal is output from Pin 24 (SENS). Address 3 selects the automatic adjustment comparator output, and HPF for data (D3) = or LPF for data (D3) = 0 is selected. The anti-shock circuit always operates in the CXA782 so that TG and TG2 (address : D3) should be set to for tracking adjustment to prevent this effect. When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC. 6

17 LD PD µ/6.3v 00µ/6.3V 30k 30k CXA782CQ/CR Center Voltage Generation Circuit (Single voltage application; Connect to GND when it s positive/negative dual power supplies.) Maximum current is approximately ±3mA. utput impedance is approximately 50Ω. VC 50 VC 48 VEE APC Circuit When the laser diode is driven with constant current, the optical output possesses large negative temperature characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output remains constant. LD 33 k 0µH PD 34 56k 55k 56k VREF.25V VEE VEE GND VEE 7

18 Focus Servo 9k FE 5k 22k 2200p 0.47µ FE 2 FEI 3 FDFCT DFCT FS4 68k FZC Focus phase Compensation FE_ 6 FCUS CIL 680k 0.µ FGD 4 40k 50k µ 22µ FE_M 7 ISET 7 20k FLB 5 FSET FS2 8 50k SRCH FS 0.µ 5 0.0µ 4.7µ The above figure shows a block diagram of the focus servo. rdinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal Ω resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used, leave Pin 3 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately.2khz when a resistance of 50Ω is connected to Pin. The focus search height is approximately ±.Vp-p when using the constants indicated in the above figure. This height is inversely proportional to the resistance connected between Pin 7 and VEE. However, changing this resistance also changes the height of the track jump and sled kick as well. The FZC comparator inverted input is set to 5% of VCC and VC (Pin 48); (VCC VC) 5%. 5Ω resistance is recommended for Pin. 8

19 330k 47p 0.47µ 20k 0.05µ 0.0µ 0.0µ CXA782CQ/CR Tracking Sled Servo TE 42 TE + 30 HPF 50k BUFFER AMP 43 LPFI 7 LPF TEI 44 DFCT TM 680k TG SL_ SLED MTR 6 M 0.047µ 470k TDFCT 47 ATSC 45 k k 680k ATSC 66p TM6 TM5 22µA 22µA TM2 SL_M 5 SL_P 4 8.2k 3.3µ 0.033µ 0.022µ TZC 46 TGU 9 TG2 0 TG2 TZC 20k Tracking Phase Compensation TM4 TM3 TM7 µa µa 90k 82k TA_M 2 TA_ 3 22µ 5k TRACKING CIL 470k FSET 5 0.0µ The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 9 and 0 is a time constant to decrease the high-frequency gain when TG2 is FF. The peak frequency of the tracking phase compensation is approximately.2khz when a 5Ω resistance connected to Pin. In the CXA782, TG and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 N. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 2. To be more specific, Track jump peak voltage = TM3 (or TM4) current feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 N. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 5; Sled kick peak voltage = TM5 ( or TM6) current feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 7 and VEE. When this resistance is 20kΩ: TM3 ( or TM4) = ±µa, and TM5 (or TM6) = ±22µA. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (Ω) and the capacitance connected to Pin 47. 9

20 Focus K Circuit RF VCC C5 0.0µ RF_ 3 30 RF_I VG 54k 20k 25 FK 5k 92k 0.625V FCUS K AMP FCUS K CMPARATR The focus K circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 30 from Pin 3 (RF signal), and the LPF output (opposite phase) of the focus K amplifier output is also obtained. The focus K output reverses when VRFI VRF 0.37V. Note that, C5 determines the time constant of the HPF for the EFM comparator and mirror circuit and the LPF of the focus K amplifier. rdinarily, with a C5 equal to 0.0µF selected, the fc is equal to khz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. DEFECT Circuit After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant bottom hold responds to 0.ms or greater disc mirror defects, and the long time constant bottom hold holds the pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and comparing both signals, the mirror defect detection signal is generated µ CC CC RF_ 3 a 2 b DEFECT AMP c d e 24 SENS DEFECT SW 28 CB 0.0µ DEFECT BTTM HLD DEFECT CMPARATR a RF b DEFECT AMP c e BTTM HLD () ; solid Line: CC DEFECT H L d BTTM HLD (2) ; dotted Line: CC2 20

21 Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. RF_ 3 30 RF_I RF.4 G MIRRR AMP PEAK& BTTM HLD H I J MIRRR HLD AMP K 29 CP 0.033µ 20k LGIC MIRRR CMPARATR RF_ 0V G (RF_I) 0V H (PEAK HLD) 0V I (BTTM HLD) 0V J K (MIRRR HLD) MIRR H L The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal. In the CXA782, this mirror output is used only during braking operations, and no external output pin is attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. UT output to the MIRR input of the DSP. 2

22 Commands The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F. Commands for the CXA782 can be broadly divided into four groups ranging in value from $0X to $3X.. $0X ( FZC at SENS pin (Pin 24)) These commands are related to focus servo control. The bit configuration is as shown below. D7 D6 D5 D4 D3 D2 D D FS4 DEFECT FS2 FS Four focus-servo related switches exist: FS, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively. $00 When FS = 0, Pin 8 is charged to (22µA µa) 50kΩ = 0.55V. If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V. $02 From the state described above, the only FS2 becomes. When this occurs, a negative signal is output to Pin 6. This voltage level is obtained by equation below. (22µA µa) 50kΩ resistance between Pins 6 and 7... Equation 50kΩ $03 From the state described above, FS becomes, and a current source of +22µA is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as shown in Fig. below. 0V Fig.. Voltage at Pin 8 when FS gose from 0 This time constant is obtained with the 50kΩ resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2) 0V $ Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6) $04 When the fact that the RF signal is missing is detected and the scratches on the disc are detected with DEFECT = 0, DFCT (FS3) is turned N. 22

23 -. FS4 This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in charge of turning the focus servo N and FF. $00 $08 Focus FF Focus N -2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 6) is changing from negative to positive; and c) The focus S-curve is varying as shown below. A t Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. rdinarily, focus searching and the turning the focus servo switch N are performed during the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus K signal. In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In addition, focus K is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart. (20ms) (200ms) $02 ($00) $03 $08 Drive voltage The broken lines in the figure Focus error indicate the voltage assuming the signal is not in focus. SENS pin (FZC) The instant the signal is brought into focus. Focus K Fig. 4. Focus N timing chart 23

24 Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A. FZC? N Transfer $08 YES F. K? N F. K? N YES YES Transfer $08 FZC? N YES Latch Latch (A) (B) Fig. 5. Poor and good software command sequences -3. SENS pin (Pin 24) The output of the SENS pin differs depending on the input data as shown below. $0X: FZC $X: DEFECT $2X: TZC $3X: Automatic adjustment comparator output $4X to 7X: HIGH-Z 2. $X ( DEFECT at SENS pin (Pin 24)) These commands deal with switching TG/TG2, brake circuit N/FF, and the sled kick output. The bit configuration is as follows Sled kick height D7 D6 D5 D4 D3 D2 D D0 D D0 (PS) (PS0) TG, TG2 Break Sled kick circuit height N/FF N/FF 0 ±3 ±4 TG, TG2 The purpose of these switches is to switch the tracking servo gain Up/Normal. TG and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should be a 00-track jump to fall back down to a 0-track jump after a 00 or 0-track jump has been performed. To do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 80 out-of-phase to cut the unneeded portion of the tracking error and apply braking Relative value ± ±2 24

25 RF_I Tracking error (TZC) [ A] Envelope Detection [ D] Waveform Shaping [ B] Waveform Shaping [ E] Edge Detection (MIRR) [ C] [ F] (Latch) D Q CK D2 [ G] BRK TM7 Low: open High: make CXA782 Fig. 6. TMI movement during braking operation From inner to outer track From outer to inner track [ A] [ B] [ C] ( MIRR ) [ D] [ E] ( TZC ) [ F] [ G] [ H] 0V Braking is applied from here. Fig. 7. Internal waveform 3. $2X ( TZC at SENS pin (Pin 24)) These commands deal with turning the tracking servo and sled servo N/FF, and creating the jump pulse and fast forward pulse during access operations. D7 D6 D5 D4 D3 D2 D D Tracking Sled control control 00: FF 00: FF 0: Servo N 0: Servo N 0: F-JUMP 0: F-FAST FRWARD : R-JUMP : R-FAST FRWARD TM, TM3, TM4 TM2, TM5, TM6 25

26 4. $3X These commands control the balance and gain control circuit switches used during automatic tracking adjustment. In the initial resetting state, BAL to BAL3 switches are FF and TG to TG3 switches are N. Balance adjustment The balance adjustment switches BAL to BAL3 can be controlled by setting D3 = 0. The switches are set using D0 to D2. At this time, the balance adjustment LPF comparator output is selected at the SENS pin. Data is set by specifying switch conditions D0 to D2 and sending a latch pulse with D3 = 0. Sending a latch pulse with D3 = does not change the balance switch settings. START BAL to BAL3 Switch Control C. UT Is the frequency high enough? YES N SENS output Balance K? Adjustment Completed Balance adjustment Gain adjustment The gain adjustment switches TG to TG3 can be controlled by setting D3 =. These switches are set using D0 to D2. At this time, the balance adjustment HPF comparator output is selected for SENS pin. In a fashion similar to the method used with the balance adjustment, set the data by sending a latch pulse with D3 =, specifying the switch conditions D0 to D2. START TG to TG3 Switch control N SENS GAIN K? YES Adjustment Completed Gain adjustment 26

27 CPU Serial Interface Timing Chart DATA D0 D D2 D3 D4 D5 D6 D7 D0 twck twck tsu th CLK /fck tcd XLT td twl (VCC = 3.0V) Item Symbol Min. Type. Max. Unit Clock frequency fck MHz Clock pulse width fwck 500 ns Setup time tsu 500 ns Hold time th 500 ns Delay time td 500 ns Latch pulse width twl 000 ns Data transfer interval tcd 000 ns System Control Item ADRESS D7 D6 D5 D4 DATA D3 D2 D D0 SENS output Focus Control FS4 Focus N =, FF = 0 DEFECT (FS3) Disable = Enable = 0 FS2 Search N =, FF = 0 FS Search Up =, Down = 0 FZC Tracking Control TG, TG2 N =, FF = 0 Brake N =, FF = 0 Sled Kick + 2 Sled Kick + DEFECT Tracking Mode Tracking Mode Sled Mode 2 TZC Select 0 0 Automatic tracking adjustment mode Gain/Bal TRACKING MDE 2 SLED MDE D3 D2 D D0 FF 0 0 FF 0 0 N 0 N 0 FWD JUMP 0 FWD MVE 0 REV JUMP REV MVE 27

28 Serial Data Truth Table Serial Data Hex Functions FS = 432 FS4 DEFECT FS2 FS FCUS CNTRL DEFECT E: enable D: disable $00 $0 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F 0 E E 0 0 E 0 0 E 0 D D 0 0 D 0 0 D E 0 0 E 0 E 0 E D 0 0 D 0 D 0 D TRACKING MDE Hex TM = $20 $2 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F

29 Automatic adjustment mode Hex TG SW 3 2 BAL SW $30 $3 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F DATA D3 = 0: Balance switch setting DATA D3 = : Gain switch setting Note) 0 means FF and means N for TG SW and BAL SW. These are not equal to the setting values of each bit for serial data. Initial State (resetting state) Item ADDRESS D7 D6 D5 D4 DATA D3 D2 D D0 HEXADECIMAL Focus Control $00 Tracking Control $0 Tracking Mode $20 Select $37 $38 The above data means the following operation modes. Focus Control Focus off, Defect enable, Focus Search off, Focus Search down Tracking Control TG TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + off Tracking Mode Tracking off, Sled off Select Tracking gain min. (TG SW: ) Tracking balance: RE3 max. (TBAL SW: 0 0 0) 29

30 Notes on peration. FSET pin The FSET pin determines the fc for the focus and tracking high-frequency phase compensation. 2. ISET pin ISET current =.27V/R = Focus search current = Tracking jump current = Sled kick current ($X: PS = PS0 = 0) 2 Use the setting resistance within the range of 20kΩ to 240kΩ. If the resistance value is out of this range, the oscillation may be occurred in the ISET block. 3. FE (focus error)/te (tracking error) gain changing method ) High gain: Resistance between FE pins (pins 6 and 7) Ω Large Resistance between TE pins (pins 2 and 3) Ω Large 2) Low gain: A signal, whose resistance is divided between Pins and 2, is input to FE. The internal gain adjustment circuit is used for TE. 4. Input voltage at Pins 9 to 22 of the microcomputer interface should be as follows: VIH VCC 90% or more VIL VCC 0% or less 5. Focus K circuit ) Refer to the Description of peration for the time constant setting of the focus K amplifier LPF and the mirror amplifier HPF. VCC 20k FK The FK and comparator output are as follows: 40k 25 utput voltage High: VFKH near VCC RL utput voltage Low: VFKL Vsat (NPN) VCC 6. Sled amplifier VEE VEE The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20. Sled/Tracking internal phase compensation and reference design material Item SD Measurement pin Conditions Typ. Unit FCS.2kHz gain.2khz phase CFLB = 0.µF CFGD = 0.µF deg.2khz gain 25 3 TRK.2kHz phase 2.7kHz gain CTGU = 0.µF deg 2.7kHz phase deg 30

31 Package utline Unit: mm CXA782CQ 48PIN QFP (PLASTIC) 5.3 ± ± 0.2 M ± 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL EPXY RESIN SNY CDE QFP-48P-L04 LEAD TREATMENT SLDER / PALLADIUM PLATING EIAJ CDE QFP048-P-22-B LEAD MATERIAL CPPER / 42 ALLY JEDEC CDE PACKAGE WEIGHT 0.7g NTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). CXA782CR 48PIN LQFP (PLASTIC) 9.0 ± ± (0.22) A (8.0) 0.5 ± ± ± to ± 0.2 NTE: Dimension does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPXY / PHENL RESIN SNY CDE LQFP-48P-L0 LEAD TREATMENT SLDER PLATING EIAJ CDE QFP048-P-0707-A LEAD MATERIAL 42 ALLY JEDEC CDE PACKAGE WEIGHT 0.2g NTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 3