7-Bit 0.25dB Digital Step Attenuator 1MHz to 6GHz

Transcription

1 7-Bit.5dB Digital Step Attenuator 1MHz to GHz F195 Datasheet Description The F195 is part of IDT s Glitch-Free TM family of DSAs optimized for the demanding requirements of Base Station (BTS) radio cards and numerous other applications. This device is offered in a compact mm x mm -pin package with 5Ω input and output impedance for ease of integration into the radio or RF system. The F195 offers very high reliability due to its construction from a monolithic silicon die in a QFN package. The insertion loss is very low with minimal distortion. Additionally, the device is designed to have extremely accurate attenuation levels. These accurate attenuation levels improve system SNR and/or ACLR by ensuring system gain is as close to the targeted level as possible. In addition, the very fast settling time in parallel mode is ideal for fast switching systems. Finally, the device uses our Glitch-Free TM technology in contrast to competing DSAs. Features Serial and 7-bit parallel interface 31.75dB range.5db steps Glitch-Free TM : low transient overshoot 5ns settling time for.5db steps Ultra linear > 3dBm IIP3 Low insertion loss < 1.7dB at GHz Attenuation error < ±.db at GHz Bi-directional RF use 3.3V or 5V supply - C to +15 C operating temperature mm x mm Thin QFN -pin package Competitive Advantage Lowest insertion loss for best SNR Glitch-Free TM technology to protect power amplifiers or ADC during transitions between attenuation states Extremely accurate attenuation levels Ultra-low distortion MSL1 and V HBM ESD Block Diagram Figure 1. Block Diagram Typical Applications RF1 RF 3G/G/G+ Base Station Systems Distributed Antenna Systems, DAS Remote Radio Heads Active Antenna Systems, AAS Broadband Satellite Equipment NFC Infrastructure Military Communication Equipment Bias VMODE D[:] DATA CLK LE Glitch-Free TM VDD Decoder SPI 1 Integrated Device Technology, Inc. 1 Rev O, March, 1

2 D1 D D3 D D5 D F195 Datasheet Pin Assignments Figure. Pin Assignments for mm x mm x.75mm TQFN Package Top View D 1 1 DATA VDD VMODE 3 B I A S Decoder SPI 17 1 CLK LE 15 RF1 5 1 RF EPAD 13 Pin Descriptions Table 1. Pin Descriptions Number Name Description 1 D Parallel control pin.5db. Pull high for attenuation. V DD Power supply input. Bypass to ground with capacitors as close as possible to pin. 3 V MODE Parallel or serial programming mode pin. Leave open or logic LOW for parallel mode. Logic HIGH for serial mode., - 13, 15 Internally grounded. These pins must be grounded as close to the device as possible. 5 RF1 1 RF 1 LE Serial latch enable. 17 CLK Serial clock input. 1 DATA Serial data input. RF Port 1. Can be used as either the input or output RF (bi-directional). Port must be at V DC. An external AC coupling capacitor must be used if there is a DC voltage present. RF Port. Can be used as either the input or output RF (bi-directional). Port must be at V DC. An external AC coupling capacitor must be used if there is a DC voltage present. 19 D Parallel control pin 1dB. Pull HIGH for attenuation. [a] D5 Parallel control pin db. Pull HIGH for attenuation. [a] 1 D Parallel control pin db. Pull HIGH for attenuation. [a] D3 Parallel control pin db. Pull HIGH for attenuation. [a] 3 D Parallel control pin 1dB. Pull HIGH for attenuation. [a] D1 Parallel control pin.5db. Pull HIGH for attenuation. [a] EPAD [a] There is a 5kΩ pull-down resistor to ground. Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance. 1 Integrated Device Technology, Inc. Rev O, March, 1

3 F195 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the F195 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Power Supply Voltage V DD V V MODE, DATA, CLK, LE, D[:] V CTRL -.3 Lower of (V DD +.5, 5.) RF1, RF V RF V Maximum RF Input Power to RF1 or RF (> 1 MHz) P MAX +3 dbm Junction Temperature T JMAX +15 C Storage Temperature Range T STOR C Lead Temperature (soldering, 1s) T LEAD + C Electrostatic Discharge HBM (JEDEC/ESDA JS-1-1) Electrostatic Discharge CDM (JEDEC -C11F) V ESDHMB V ESDCDM (Class ) 1 (Class C3) V V V 1 Integrated Device Technology, Inc. 3 Rev O, March, 1

4 F195 Datasheet Recommended Operating Conditions Table 3. Recommended Operating Conditions Parameter Symbol Condition Minimum Typical Maximum Units Power Supply Voltage V DD V Operating Temperature Range T EP Exposed paddle C RF Frequency Range f RF.1 GHz Maximum Input Power P MAX RF1 or RF See Figure 3 dbm RF Peak Input Power P PEAK RF1 Port, V DD = 3.3V, T EP = 5 C, f RF > 5MHz, WCDMA, 3GPP, Downlink, DPCH, Chip rate =3.MSPS, Avg. P IN = +dbm 1 %.9.1 % % % 33. RF1 Port Impedance Z 1 5 RF Port Impedance Z 5 dbm Figure 3. Maximum Operating CW Input Power vs. Input Frequency 1 Integrated Device Technology, Inc. Rev O, March, 1

5 F195 Datasheet Electrical Characteristics Table. Electrical Characteristics Specifications apply at V DD = 3.3V, T EP = 5 C, f RF = GHz, LSB =.5dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[:] = [], Maximum attenuation D[:] = [ ]. Parameter Symbol Condition Minimum Typical Maximum Units Logic Input HIGH V IH All logic pins. [a] 5.5 V Logic Input LOW V IL All logic pins 1 V Logic Current I IH, I IL µa DC Current I DD V DD = 3.3V 5 V DD = 5.5V 31 Attenuation Range No missing codes db Minimum Gain Step for Monotonicity DSA Settling Time [b] Maximum Video Feed-Through Maximum Spurious Level on any RF Port [c] LSB t SET VID FT SPUR MAX f RF <.GHz.5 f RF <.GHz.5 f RF <.GHz 1. Max to min attenuation to settle to within.5db of final value Min to max attenuation to settle to within.5db of final value Measured with 1ns rise time, V to 3.3V control pulse Unused RF ports terminated into 5Ω 1.. µa db µs 1 mv pp -11 dbm Serial Clock Speed f CLK 1 MHz Parallel to Serial Setup t PS 1 ns Serial Data Hold Time t H 1 ns LE Delay Time from final serial clock rising edge 1 ns Maximum Switch Rate SW RATE 5 khz [a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization. [b] Speeds are measured after SPI programming is completed (data latched with LE = LOW to HIGH transition). [c] Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is.mhz. 1 Integrated Device Technology, Inc. 5 Rev O, March, 1

6 F195 Datasheet Electrical Characteristics Table 5. Electrical Characteristics Specifications apply at V DD = 3.3V, T EP = 5 C, f RF = GHz, LSB =.5dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[:] = [], Maximum attenuation D[:] = [ ]. Insertion Loss Parameter Symbol Condition Minimum Typical Maximum Units Relative Phase Between the Minimum and Maximum Attenuation Step Error Absolute Attenuation Error IL Φ DNL INL RF1 Port Return Loss RL 1 RF Port Return Loss RL 1MHz f RF 1GHz 1.1 1GHz < f RF GHz [a] GHz < f RF 3GHz 1.5 3GHz < f RF GHz 1. GHz < f RF 5GHz 1.9 5GHz < f RF GHz. f RF = 1GHz 1 f RF = GHz 5 f RF = GHz 5 f RF = GHz 7 Maximum error between any two adjacent attenuation levels Max. error for state 19.75dB, f RF = MHz Max. error, over all states f RF = MHz db deg.15. db MHz f RF GHz GHz < f RF GHz 17 GHz < f RF GHz 13 1MHz f RF GHz GHz < f RF GHz 1 GHz < f RF GHz 1 [a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization. +.5 db db db 1 Integrated Device Technology, Inc. Rev O, March, 1

7 F195 Datasheet Electrical Characteristics Table. Electrical Characteristics Specifications apply at V DD = 3.3V, T EP = 5 C, f RF = GHz, LSB =.5dB steps and Evaluation Board (EVKit) trace and connector losses are de-embedded, unless otherwise noted. Minimum attenuation D[:] = [], Maximum attenuation D[:] = [ ]. Input IP3 Parameter Symbol Condition Minimum Typical Maximum Units IIP3 P IN = +19dBm per tone 5MHz tone separation Attn =.db Attn = 15.75dB Attn = 31.75dB P IN = +1dBm per tone 1MHz tone separation f RF =.7GHz [a] 3.3 f RF = 1.GHz 3.7 f RF =.GHz 3. f RF =.GHz 3.7 Input.1dB Compression [b] IP.1dB 35 dbm [a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are not shown in bold italics are guaranteed by design characterization. [b] The input.1db compression point is a linearity figure of merit. Refer to the Recommended Operating Conditions section and Figure 3 for the maximum operating power levels. dbm dbm 1 Integrated Device Technology, Inc. 7 Rev O, March, 1

8 F195 Datasheet Thermal Characteristics Table 7. Package Thermal Characteristics Parameter Symbol Value Units Junction to Ambient Thermal Resistance θ JA C/W Junction to Case Thermal Resistance (case is defined as the exposed paddle) θ JC-BOT C/W Moisture Sensitivity Rating (Per J-STD-) MSL 1 Typical Operating Conditions (TOC) V DD = 3.3V Z L = Z S = 5Ω T EP = 5 C f RF =.GHz Attenuation setting = db = D[:] =[] P in = +1dBm / tone 5MHz tone spacing All temperatures are referenced to the exposed paddle Evaluation Kit traces and connector losses are de-embedded 1 Integrated Device Technology, Inc. Rev O, March, 1

9 F195 Datasheet Typical Performance Characteristics Insertion Loss vs Frequency Figure Insertion Loss (db) Insertion Loss (db) Figure Insertion Loss vs Attenuator Setting GHz.5 GHz 5. GHz Figure. 1.5 GHz. GHz. GHz.5 GHz Attenuation Setting (db) Input Return Loss vs Frequency [All States] Figure Return Loss (db) Return Loss (db) 1. GHz 3.5 GHz. GHz Input Return Loss vs Attenuator Setting. GHz.5 GHz 5. GHz.5 GHz 3. GHz 5.5 GHz 1. GHz 3.5 GHz. GHz 1.5 GHz. GHz. GHz.5 GHz Figure Attenuation Setting (db) Output Return Loss vs Frequency [All States] Figure Return Loss (db) Return Loss (db).5 GHz 3. GHz 5.5 GHz Output Return Loss vs Attenuator Setting. GHz.5 GHz 5. GHz.5 GHz 3. GHz 5.5 GHz 1. GHz 3.5 GHz. GHz 1.5 GHz. GHz. GHz.5 GHz Integrated Device Technology, Inc Attenuation Setting (db) 9 Rev O, March, 1

10 Error (db) Error (db) Error (db) Error (db) Error (db) Error (db) F195 Datasheet Typical Performance Characteristics Figure 1. Worst Case Absolute Accuracy vs Frequency [LSB =.5dB] C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max Figure 1. Worst Case Absolute Accuracy vs Frequency [LSB =.5dB] C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max Figure 1. Worst Case Absolute Accuracy vs Frequency [LSB = 1.dB] Figure 11. Absolute Accuracy vs Attenuator Setting [LSB =.5dB] GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz Attenuation Setting (db) Figure 13. Absolute Accuracy vs Attenuator Setting [LSB =.5dB] GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz. GHz Attenuation Setting (db) Figure 15. Absolute Accuracy vs Attenuator Setting [LSB = 1.dB] C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz. GHz Attenuation Setting (db) 1 Integrated Device Technology, Inc. 1 Rev O, March, 1

11 Error (db) Error (db) Error (db) Error (db) Error (db) Error (db) F195 Datasheet Typical Performance Characteristics Figure 1. Worst Case Step Accuracy vs Frequency [LSB =.5dB] Figure 17. Step Accuracy vs Attenuator Setting [LSB =.5dB] GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max Figure 1. Worst Case Step Accuracy vs Frequency [LSB =.5dB] Attenuation Setting (db) Figure 19. Step Accuracy vs Attenuator Setting [LSB =.5dB] GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz. GHz C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max Figure. Worst Case Step Accuracy vs Frequency [LSB = 1.dB] Attenuation Setting (db) Figure 1. Step Accuracy vs Attenuator Setting [LSB = 1.dB] GHz.5 GHz 1. GHz 1.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz. GHz C / Min - C / Max C / Min +5 C / Max +15 C / Min +15 C / Max Attenuation Setting (db) 1 Integrated Device Technology, Inc. 11 Rev O, March, 1

12 F195 Datasheet Typical Performance Characteristics Figure 3. Relative Insertion Phase vs Attenuator Setting Phase (degrees) Phase (degrees) Figure. Relative Insertion Phase vs Frequency [All States] GHz.5 GHz 5. GHz 1.5 GHz. GHz. GHz.5 GHz 5 3 Positive phase means the device is electrically shorter. Positive phase means the device is electrically shorter Attenuation Setting (db) Figure. Attenuation vs Frequency [All States] Figure 5. Attenuation vs Attenuator Setting Attenuation (db) Attenuation (db) 1. GHz 3.5 GHz. GHz GHz.5 GHz 5. GHz.5 GHz 3. GHz 5.5 GHz 1. GHz 3.5 GHz. GHz 1.5 GHz. GHz. GHz.5 GHz V / - C 3. V / +5 C 3. V / +15 C V / - C 3.3 V / +5 C 3.3 V / +15 C Attenuation Setting (db) Figure. Insertion Loss vs Frequency [db] 5. V / - C 5. V / +5 C 5. V / +15 C Figure 7. Evaluation Board Insertion Loss. 5.5 V / - C 5.5 V / +5 C 5.5 V / +15 C Insertion Loss (db) Insertion Loss (db).5 GHz 3. GHz 5.5 GHz C +5 C C Integrated Device Technology, Inc. 1 1 Rev O, March, 1

13 Attenuation (db) Attenuation (db) Compression (db) Input IP3 (dbm) Input IP3 (dbm) F195 Datasheet Typical Performance Characteristics Figure. Input IP3 vs Frequency [db] Figure 9. Input IP3 vs Attenuation [GHz] C / RF1 - C / RF +5 C / RF1 +5 C / RF +15 C / RF1 +15 C / RF Figure 3. Compression vs Input Power [GHz] Attenuation (db) db.5 db.5 db 1. db. db. db. db 1. db 1. db 1. db. db 3. db db Input Power (dbm) Figure 31. Typical Switching Time for a.5db Attenuation Transition Figure 3. Switching Time between Maximum and Minimum Attenuation db to 5.75 db 5.75 db to 5.5 db Time (µs) - -. to db to. db Time (µs) 1 Integrated Device Technology, Inc. 13 Rev O, March, 1

14 F195 Datasheet Programming The F195 can be programmed using either the parallel or the serial mode, which is selectable via V MODE (pin 3). The serial mode is selected by pulling V MODE to a logic HIGH, and the parallel mode is selected by floating V MODE or setting it to logic LOW. Serial Mode F195 Serial Mode is selected by pulling V MODE to a logic HIGH. The serial interface uses a -bit word with only 7 bits used. The serial word is shifted in LSB (D) first. When serial programming is used, all the parallel control input pins (1, 19 - ) must be grounded. Table. 7-Bit SPI Word Sequence Data Bit D7 D D5 D D3 D D1 D Symbol Not Used Attenuation 1 db Control Bit Attenuation db Control Bit Attenuation db Control Bit Attenuation db Control Bit Attenuation 1 db Control Bit Attenuation.5 db Control Bit Attenuation.5 db Control Bit Table 9. Truth Table for Serial Control Word D7 (MSB) D D5 D D3 D D1 D (LSB) Attenuation (db) X X 1.5 X 1.5 X 1 1 X 1 X 1 X 1 X 1 1 X In the Serial Mode, the F195 is programmed via the serial port on the rising edge of Latch Enable (LE). It is required that LE be kept logic LOW until all data bits are clocked into the shift register. The F195 will change attenuation state after the data word is latched into the active register. Refer to Figure Integrated Device Technology, Inc. 1 Rev O, March, 1

15 F195 Datasheet Figure 33. Serial Register Timing Diagram Table 1. SPI Timing Diagram Values for the Serial Mode Parameter Symbol Test Condition Min Typical Max Units CLK Frequency f C 5 MHz CLK HIGH Duration Time t CH ns CLK LOW Duration Time t CL ns DATA to CLK Setup Time t S 1 ns CLK Period [a] t P ns CLK to Data Hold Time t H 1 ns Final CLK Rising Edge to LE Rising Edge t CLS 1 ns LE to CLK Setup Time t LS 1 ns LE Trigger Pulse Width t L 1 ns LE Trigger to CLK Setup Time [b] t LC 1 ns [a] (t CH + t CL ) 1/f C. [b] Once all desired data has been clocked in, LE must transition from LOW to HIGH after the minimum setup time t LC and before any further CLK signals. Serial Mode Default Startup Condition When the device is first powered up, it will default to the maximum attenuation of 31.75dB independent of the V MODE and parallel pin [D:D] conditions. Table 11. Default Setting Truth Table for Serial Control Word D7 (MSB) D D5 D D3 D D1 D (LSB) Attenuation (db) X Integrated Device Technology, Inc. 15 Rev O, March, 1

16 F195 Datasheet Parallel Control Mode For the F195, the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode Direct Parallel Mode is selected when V MODE is floating or a logic LOW and LE is a logic HIGH. In this mode, the device will immediately react to any voltage changes on the parallel control pins (1, 19 - ). Use Direct Parallel Mode for the fastest settling time. The serial pins, CLK and DATA, can be either grounded or left opened in the Parallel Mode. Latched Parallel Mode Latched Parallel Mode is selected when V MODE is floating or a logic LOW and LE is toggled from logic LOW to HIGH. To utilize Latched Parallel Mode: Set V MODE to logic LOW or leave floating. Set LE to logic LOW. Adjust pins (1, 19 - ) to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic LOW). Set LE to a logic HIGH. The device will then transition to the attenuation settings reflected by pins D - D. If LE is set to a logic LOW then the attenuator will not change state. The truth table for the Parallel Mode is identical for bits D to D as shown in the Serial Mode truth table; see Table 9. Figure 3. Latch Parallel Timing Diagram Table 1. Latched Parallel Timing Diagram Values Parameter Symbol Min Max Units Serial to Parallel Mode Setup Time t SPS 1 ns Parallel Data Hold Time t PDH 1 ns LE Minimum Pulse Width t LE 1 ns Parallel Data Setup Time t PDS 1 ns 1 Integrated Device Technology, Inc. 1 Rev O, March, 1

17 F195 Datasheet Evaluation Kit Picture Figure 35. Top View SW1 Switch for parallel control VLOGIC VMODE VDD J Parallel Control Pins RF1 RF J1 Serial Control Pins VDD Figure 3. Bottom View 1 Integrated Device Technology, Inc. 17 Rev O, March, 1

18 F195 Datasheet Evaluation Kit / Applications Circuit Figure 37. Electrical Schematic J9 VLOGIC D D1 D D3 D D5 D VMODE VDD J VDD HEADER 1x J 1 J7 HEADER 1x R9 1 C9 R1 C1 1 7 SW Logic LOW switch to '-' position Logic HIGH switch to '+' position pin DIP Sw itch 1 Pin Header R1 R R3 R R5 R R7 R VDD C1 C C3 C C5 C C7 C R11 R1 R J1 C11 C1 C13 HEADER J1 J U D VDD VMODE RF1 DATA 1 CLK 17 LE 1 15 RF 1 13 J D1 D 3 D3 D 1 D5 D 19 Thru Cal J5 1 RF1 J3 VDD J RF HEADER 1x 5 PAD VDD R1 VDD C1 C15 1 Integrated Device Technology, Inc. 1 Rev O, March, 1

19 F195 Datasheet Table 13. Bill of Material (BOM) Part Reference QTY Description Manufacturer Part # Manufacturer C1 - C, C11 - C pF ±5%, 5V, CG Ceramic Capacitor () GRM1555C1H11J MURATA C9, C15 1pF ±5%, 5V, CG Ceramic Capacitor () GRM1555C1H1J MURATA C1, C1 1nF ±5%, 5V, X7R Ceramic Capacitor (3) GRM1R71H13J MURATA R1 1 Ω Resistors () ERJ-GERX PANASONIC R1 - R, R11 - R Ω ±1%, 1/1W, Resistor () ERJ-RKF1X PANASONIC R9 1 1kΩ ±1%, 1/1W, Resistor () ERJ-RKF1X PANASONIC J5, J7, J 3 CONN HEADER VERT SGL X 1 POS GOLD 911--AR 3M J1 1 CONN HEADER VERT SGL X POS GOLD HLF Amphenol FCI J 1 CONN HEADER VERT SGL 1 X 1 POS GOLD AR 3M J1 - J, J11 5 Edge Launch SMA (.375 inch pitch ground, tab) Emerson Johnson SW1 1 SWITCH POSITION DIP SWITCH KAT11E E-Switch U1 1 DSA F195NBGK IDT 1 Printed Circuit Board F195 EVKit Rev 1 IDT J9, R1 Do Not Populate (DNP) 1 Integrated Device Technology, Inc. 19 Rev O, March, 1

20 F195 Datasheet Evaluation Kit Operation Power Supply Setup Set up a power supply in the voltage range of 3.V to 5.5V with the power supply output disabled. The voltage can be applied via one of the following connections (see Figure 3): J11 connector J5 header connection (note the polarity of the pin on this connector) Pin 9 (V DD ) and pin 1 () on the J header connection Figure 3. Power Supply Connections V DD V DD Parallel Logic Control Setup The Evaluation Board has the ability to control the F195 in the Parallel Mode. For external control, apply logic voltages to the J header pins 1 through 7 (see Figure 39). For manual control, switches 1 through 7 on SW1 can be set. The switch is a three-position switch. The bottom position, "-" will ground the pin. The center position "O" will leave the pin open circuited. Setting the switch to the top position "+" will apply a voltage that is supplied to the switch. The logic voltage can be applied in one of three ways: Apply a voltage through a SMA connector (J9). This connector is not supplied. Apply a voltage on pin of the J7 header connector. Short out the two header connectors, J7 and J, so a resistor divider will generate the correct logic voltage from the power supply on the Evaluation Board. The logic voltage will be V DD. 1 Integrated Device Technology, Inc. Rev O, March, 1

21 SW1 Switch for parallel control F195 Datasheet Figure 39. Parallel Logic Voltage Connections SW1 Switch for parallel control V MODE V DD VLOGIC V MODE J Parallel Control Pins V DD J Parallel Control Pins Serial Logic Control Setup The Evaluation Board has the ability to control the F195 in the Serial Mode. Connect the serial controller to the J1 header connection as shown in Figure. To use the Serial Mode, set SW1 switch to the "+" or "O" position. RF The attenuation setting can be programmed according to Table 9. Figure. Serial Logic Connections RF1 RF J1 Serial Control Pins Power-On Procedure V DD J11 Serial Control Pins Set up the voltage supplies and Evaluation Board as described in the "Power Supply V Setup" section and either the "Parallel Logic Control Setup" DD or "Serial Logic Control Setup" sections above. Enable the power supply. Enable the proper attenuation setting according to Table 9. Power-Off Procedure Set the logic control pins to a logic LOW. Disable the power supply. 1 Integrated Device Technology, Inc. 1 Rev O, March, 1

22 F195 Datasheet Application Information Digital Pin Voltage and Resistance Values Table 1 provides the open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Table 1. Digital Pin Voltages and Resistance Pin Name Open Circuit DC Voltage Internal Connection 3, 1, 17, 1 V MODE, LE, CLK, DATA V 5kΩ pull-down resistor to 1, 19 - D, D D1 V 5kΩ pull-down resistor to Power Supplies A common power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade the noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage changes or transients should have a slew rate smaller than 1V/µs. In addition, all control pins should remain at V (+/-.3V) while the supply voltage ramps or while it returns to zero. If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to pins for the SPI (1, 17, 1), parallel (1, 19-) and V MODE pin (3) as shown below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control line. Figure 1. Control Pin Interface for Signal Integrity D3 5 kohm pf pf 5 kohm D D 5 kohm pf pf 5 kohm D5 D1 5 kohm pf pf 5 kohm D pf 5 kohm DATA D 5 kohm 1 1 VMODE 5 kohm pf pf 3 B I A S Decoder SPI pf pf 5 kohm 5 kohm CLK LE 5 1 EPAD 13 1 Integrated Device Technology, Inc. Rev O, March, 1

23 F195 Datasheet Package Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. Ordering Information Orderable Part Number Package MSL Rating Shipping Packaging Temperature F195NBGK mm x mm x.75mm pin QFN 1 Tray - C to +15 C F195NBGK mm x mm x.75mm pin QFN 1 Reel - C to +15 C F195EVB F195EVS Evaluation Board Evaluation Solution including the Evaluation Board, Controller Board, and cable. The Evaluation Software is available for download on the product page on the IDT website: Marking Diagram F195 NBGK Z171AAG 1. Line 1 and are the part number.. Line 3 Z is for die version. 3. Line 3 yyww = 171 has two digits for the year and week that the part was assembled.. Line 3 NG denotes Assembly Lot number. 1 Integrated Device Technology, Inc. 3 Rev O, March, 1

24 F195 Datasheet Revision History Revision Revision Date Description of Change O March, 1 Initial Release Corporate Headquarters Silver Creek Valley Road San Jose, CA Sales or -- Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as IDT ) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operati ng parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual property rights of others. This document is presented o nly as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the Uni ted States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. 1 Integrated Device Technology, Inc. Rev O, March, 1