F2480 Datasheet. Broadband RF Analog VGA 400 to 3000 MHz. Features. Description. Competitive Advantage. Block Diagram. Typical Applications

Transcription

1 Broadband RF Analog VGA 4 to 3 MHz F248 Datasheet Description The F248 is a 4 to 3 MHz RF Analog Variable Gain Amplifier (AVGA) that can be used in receivers, transmitters and other applications. Either the amplifier or voltage variable attenuator (VVA) can be configured as the first stage in the cascade. The F248 RF AVGA provides 12dB typical maximum cascade gain (no attenuation) with 4.3dB noise figure (amplifier as first stage) and 36dB gain adjustment designed to operate with a single +5V supply. Nominally, the amplifier offers +41.5dBm output IP3 using 16mA of I CC. This device is packaged in a 5 x 5 mm, 32-pin TQFN with 5 single-ended RF input and RF output impedances for ease of integration into the signal-path lineup. Competitive Advantage The F248 RF AVGA provides very high-performance by combining a silicon VVA & a Zero-Distortion RF amplifier in a single, compact TQFN package. Because of the superb VVA IP3 performance over its full attenuation range, the VVA can be placed after the amplifier while yielding the desired cascaded OIP3 performance. Utilizing IDT s technology, the resultant RF AVGA provides +41.5dBm OIP3 performance at 9MHz. The device is internally matched so there is no need to optimize external matching elements. Features 4 to 3 MHz (Amplifier Range) 5 to 6 MHz (Attenuator Range) 12dB typical cascaded max gain 36dB continuous gain range Excellent linearity +41.5dBm OIP3 Noise Figure 4.3dB I CC = 16mA 1.2mA Amplifier Standby Current Bi-directional attenuator RF ports Positive amplifier gain slope vs. frequency to counteract system PCB loss. V MODE pin allows either positive or negative attenuation control response Linear-in-dB attenuation characteristic 4 RF Port pinout supporting multiple lineup configurations 5Ω input and output impedances Broadband, Internally Matched 5 x 5 mm, 32-pin TQFN package Block Diagram Figure 1. Block Diagram Typical Applications Multi-mode, Multi-carrier Receivers PCS19 Base Stations DCS18 Base Stations WiMAX and LTE Base Stations UMTS/WCDMA 3G Base Stations PHS/PAS Base Stations Point to Point Infrastructure Public Safety Infrastructure Broadband Repeaters GPS Receivers Distributed Antenna Systems Cable Infrastructure Digital Radio RFAMP_IN Band_Select STBY V CC 2 I BIAS Bias Control Zero-Distortion TM RFAMP_OUT ATTN_RF1 Control ATTN_RF2 V CTRL V MODE 217 Integrated Device Technology, Inc. 1 March 23, 217

2 F248 Datasheet Pin Assignments Figure 2. Pin Assignments for 5 x 5 x.75 mm - TQFN Package Top View NC 1 24 NC GND 2 23 NC RFAMP_IN 3 22 V MODE GND 4 21 V CC NC NC NC NC VCC Band_Select STBY RSET RDSET NC ATTN_RF2 NC NC GND RFAMP_OUT GND NC NC ATTN_RF1 NC EP Bias Ctrl Control V CTRL NC NC NC 217 Integrated Device Technology, Inc. 2 March 23, 217

3 F248 Datasheet Pin Descriptions Table 1. Pin Descriptions Number Name Description 1, 5, 6, 7, 8, 14, 16, 17, 18, 19, 23, 24, 25, 27, 28, 32 NC No internal connection. These pins can be left unconnected, have voltage applied, or connected to ground (recommended). 2, 4, 29, 31 GND Ground these pins. These pins are internally connected to the exposed paddle. 3 RFAMP_IN Amplifier input internally matched to 5. Must use external DC block. 9 V CC 1 Band_Select 11 STBY +5V Power Supply. Tie to V CC and connect bypass capacitors as close to the pin as possible. See Typical Application Circuit for details. Leave pin open circuited for low-band select and connect Ω resistor to GND for mid-band, high-band and wide-band applications. A pull-up resistor of approximately 1.5M connects between this pin and V CC. Logic Low or Open on this pin enables the device. Logic High puts the device into Standby mode. A pulldown resistor of approximately 1M connects between this pin and GND. 12 RSET Connect external resistor to GND to optimize amplifier bias. Used in conjunction with pin RDSET Connect external resistor to GND to optimize amplifier bias. Used in conjunction with pin 12. ATTN_RF2 2 V CTRL 21 V CC 22 V MODE 26 ATTN_RF1 Attenuator RF Port 2. Matched to 5. Use an external DC blocking capacitor as close to the device as possible. Attenuator control voltage. Apply a voltage in the range as specified in the General Specifications Table. See application section for details about V CTRL. This pin has an internal pull down resistor. +5V Power Supply. Tie to V CC and connect bypass capacitors as close to the pin as possible. See Typical Application Circuit for details. Attenuator slope control. Set to logic LOW to enable negative attenuation slope (Attenuation low to high as voltage is increased). Set to logic HIGH to enable positive attenuation slope (Attenuation high to low as voltage is increased). Attenuator RF Port 1. Matched to 5. Use an external DC blocking capacitor as close to the device as possible. 3 RFAMP_OUT Amplifier output internally matched to 5. Must use external DC block as close to the pin as possible. EP Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the noted RF performance. 217 Integrated Device Technology, Inc. 3 March 23, 217

4 F248 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the F248 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units V CC to GND V CC V STBY, Band_Select V LOGIC -.3 V CC +.25 V RSET I RSET +1.5 ma RDSET I RDSET +.8 ma RFAMP_IN externally applied DC voltage V RFAMPin V RFAMP_OUT externally applied DC voltage V RFAMPout V CC -. V CC +. V V MODE to GND V MODE -.3 V CTRL to GND (V CC = to 5.25 V) V CTRL -.3 Lower of (V CC, 3.9) Lower of (V CC, 4.) ATTEN_RF1, ATTEN_RF2 V ATTENRF V RFAMP_IN RF Input Power applied for 24 hours maximum (V CC applied, RF = 2GHz, T A=+25 C) ATTN_RF1 or ATTN_RF2 RF Input Power (@ 2GHz and +85 C) P MAXAMP +22 dbm P MAXATTEN +3 dbm Continuous Power Dissipation P diss 1.5 W Junction Temperature T j + C Storage Temperature Range T st C Lead Temperature (soldering, 1s) +26 C Electrostatic Discharge HBM (JEDEC/ESDA JS-1-214) Electrostatic Discharge CDM (JEDEC 22-C11F) Class 1C Class C3 V V 217 Integrated Device Technology, Inc. 4 March 23, 217

5 F248 Datasheet Recommended Operating Conditions Table 3. Recommended Operating Conditions Parameter Symbol Condition Minimum Typical Maximum Units Power Supply Voltage V CC All V CC Pins V Operating Temperature Range T EP Exposed Paddle Temperature -4 + C RF Frequency Range Amplifier RF Maximum Input Operating Power Attenuator RF Maximum Input Operating Power f RF Amplifier 4 3 Attenuator 5 6 P max1, CW T EP = -4 to C 8 dbm P max2, CW ATTEN_RF1 or ATTEN_RF2 See Figure 3 dbm RFAMP_IN Port Impedance Z RFAMPIN 5 Ω RFAMP_OUT Port Impedance Z RFAMPOUT 5 Ω ATTN_RF1 Port Impedance Z ATTNRF1 5 Ω ATTN_RF2 Port Impedance Z ATTNRF2 5 Ω MHz Figure 3. Attenuator Maximum RF Input Power vs. Frequency 217 Integrated Device Technology, Inc. 5 March 23, 217

6 F248 Datasheet Electrical Characteristics Table 4. General Electrical Characteristics Parameter Symbol Condition Minimum Typical Maximum Units Logic Input High Threshold V IH_AMP STBY, Band_Select 1.1 [a] V CC [b] V Logic Input Low Threshold V IL_AMP STBY, Band_Select V V MODE Logic V CTRL Voltage Logic Current V IH_Mode V CC > 3.9V V V CC 3.9V 1.17 V CC.3 V IL_Mode.63 V CTRL 3.9V < V CC 5.25V V V CC 3.9V V CC.3 I STBY I Band_Select -1 1 I MODE Control Current I CTRL Pin µa Supply Current Startup Time from STBY I CC Pin Pin 9 Low Band Bias 16 Pin 9 Mid Band Bias Pin 9 High Band Bias 121 Pin 9 Wide Band Bias 121 Pin 9 Standby % of STBY going low to Gain within ± 1dB a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization. V V µa ma 25 ns 217 Integrated Device Technology, Inc. 6 March 23, 217

7 F248 Datasheet Table 5. Stand Alone Amplifier Electrical Characteristics Typical Application Circuit. See Table 8 band settings as noted (LB, MB, HB, WB), V CC = +5.V, T EP = +25 C, f RF = 2MHz, P OUT = dbm/tone for single tone and two tone tests, OIP3 tone delta = 1MHz, all RF source and RF load impedances = 5Ω, PCB board and connector losses are de-embedded, unless otherwise noted. Parameter Symbol Condition Minimum Typical Maximum Units Input Return Loss RL AMPIN 16 db Output Return Loss RL AMPOUT 17 db Gain Noise Figure Output Third Order Intercept Point Output 1dB Compression Reverse Isolation G LB 4MHz Low Band Bias MHz Low Band Bias 12.1 [a] G MB 2MHz Mid Band Bias 14.1 G HB 27MHz High Band Bias G WB NF LB 4MHz Wide Band Bias MHz Wide Band Bias MHz Low Band Bias 4.5 9MHz Low Band Bias 4.3 NF MB 2MHz Mid Band Bias 4.5 NF HB 27MHz High Band Bias 5. NF WB OIP3 LB 4MHz Wide Band Bias MHz Wide Band Bias 5. 4MHz Low Band Bias 37 9MHz Low Band Bias 38 [b] 41.5 OIP3 MB 2MHz Mid Band Bias 41 OIP3 HB 27MHz High Band Bias 4 OIP3 WB OP1dB LB 4MHz Wide Band Bias 35 27MHz Wide Band Bias 39 4MHz Low Band Bias MHz Low Band Bias 2.9 OP1dB MB 2MHz Mid Band Bias 19.7 OP1dB HB 27MHz High Band Bias 19.5 OP1dB WB RevISO LB 4MHz Wide Band Bias MHz Wide Band Bias MHz Low Band Bias 2.5 9MHz Low Band Bias 18.5 RevISO MB 2MHz Mid Band Bias 18 RevISO HB 27MHz High Band Bias 18 RevISO WB 4MHz Low Band Bias MHz High Band Bias 18 a. Items in min/max columns in bold italics are guaranteed by test. b. Items in min/max columns that are not bold/italics are guaranteed by design characterization. db db dbm dbm db 217 Integrated Device Technology, Inc. 7 March 23, 217

8 F248 Datasheet Table 6. Stand Alone Voltage Variable Attenuator Electrical Characteristics Typical Application Circuit. V CC = +5V, T EP = +25 C, signals applied to ATTEN_RF1 input, f RF = 2MHz, minimum attenuation, P IN = dbm for small signal parameters, P IN = +2dBm / tone for single tone and two tone linearity tests, two tone delta frequency = 5MHz, all RF source and RF load impedances = 5Ω, PCB board traces and connector losses are de-embedded, unless otherwise noted. Insertion Loss Maximum Attenuation Parameter Symbol Condition Minimum Typical Maximum Units Relative Insertion Phase Relative to Insertion Loss Minimum ATTEN_RF1 Return Loss Over Control Voltage Range Minimum ATTEN_RF2 Return Loss Over Control Voltage Range Input IP3 A min A max 5MHz [a] 1. 7MHz 1.2 2MHz MHz 1.5 6MHz 2.7 5MHz [a] 29 7MHz MHz MHz MHz 37 Φ MAX At 35dB attenuation 27 Φ MID At 18dB attenuation 1 S11 S22 5MHz [a] 16 7MHz 17 2MHz 17 27MHz 17 6MHz 5MHz [a] 14 7MHz 2MHz 16 27MHz 17 6MHz 13 IIP3 65 dbm IIP3 ATTEN All attenuation settings dbm Minimum Output IP3 OIP3 MIN Maximum attenuation 35 dbm Input IP2 ( f 1+ f 2 ) IIP2 P IN + IM2 [dbc] 95 IIP2 MIN All attenuation settings 87 Input IH2 HD2 P IN + H2 [dbc] 9 dbm Input IH3 HD3 P IN + H3 [dbc]/2 54 dbm Input 1dB Compression [b] IP1dB 34.4 dbm Settling Time T SETTL.1dB Any 1dB step in the db to 33dB range. 5% V CTRL to RF settled to within ±.1dB db db deg db db dbm µs a. Set blocking capacitors C2 and C9 to.1µf to achieve best return loss performance at 5MHz. b. The input 1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. 217 Integrated Device Technology, Inc. 8 March 23, 217

9 F248 Datasheet Thermal Characteristics Table 7. Package Thermal Characteristics Parameter Symbol Value Units Amplifier - Junction to Ambient Thermal Resistance. θ JA-AMP 4 C/W Attenuator - Junction to Ambient Thermal Resistance. θ JA-ATTN 8 C/W Amplifier - Junction to Case Thermal Resistance. (Case is defined as the exposed paddle) Attenuator - Junction to Case Thermal Resistance. (Case is defined as the exposed paddle) θ JC_BOT_AMP 4 C/W θ JC_BOT_ATTN 5 C/W Moisture Sensitivity Rating (Per J-STD-2) MSL 1 Typical Operating Conditions (TOC) Unless otherwise noted: V CC = +5.V T EP = +25 C (T EP is defined as the exposed paddle temperature). Amplifier components configured for operation per Table 8 for each indicated band. P OUT = dbm/tone for all amplifier linearity tests. 1MHz tone spacing for all amplifier linearity tests. P IN = +2dBm/tone applied to ATTEN_RF1 for all attenuator linearity tests. 5MHz tone spacing for all attenuator linearity tests. V CTRL setting = minimum attenuation setting. STBY = Logic HIGH (or open). Band Select = GND. V MODE = Logic LOW = Negative Slope. Evaluation kit trace and connector losses are fully de-embedded. S-parameters for the amplifier and attenuator have external RF caps replaced by resistors for purposes of displaying broadband results. Since the Wide Band and Mid Band settings are the same in Table 8, the Mid Band results will be the same curves as those displayed in the Amplifier Wide Band section. 217 Integrated Device Technology, Inc. 9 March 23, 217

10 F248 Datasheet Typical Performance Characteristics Attenuator [1] Figure 4. Attenuation vs. VCTRL over Frequency and VMODE Figure 5. Attenuation vs. Frequency over VCTRL GHz / Vmode = V.9GHz / Vmode = 3V 2.GHz / Vmode = V 2.GHz / Vmode = 3V 3.GHz / Vmode = V 3.GHz / Vmode = 3V Vctrl =.V Vctrl =.8V Vctrl = 1.V Vctrl = 1.2V Vctrl = 1.4V Vctrl = 1.6V Vctrl = 1.8V Vctrl = 2.4V Figure 6. Min Min. and Max. Attenuation vs. Frequency over Temperature -4C / Vctrl =.V 25C / Vctrl =.V C / Vctrl =.V -4C / Vctrl = 3.V 25C / Vctrl = 3.V C / Vctrl = 3.V Max. Figure 7. Attenuation Delta to 25C (db) Attenuation Delta to +25 C vs. VCTRL over Frequency and Temperature -4C /.9GHz -4C / 2.GHz -4C / 3.GHz C /.9GHz C / 2.GHz C / 3.GHz Integrated Device Technology, Inc. 1 March 23, 217

11 F248 Datasheet Typical Performance Characteristics Attenuator [2] Figure 8. Attenuation vs. VCTRL over Frequency Figure 9. Attenuation Slope vs. VCTRL over GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz Attenuation Slope (db/v) Frequency.4GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz Figure 1. Return Loss (ATTEN_RF1 port) vs. VCTRL over Frequency Figure 11. Return Loss (ATTEN_RF2 port) vs. VCTRL over Frequency.4GHz.4GHz -5.7GHz 1.5GHz -5.7GHz 1.5GHz RF1 Return Loss (db) GHz 4.GHz 5.GHz 6.GHz RF2 Return Loss (db) GHz 4.GHz 5.GHz 6.GHz Figure 12. Insertion Phase Change vs. VCTRL over Frequency Figure 13. Insertion Phase Slope vs. VCTRL over Frequency Insertion Phase (deg) GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz (positive phase = electrically shorter) Insertion Phase Slope (deg/v) GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz Integrated Device Technology, Inc. 11 March 23, 217

12 F248 Datasheet Typical Performance Characteristics Attenuator [3] Figure 14. Attenuation Response vs. VCTRL over Frequency and Temperature C /.9GHz 25C /.9GHz C /.9GHz -4C / 2.GHz 25C / 2.GHz C / 2.GHz -4C / 3.GHz 25C / 3.GHz C / 3.GHz Figure 16. Return Loss (ATTEN_RF1) vs. VCTRL over Frequency and Temperature -4C /.9GHz -4C / 2.GHz -4C / 3.GHz Figure. Attenuation Slope vs. VCTRL over Frequency and Temperature Attenuation Slope (db/v) C /.9GHz 25C /.9GHz C /.9GHz -4C / 2.GHz 25C / 2.GHz C / 2.GHz -4C / 3.GHz 25C / 3.GHz C / 3.GHz Figure 17. Return Loss (ATTEN_RF2) vs. VCTRL, over Frequency and Temperature -4C /.9GHz -4C / 2.GHz -4C / 3.GHz -5 25C /.9GHz 25C / 2.GHz 25C / 3.GHz -5 25C /.9GHz 25C / 2.GHz 25C / 3.GHz RF1 Return Loss (db) C /.9GHz C / 2.GHz C / 3.GHz RF2 Return Loss (db) C /.9GHz C / 2.GHz C / 3.GHz Figure 18. Insertion Phase Change vs. VCTRL over Frequency and Temperature Figure 19. Insertion Phase Slope vs. VCTRL over Frequency and Temperature 7-4C /.9GHz -4C / 2.GHz -4C / 3.GHz Insertion Phase Slope (deg/v) C /.9GHz 25C / 2.GHz 25C / 3.GHz C /.9GHz C / 2.GHz C / 3.GHz Integrated Device Technology, Inc. 12 March 23, 217

13 F248 Datasheet Typical Performance Characteristics Attenuator [4] Figure 2. Return Loss (ATTEN_RF1 port) vs. Attenuation over Frequency RF1 Return Loss (db) Figure 22. Return Loss (ATTEN_RF2 port) vs. Attenuation over Frequency RF2 Return Loss (db) Figure 24. Insertion Phase Change vs. Attenuation over Frequency Insertion Phase (deg) GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz GHz.7GHz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz (positive phase = electrically shorter).4ghz.7ghz 1.5GHz 2.7GHz 4.GHz 5.GHz 6.GHz Figure 21. Return Loss (ATTEN_RF1 port) vs. Attenuation over Freq & Temp RF1 Return Loss (db) C /.9GHz -4C / 2.GHz -4C / 3.GHz 25C /.9GHz 25C / 2.GHz 25C / 3.GHz C /.9GHz C / 2.GHz C / 3.GHz Figure 23. Return Loss (ATTEN_RF2 port) vs. Attenuation over Freq & Temp RF2 Return Loss (db) C /.9GHz -4C / 2.GHz -4C / 3.GHz 25C /.9GHz 25C / 2.GHz 25C / 3.GHz C /.9GHz C / 2.GHz C / 3.GHz Figure 25. Insertion Phase Change vs. Attenuation over Freq & Temp Integrated Device Technology, Inc. 13 March 23, 217

14 F248 Datasheet Typical Performance Characteristics Attenuator [5] Figure 26. Min. and Max. Attenuation vs. Frequency Min C / Vctrl = 3V 25C / Vctrl = 3V C / Vctrl = 3V Figure 28. Worst-Case Return Loss (ATTEN_RF1 port) vs. Frequency over Temp Worst-Case RF1 Return Loss (db) C / Vctrl = V 25C / Vctrl = V C / Vctrl = V C 25C C Max. Figure 27. Min. and Max. Attenuation Slope vs. Frequency Min./Max. Atenuation Slope (db/v) Max. Slope Min. Slope Figure 29. Worst-Case Return Loss (ATTEN_RF2 port) vs. Frequency over Temp Worst-Case RF2 Return Loss (db) C C C Figure 3. Max. Insertion Phase Change vs. Frequency over Temp Max. Insertion Phase (deg) C 25C C (positive phase = electrically shorter) Integrated Device Technology, Inc. 14 March 23, 217

15 F248 Datasheet Typical Performance Characteristics 2 GHz Attenuator [6] Figure 31. Input IP3 vs. VCTRL over VMODE and Temperature Input IP3 (dbm) C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode= 3V 25C / Vmode= 3V C / Vmode= 3V Figure 33. Input IP2 vs. VCTRL over VMODE and Temperature Input IP2 (dbm) C / Vmode = 3V Figure nd Harmonic Input Intercept Point vs. VCTRL over VMODE and Temperature C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode = 3V 25C / Vmode = 3V Figure 32. Output IP3 vs. VCTRL over VMODE and Temperature Output IP3 (dbm) C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode= 3V 25C / Vmode= 3V C / Vmode= 3V Figure 34. Output IP2 vs. VCTRL over VMODE and Temperature Output IP2 (dbm) C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode = 3V 25C / Vmode = 3V C / Vmode = 3V Figure rd Harmonic Input Intercept Point vs. VCTRL over VMODE and Temperature IH2 (dbm) 1 9 IH3 (dbm) C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode = 3V 25C / Vmode = 3V C / Vmode = 3V C / Vmode = V 25C / Vmode = V C / Vmode = V -4C / Vmode = 3V 25C / Vmode = 3V C / Vmode = 3V Integrated Device Technology, Inc. March 23, 217

16 F248 Datasheet Typical Performance Characteristics 2 GHz Attenuator [7] Figure 37. Input IP3 vs. VCTRL over RF Port and Temperature Input IP3 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure 39. Input IP2 vs. VCTRL over RF Port and Temperature Input IP2 (dbm) C / RF2 Driven Figure nd Harm Input Intercept Point vs. VCTRL over RF Port and Temp C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven Figure 38. Output IP3 vs. VCTRL over RF Port and Temperature Output IP3 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure 4. Output IP2 vs. VCTRL over RF Port and Temperature Output IP2 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure rd Harm Input Intercept Point vs. VCTRL over RF Port and Temp IH2 (dbm) 1 9 IH3 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Integrated Device Technology, Inc. 16 March 23, 217

17 F248 Datasheet Typical Performance Characteristics 2 GHz Attenuator [8] Figure 43. Input IP3 vs. Attenuation over Temperature Input IP3 (dbm) C 4 25C C Figure 44. Output IP3 vs. Attenuation over Temperature Output IP3 (dbm) C 25C C Figure 45. Input IP2 vs. Attenuation over Temperature 12 Figure 46. Output IP2 vs. Attenuation over Temperature 12-4C Input IP2 (dbm) C 25C C Output IP2 (dbm) 25C 11 C Figure nd Harm Input Intercept Point vs. Attenuation over Temperature IH2 (dbm) Figure rd Harm Input Intercept Point vs. Attenuation over Temperature IH3 (dbm) C 3-4C 7 25C 2 25C 6 C C Integrated Device Technology, Inc. 17 March 23, 217

18 F248 Datasheet Typical Performance Characteristics 2 GHz Attenuator [9] Figure 49. Input IP3 vs. Attenuation over RF Port and Temperature Input IP3 (dbm) C / RF1 Driven 25C / RF1 Driven 4 C / RF1 Driven 35-4C / RF2 Driven 25C / RF2 Driven 3 C / RF2 Driven Figure 51. Input IP2 vs. Attenuation over RF Port and Temperature Input IP2 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure nd Harm Input Intercept Point vs. Attenuation over RF Port and Temp Figure 5. Output IP3 vs. Attenuation over RF Port and Temperature Output IP3 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure 52. Output IP2 vs. Attenuation over RF Port and Temperature Output IP2 (dbm) C / RF1 Driven 25C / RF2 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Figure rd Harm Input Intercept Point vs. Attenuation over RF Port and Temp IH2 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven IH3 (dbm) C / RF1 Driven 25C / RF1 Driven C / RF1 Driven -4C / RF2 Driven 25C / RF2 Driven C / RF2 Driven Integrated Device Technology, Inc. 18 March 23, 217

19 F248 Datasheet Typical Performance Characteristics Amplifier Wide Band Mode [1] Figure 55. Gain vs. Frequency over Temperature and Voltage WB mode 16 Figure 56. Reverse Isolation vs. Frequency over Temperature and Voltage WB Mode Gain (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Reverse Isolation (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 57. Input Match vs. Frequency over Temperature and Voltage WB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure nd Harmonic vs. Fundamental Freq over Temp and Voltage WB Mode Figure 58. Output Match vs. Frequency over Temperature and Voltage WB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 6. 3 rd Harmonic vs. Fundamental Freq over Temp and Voltage WB Mode C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Harmonic (dbc) Harmonic (dbc) Integrated Device Technology, Inc. 19 March 23, 217

20 F248 Datasheet Typical Performance Characteristics Amplifier Wide Band Mode [2] Figure 61. Output IP3 vs. Frequency over Temperature and Voltage WB Mode Figure 62. Output IP2H vs. Frequency over Temperature and Voltage WB Mode OIP3 (dbm) OIP2H (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V 35-4 C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 63. Output P1dB vs. Frequency over Temperature and Voltage WB Mode Figure 64. Noise Figure vs. Frequency over Temperature and Voltage WB Mode Compresssion (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Noise Figure (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Integrated Device Technology, Inc. 2 March 23, 217

21 F248 Datasheet Typical Performance Characteristics Amplifier Low Band Mode [1] Figure 65. Gain vs. Frequency over Temperature and Voltage LB mode 16 Figure 66. Reverse Isolation vs. Frequency over Temperature and Voltage LB Mode Gain (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Reverse Isolation (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 67. Input Match vs. Frequency over Temperature and Voltage LB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure nd Harmonic vs. Fundamental Freq over Temp and Voltage LB Mode Figure 68. Output Match vs. Frequency over Temperature and Voltage LB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 7. 3 rd Harmonic vs. Fundamental Freq over Temp and Voltage LB Mode C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Harmonic (dbc) Harmonic (dbc) Integrated Device Technology, Inc. 21 March 23, 217

22 F248 Datasheet Typical Performance Characteristics Amplifier Low Band Mode [2] Figure 71. Output IP3 vs. Frequency over Temperature and Voltage LB Mode 45 Figure 72. Output IP2H vs. Frequency over Temperature and Voltage LB Mode OIP3 (dbm) OIP2H (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V 35-4 C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 73. Output P1dB vs. Frequency over Temperature and Voltage LB Mode Compresssion (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Integrated Device Technology, Inc. 22 March 23, 217

23 F248 Datasheet Typical Performance Characteristics Amplifier High Band Mode [1] Figure 74. Gain vs. Frequency over Temperature and Voltage HB mode Figure 75. Reverse Isolation vs. Frequency over Temperature and Voltage HB Mode Gain (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Reverse Isolation (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 76. Input Match vs. Frequency over Temperature and Voltage HB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure nd Harmonic vs. Fundamental Freq over Temp and Voltage HB Mode Figure 77. Output Match vs. Frequency over Temperature and Voltage HB Mode Match (db) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure rd Harmonic vs. Fundamental Freq over Temp and Voltage HB Mode C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Harmonic (dbc) Harmonic (dbc) Integrated Device Technology, Inc. 23 March 23, 217

24 F248 Datasheet Typical Performance Characteristics Amplifier High Band Mode [2] Figure 8. Output IP3 vs. Frequency over Temperature and Voltage HB Mode 45 Figure 81. Output IP2H vs. Frequency over Temperature and Voltage HB Mode OIP3 (dbm) OIP2H (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V 35-4 C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Figure 82. Output P1dB vs. Frequency over Temperature and Voltage HB Mode Compresssion (dbm) C / 4.75 V -4 C / 5. V -4 C / 5.25 V +25 C / 4.75 V +25 C / 5. V +25 C / 5.25 V + C / 4.75 V + C / 5. V + C / 5.25 V Integrated Device Technology, Inc. 24 March 23, 217

25 F248 Datasheet Device Usage Table 8. Suggested Components for Optimum Linearity Performance of the Amplifier Band Frequency Range (MHz) Band_Select Pin 1 RSET Pin 12 to GND (kω) RDSET Pin 13 to GND (kω) Low Band 4 11 LB (Open) Mid Band HB (GND) High Band 22 3 HB (GND) Wide Band 4 3 HB (GND) Note: Mid Band and Wide Band use the same setting and component values. Table 9. Control Pins Usage for the TX VGA Pin Description Pin Input Level Function Band_Select 1 STBY 11 V MODE 22 Application Information Logic LOW Logic HIGH or Open Circuit Logic LOW or Open Circuit Logic HIGH Logic LOW Logic HIGH Improves higher frequency performance Improves lower frequency performance Amplifier Powered On Amplifier Power Savings Mode Negative Attenuation Slope V CTRL =. V results in insertion loss V CTRL = 2.8 V results in maximum attenuation Positve Attenuation Slope V CTRL = 2.8 V results in insertion loss V CTRL =. V results in maximum attenuation The F248 has been optimized for use in high performance RF applications from 4 to 3 MHz. STBY The STBY control pin allows for power saving when the device is not in use. Setting the STBY pin as a logic low or by leaving the pin open will produce a full current operation mode. The STBY pin has an internal 1 MΩ resistor to ground. Applying logic high to this pin will put the part in the power savings mode. Band_Select The Band_Select control pin can be used to boost the current in the device. This is typical done in the High Band and Wide Band frequency applications by grounding the Band_Select pin. Internally there is a 1.5 MΩ pull-up resistor to set this pin high if no connection is made to it. RSET and RDSET RSET (pin 12) and RDSET (pin 13) use external resistors to ground to set the DC current in the device and to optimize the linearity performance of the amplifier stage. The resistor values in Table 8 can be used as a guide for the RF band of interest. By decreasing the resistor value to ground on the RSET pin will increase the DC current in the amplifier stage. The maximum operating DC current through RSET should never be higher than 1.5mA at T EP= ºC. The resistor to ground on RDSET is used to optimize the linearity performance in conjunction with the resistor on RSET. C1 (pf) Icc (ma) 217 Integrated Device Technology, Inc. 25 March 23, 217

26 F248 Datasheet Application Information (Cont.) Amplifier Stability The standalone amplifier is not unconditionally stable. Set RS = 5 and R1 = 5 to makes the circuit unconditionally stable. By increasing RS from the EVKIT value of to 5 decreases the small signal gain by approx..5db and increases the NF by approx..5db. By changing R1 from an open to 5 decreases the small signal gain by approx..5db and decreases the OIP3 and OP1dB by approx..5db. ATTEN_RF1 and ATTEN_RF2 Ports The attenuator stage is bi-directional thus allowing ATTEN_RF1 or ATTEN_RF2 to be used as the RF input. As displayed in the Typical Operating Conditions curves, ATTEN_RF1 shows enhanced linearity. V CC must be applied prior to the application of RF power to ensure reliability. DC blocking capacitors are required on the RF pins and should be set to a value that results in a low reactance over the frequency range of interest. Attenuator Default Start-up The V CTRL pin has an internal pull-down resistor while V MODE does not have an internal pull-up or pull-down resistor and thus needs to be set externally. If V MODE is set to a logic LOW and V CTRL = V, the part will power up in the insertion loss state. If V MODE is set to a logic HIGH and V CTRL = V the part will power up in the maximum attenuation state. It is recommended that the user tie V MODE to either ground or logic HIGH. Ensure the V MODE and V CTRL pin voltages meet the dependencies to V CC as noted in the General Specifications Table during power up or under operation. V CTRL The V CTRL pin is used to control the attenuation of the attenuator stage. With V MODE set to a logic LOW (HIGH), this places the device in a negative (positive) slope mode where increasing (decreasing) the V CTRL voltage produces an increasing (a decreasing) attenuation from min attenuation (max attenuation) to max attenuation (min attenuation) respectively. See the General Specifications Table for the allowed control voltage range and its dependence on V CC. Apply V CC before applying voltage to the V CTRL pin to prevent damage to the on-chip pull-up ESD diode. If this sequencing is not possible, then set resistor R6 to 1k to limit the current into the V CTRL pin. V MODE The V MODE pin is used to set the attenuation vs. V CTRL slope. With V MODE set to logic LOW (HIGH) this will set the attenuation slope to be negative (positive). A negative (positive) slope is defined as increasing (decreasing) attenuation with increasing (decreasing) V CTRL voltage. The EVKit provides an on-board jumper to manually set the V MODE. Installing a jumper on header J4 from V MODE to GND (V IH) to set the device for a negative (positive) slope. Resistors R2 and R3 on the evaluation board form a voltage divider to establish a compatible logic HIGH level using the V CC supply as a source. The V MODE does not have an internal pull-up or pull-down resistor so it must be set externally. Power Supplies A common 5V power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than 1V / 2µs. In addition, all control pins should remain at V (±.3V) while the supply voltage ramps or while it returns to zero. 217 Integrated Device Technology, Inc. 26 March 23, 217

27 F248 Datasheet Control Pin Interface If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit at the input of each control pin is recommended. This applies to control pins 1, 11, 2, and 22 as shown below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity. For multiple devices driven by a single control line, values will need to be adjusted accordingly so as to not load the control line. Figure 83. Control Pin Components for Signal Integrity Control Integrated Device Technology, Inc. 27 March 23, 217

28 F248 Datasheet Evaluation Kit Picture Figure 84. Top View Figure 85. Bottom View 217 Integrated Device Technology, Inc. 28 March 23, 217

29 F248 Datasheet Evaluation Kit / Applications Circuit Figure 86. Electrical Schematic Note: RS and R1 are used to produce unconditional stability for the amplifier and are not included in the performance stated in this datasheet. See applications information section above. 217 Integrated Device Technology, Inc. 29 March 23, 217

30 F248 Datasheet Table 1. Bill of Material (BOM) Part Reference QTY Description Manufacturer Part # Manufacturer C1 1 9pF ±.25pF, 5V, CG Ceramic Capacitor (42) GRM55C1H9RC Murata C2, C9 2 1pF ±5%, 5V, CG Ceramic Capacitor (42) GRM55C1H11J Murata C3 1 1µF ±2%, 6.3V, X5R Ceramic Capacitor (63) GRM188R6J16M Murata C4 1 47pF ±5%, 5V, CG Ceramic Capacitor (42) GRM55C1H47J Murata C5, C7, C1 3 1pF ±5%, 5V, CG Ceramic Capacitor (42) GRM55C1H12J Murata C6, C8 2 1nF ±5%, 5V, X7R Ceramic Capacitor (63) GRM188R71H13J Murata C11 1.1µF ±1%, 16V, X7R Ceramic Capacitor (42) GRM5R71C14K Murata RS [a] 1 ±1%, 1/1W, Resistor (42) ERJ-2GERX Panasonic R1 [a] Not Installed R2, R3 2 1k ±1%, 1/1W, Resistor (42) ERJ-2RKF13X Panasonic R4 Not Installed R5, R6, R7, R11, R13 5 ±1%, 1/1W, Resistor (42) ERJ-2GERX Panasonic R k ±1%, 1/1W, Resistor (42) ERJ-2RKF642X Panasonic R k ±1%, 1/1W, Resistor (42) ERJ-2RKF241X Panasonic R1, R12 Not Installed, Alternate 1 Bias Resistor (42) R14, R Not Installed, Alternate 2 Bias Resistor (42) R16, R17 Not Installed, Alternate 3 Bias Resistor (42) TP1 TP5 5 Test Point 521 Keystone Electronics J1, J2, J3, J5, J6, J7 6 SMA End-Launch (small) Emerson Johnson J4 1 CONN HEADER VERT SGL 3 POS GOLD AR 3M J8, J9 2 CONN HEADERS VERT SGL 2 POS GOLD AR 3M J1, J x 4 HEADER VERT HLF FCI U1 1 RF Amplifier / VVA F248NBGI IDT 1 Printed Circuit Board F248 PCB IDT a. The data included in this datasheet does not include these as stability resistors. For the amplifier to be unconditionally stable RS and R1 must be installed. See the Applications Section for more details. 217 Integrated Device Technology, Inc. 3 March 23, 217

31 F248 Datasheet Evaluation Kit Operation Below is a basic setup procedure for configuring and testing the F248 EVKit. Pre-Configure EVKit: The section is a guide to setup the EVKit for testing. Remove the J8 header shunt if the application is for low band operation. All other operating bands require the J8 shunt to be installed. Remove any shorting shunt from header J9 which will allow the part to be in the operating mode when powered up. Verify that there is a shunt between pins 1, 2 of J11 and pins 1, 2 of J1. These pins configure the PCB to use the installed bias resistors to support Mid Band and Wide Band (see Table 8). Alternate resistors can be installed on the unpopulated resistor slots on J11 and J1 to support the other operating bands (see Additional EVKit Information section). If a negative (positive) attenuator control slope is desired, connect a shunt between pins 1 and 2 (2 and 3) of header J4. Power Supply Setup: Without making any connections to the EVKit, setup one fixed power supply for 5V with a current limit of 16mA and one variable supply set to V with a current limit of 1mA. Disable both power supplies. RF Test Setup: Set up the RF test set to the desired frequency and power ranges within the specified operating limits noted in this datasheet. Disable the output power of all the RF sources. Connect EVKit to Test setup: With the RF sources and power supplies disabled connect the fixed 5V power supply to connector J3, the variable supply to J6 and the RF connections to the desired RF ports. Terminate any unused RF ports (J1, J2, J5, J7) into 5. Powering Up the EVkit: Enable the 5V supply and observe a DC current of approx. 12mA. Enable the variable supply. Enable the RF sources. Verify that the DC current stays about 12mA to verify that the amplifier is not being over driven by RF input power. If the J4 connection is set for a negative (positive) attenuation slope then increasing the variable supply with produce increased (decreased) attenuation for the attenuator path (J2 to J7). Powering Down the EVkit: Disable the RF power being applied to the device. Adjust the variable supply down to V and disable it. Disable the 5V supply. Disconnect EVKit from the RF test stand. Additional EVKIT Information EVKit modification to support additional Table 8 bias settings: The standard EVKit is setup for only one RSET / RDSET bias setting (pins 12/ 13 on the F248) noted in Table 8. Additional Table 8 values (R12/R1, R/R14, R17/ R16) can be installed on the board to allow for different jumper settings. Never have two shunts installed at the same time on header J11 since this may produce excessive bias current and damage the part. As the resistance to ground decreases on pin 12 of the device, the DC current will increase. The DC current of the EVKIT should never exceed 25mA. 217 Integrated Device Technology, Inc. 31 March 23, 217

32 F248 Datasheet Package Drawings Figure 87. Package Outline Drawing (5 x 5 x.75 mm 32-pin TQFN), NBG Integrated Device Technology, Inc. 32 March 23, 217

33 F248 Datasheet Recommended Land Pattern Figure 88. Recommended Land Pattern 217 Integrated Device Technology, Inc. 33 March 23, 217

34 F248 Datasheet Ordering Information Orderable Part Number Package MSL Rating Shipping Packaging Temperature F248NBGI 5 x 5 x.75 mm 32-TQFN 1 Tray -4 to + C F248NBGI8 5 x 5 x.75 mm 32-TQFN 1 Tape and Reel -4 to + C F248EVBI Evaluation Board Marking Diagram IDT F248NBGI Z3L Line 1 - Company. Line 2 - Product Number. Line 3 - Z the initial alpha characters are the ASM Test Step. Line 3-3 is two digits for the year and week that the part was assembled (2, Week 3). Line 3 - L or last alpha characters are the Assembler Code. Line 4 - Near Dot Lot Code. Q32A16Y Revision History Revision Date March 23, 217 Initial release. Description of Change Corporate Headquarters 624 Silver Creek Valley Road San Jose, CA Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as IDT ) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. 217 Integrated Device Technology, Inc. 34 March 23, 217