7-Bit 0.25 db Wideband Digital Step Attenuator FEATURES FUNCTIONAL BLOCK DIAGRAM RF 1 RF 2. Part# Tape & Reel

Transcription

1 F956 Datasheet 7-Bit.5 db Wideband Digital Step Attenuator to 6 MHz GENERAL DESCRIPTION This document describes the specification for the F956 Digital Step Attenuator. The F956 is part of IDT s Glitch-Free TM family of DSAs optimized for the demanding requirements of Base Station (BTS) radio cards and numerous other non-bts applications. This device is offered in compact 5 mm x 5 mm 3-pin package with 5 input and output impedance for ease of integration into the radio or RF system. COMPETITIVE ADVANTAGE The F956 offers very high reliability due to its construction from a monolithic silicon die in a QFN package. The insertion loss is very low with minimal distortion. Additionally the device is designed to have extremely accurate attenuations levels. These accurate attenuation level improves system SNR and/or ACLR by ensuring system gain is as close to targeted level as possible. Also, the very fast settling time in parallel mode is ideal for fast switching systems. Finally, the device is Glitch-Free TM with less than db of ringing across the attenuation range in stark contrast to competing DSAs that glitch as much as db during MSB state changes. Lowest insertion loss for best SNR Glitch-Free TM technology to protect PA or ADC during transitions between attenuation states. Extremely accurate attenuation levels Ultra low distortion MSL and V HBM ESD ORDERING INFORMATION F956NBGI8 Green Tape & Reel FEATURES Serial & 7-bit Parallel Interface 3.75 db Range.5 db steps Glitch-Free TM : low transient overshoot 5 ns settling time Ultra linear > 6 dbm IIP3 Low Insertion Loss <.7 GHz Attenuation error < ±. GHz Bi-directional RF use 3.3 V or 5 V Supply.8 V or 3.3 V control logic Low Current Consumption: 35 μa typical - C to +5 C operating temperature 5 mm x 5 mm Thin QFN 3 pin package FUNCTIONAL BLOCK DIAGRAM RF RF Bias V MODE Part# Details Part# Freq Range (MHz) Decoder D[6:] A[:] Resolution / Range (db) Glitch-Free TM SPI CLK DATA LE Control F / 3.75 Parallel & Serial F / 3.5 F95.5 / 5.5 Serial Only Serial Only F953.5 / 3.5 Parallel & Serial F / 3.75 Parallel & Serial F9.5 / 3.5 Parallel & Serial IL (db).3 Pinout PE37 PE37. HMC35.9 HMC PE3 DAT-3R5 PE375, PE37, RFSA375 PE3 PE3 F956, Rev /8/6 6 Integrated Device Technology, Inc.

2 F956 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to V DD V D[6:], DATA, CLK, LE, A, A, A, V MODE VCNTL -.3 Min (V DD +.3, 3.9) RF, RF V RF V Maximum Input Power applied to RF or RF (> MHz) P RF +3 dbm Operating Case Temperature 5 C Continuous Power Dissipation.5 W Maximum Junction Temperature TJ max +5 C Storage Temperature Range T ST C Lead Temperature (soldering, s) T LEAD +6 C Electrostatic Discharge HBM (JEDEC/ESDA JS--) ESD Voltage CDM (Per JESD-CF) V ESDHBM V ESDCDM 5 (Class C) 5 (Class C) V V V Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. PACKAGE THERMAL AND MOISTURE CHARACTERISTICS θ JA (Junction Ambient) θ JC (Junction Case) [The Case is defined as the exposed paddle] Moisture Sensitivity Rating (Per J-STD-) MSL C/W C/W 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

3 Max CW P IN (dbm) F956 F956 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions Min Typ Max Units Supply Voltage(s) V DD V Operating Temperature Range T CASE Case Temperature - +5 C Frequency Range F RF 6 MHz RF CW Input Power P CW RF or RF RF Peak Input Power P peak RF Port, V DD = 3.3V, T CASE = 85 C, F RF > 5 MHz, WCDMA, 3GPP, Downlink, 6 DPCH, Chip rate =3.8 MSPS, Avg. Pin = + dbm See Figure % 8.9. % 3.7 % 3.3 % 33. RF Source Impedance Z RFI Single Ended 5 Ω RF Load Impedance Z RFO Single Ended 5 Ω dbm dbm Frequency (MHz) Figure - Maximum Operating RF input power vs Input frequency Rev /8/6 3 7-Bit.5 db Wideband Digital Step Attenuator

4 F956 F956 SPECIFICATION Specifications apply at V DD = +3.3 V, T CASE = +5 C, F RF = GHz,.5 db steps unless otherwise noted. Minimum Attenuation D[6:] = [], Maximum Attenuation D[6:] = [], EVKit losses are de-embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Logic Input High Logic Input Low V IH V IL CLK, LE, DATA, D[6:], A, A, A, V MODE 3. V V DD 3.6 V.7 V DD 3.6 V < V DD CLK, LE, DATA, D[6:], A, A, A, V MODE V.63 V Logic Current I IH, I IL Individual Pins - + μa Supply Current I DD 35 8 μa Attenuation Range ATT RNG No missing codes 3.75 db Minimum Gain Step DSA Settling time Video Feedthrough RF, RF ports LSB SET VID FT F RF.5 GHz.5 F RF 6.5 GHz.5 F RF 8.5 GHz. Max to Min Attenuation to settle to within.5 db of final value Min to Max Attenuation to settle to within.5 db of final value Measured at RF ports with.5 ns risetime, to 3.3 V control pulse.9.8 db s mv pp Maximum spurious level on any RF port Spur MAX Spur Freq ~. MHz - dbm Serial Clock Speed F CLK SPI 3 wire bus 5 MHz Parallel to Serial Setup A SPI 3 wire bus ns Serial Data Hold Time B SPI 3 wire bus ns LE Delay C SPI 3 wire bus Time from final serial clock rising edge ns Maximum Switching Rate SW RATE 5 khz Specification Notes: Note : Items in min/max columns in bold italics are Guaranteed by Test. Note : Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3. The input. db compression point is used as a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from RF CW Power (Figure ) and the RF Average Power (Recommended Operating Conditions Table).. Note : Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is. MHz. 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

5 F956 F956 SPECIFICATION (CONTINUED) Specifications apply at V DD = +3.3 V, T CASE = +5 C, F RF = GHz,.5 db steps unless otherwise noted. Minimum Attenuation D[6:] = [], Maximum Attenuation D[6:] = [], EVKit losses are de-embedded unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Insertion Loss Relative Phase (Amin vs. Amax) Step Error (Differential Non-Linearity) Absolute Attenuation Error (Integral Non-Linearity) IL ΦΔ DNL INL Input Return Loss S Output Return Loss S Input IP3 IIP3 MHz < F RF GHz.3.8 GHz < F RF 3 GHz GHz < F RF GHz.6. GHz < F RF 5 GHz..6 5 GHz < F RF 6 GHz.6 3. F RF = GHz F RF = GHz 5 F RF = GHz 55 F RF = 6 GHz 9 Max error between adjacent steps Max Error for state 9.75 db, FRF = GHz Max Error, over all states F RF = GHz db deg..9 db MHz < F RF GHz 5 GHz < F RF GHz 5 GHz < F RF 6 GHz 7 MHz < F RF GHz 8 GHz < F RF GHz 6 GHz < F RF 6 GHz 7 P IN = + dbm per tone 5 MHz Tone Separation Attn = db 6 Attn = 5.75 db 6 Attn = 3.75 db 6 Attn = db P IN = + dbm per tone MHz Tone Separation F RF =.7 GHz F RF =.8 GHz F RF =. GHz 6 6. F RF =.6 GHz Input.dB Compression 3 P.dB F RF = GHz, Attn = db 3.5 dbm Specification Notes: Note : Items in min/max columns in bold italics are Guaranteed by Test. Note : Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3. The input. db compression point is used as a linearity figure of merit. The recommended maximum input power is specified as the lesser of the two values from RF CW Power (Figure ) and the RF Average Power (Recommended Operating Conditions Table).. Note : Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is. MHz. db db db dbm dbm Rev /8/6 5 7-Bit.5 db Wideband Digital Step Attenuator

6 F956 PROGRAMMING OPTIONS F956 can be programmed using either the parallel or serial interface; selectable via V MODE (pin 3). Serial mode is selected by floating V MODE or pulling V MODE to a logic high and parallel mode is selected by setting V MODE to logic low. SERIAL CONTROL MODE F956 Serial mode is selected by floating V MODE (pin 3) or pulling it to logic high. The serial interface is a 6-bit shift register made up of two words. The first 8-bit word is the Attenuation word, which controls the DSA state. The second word is the address word, which uses only 3 of 8-bits that must match the hard wired A-A programming in order to change the DSA state. If no external connections are made to A A then internally they will default to due to internal pull down resistors. If these 3 external preset address bits are not matched with the SPI loaded address bits then the current attenuator state will remain unchanged. This allows up to 8 serial-controlled devices to be used on a single board, which share a common DATA, CLK and LE. When serial programming is used, all the parallel control input pins 6 3 can be left open or grounded. If a pin is grounded then an additional 5 µa will be drawn from the voltage supply per pin. Set to either Logic High or Low Set to Logic Low MSB (Last In) LSB (First In) Q5 Q Q3 Q Q Q Q9 Q8 Q7 Q6 Q5 Q Q3 Q Q Q A7 A6 A5 A A3 A A A D7 D6 D5 D D3 D D D 8-Bit Address Word 8-Bit Attenuation Word Figure -Two 8-bit words are comprised of 6bit serial in, parallel out shift register Table -Truth Table for the Serial Address Word A7 (MSB) A6 A5 A A3 A A A Address Setting X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 7-Bit.5 db Wideband Digital Step Attenuator 6 Rev /8/6

7 F956 Table - Truth Table for the Serial Control Word D7 D6 D5 D D3 D D D (LSB) Attenuation (db) SERIAL MODE DEFAULT CONDITION When the device is first powered up it will default to the Maximum Attenuation setting as described below: Note that for the F956 in all cases logic high () has the attenuation stepped IN, while logic low () has the attenuation stepped OUT. MSB (Last In) LSB (First In) Q5 Q Q3 Q Q Q Q9 Q8 Q7 Q6 Q5 Q Q3 Q Q Q A7 A6 A5 A A3 A A A D7 D6 D5 D D3 D D D X X X X X 8-Bit Address Word 8-Bit Attenuation Word Figure 3 -Default register settings set for max attenuation and Address Word REGISTER TIMING DIAGRAM: (NOTE THE TIMING SPEC INTERVALS IN BLUE) With serial control, the F956 can be programmed via the serial port on the rising edge of Latch Enable (LE) which loads the last 8 DATA line bits [formatted LSB (D) first] resident in the SHIFT register followed by the Address Word into the ACTIVE register. Rev /8/6 7 7-Bit.5 db Wideband Digital Step Attenuator

8 F956 Reinsert Figure - Serial Timing Diagram Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch enable be left high when the device is not being programmed. Interval Symbol t ps Table 3 - Serial Mode Timing Table Description Parallel to Serial Setup Time - From rising edge of Vmode to rising edge of CLK for D5 Min Spec Max Spec Units ns t p Clock high pulse width ns t cls LE Setup Time - From the rising edge of CLK pulse for D to LE rising edge minus half the clock period. ns t lew LE pulse width 3 ns t dst t dht Data Setup Time - From the starting edge of Data bit to rising edge of CLK Data Hold Time - From rising edge of CLK to falling edge of the Data bit. ns ns PARALLEL CONTROL MODE For the F956 the user has the option of running in one of two parallel modes. Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when V MODE is a logic low and LE is a logic high. In this mode the device will immediately react to any voltage changes to the parallel control pins [pins 6 3]. Use direct parallel mode for the fastest settling time. 7-Bit.5 db Wideband Digital Step Attenuator 8 Rev /8/6

9 F956 Latched Parallel Mode: Latched Parallel Mode is selected when V MODE is logic low and LE is toggled from logic low to high. To utilize Latched Parallel Mode: Set V MODE is logic low. Set LE to logic low. Adjust pins [6, 7, 8, 9, 3, 3, 3] to the desired attenuation setting. (Note the device will not react to these pins while LE is a logic low). Pull LE to a logic high. The device will then transition to the attenuation settings reflected by pins D6 - D. IF LE is pulled to a logic low then the attenuator will not change state. Latched Parallel Mode implies a default state for when the device is first powered up with V MODE set for logic low and LE logic low. In this case the default setting is MAXIMUM Attenuation. Table - Truth Table for the Parallel Control Word D6 D5 D D3 D D D Attenuation (db) Figure 5 - Latched Parallel Mode Timing Diagram Rev /8/6 9 7-Bit.5 db Wideband Digital Step Attenuator

10 F956 Table 5 - Latched Parallel Mode Timing Interval Min Max Description Symbol Spec Spec Units t sps Serial to Parallel Mode Setup Time ns t pdh Parallel Data Hold Time ns t le LE minimum pulse width ns t pds Parallel Data Setup Time ns TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.. V DD = +3.3 V. T CASE = +5 C 3. 5 MHz Tone Space. Serial Control 5. P IN = dbm 6. RF is the input port 7. Attenuation Setting = db 8. EVKit losses (traces and connectors) are fully de-embedded 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

11 F956 TYPICAL OPERATING CONDITIONS (- -) Insertion Loss vs Frequency Insertion Loss vs Attenuation 3. GHz, - C 3. GHz, +5 C - Insertion Loss (db) Insertion Loss (db) GHz, +5 C C - +5 C C Frequency (GHz) Attenuation (db) Input Return Loss vs Attenuation Match(dB) Match (db) Input Return Loss vs Frequency [All States] - -5 GHz. GHz.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz Frequency (GHz) Attenuation (db) Output Return Loss vs Frequency [All States] Output Return Loss vs Attenuation Match (db) Match (db) GHz.5 GHz. GHz.5 GHz 3. GHz 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz GHz Frequency (GHz) Rev /8/ Attenuation (db) 7-Bit.5 db Wideband Digital Step Attenuator

12 Error (db) Error (db) Error (db) Error (db) Error (db) Error (db) F956 TYPICAL OPERATING CONDITIONS (- -) Worst Case Absolute Accuracy (LSB=.5 db) Absolute Accuracy (LSB=.5 db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz) GHz. GHz.5 GHz. GHz.5 GHz GHz 3.5 GHz. GHz.5 GHz Attenuation (db) Worst Case Absolute Accuracy (LSB=.5 db) Absolute Accuracy (LSB=.5 db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz) GHz. GHz.5 GHz. GHz.5 GHz 3. GHz GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz Attenuation (db) Worst Case Absolute Accuracy (LSB=. db) Absolute Accuracy (LSB=. db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz) GHz. GHz.5 GHz. GHz.5 GHz 3. GHz GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz Attenuation (db) 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

13 Error (db) Error (db) Error (db) Error (db) Error (db) Error (db) F956 TYPICAL OPERATING CONDITIONS (- 3 -) Worst Case Step Accuracy (LSB=.5 db) Step Accuracy (LSB=.5 db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz).5 GHz. GHz.5 GHz. GHz.5 GHz. 3. GHz 3.5 GHz. GHz.5 GHz Attenuation (db) Worst Case Step Accuracy (LSB=.5 db) Step Accuracy (LSB=.5 db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz).5.5 GHz. GHz.5 GHz. GHz.5 GHz 3. GHz. 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz Attenuation (db) Worst Case Step Accuracy (LSB=. db) Step Accuracy (LSB=. db) C Min - C Max +5 C Min +5 C Max +5 C Min +5 C Max Frequency (GHz).5 GHz. GHz.5 GHz. GHz.5 GHz 3. GHz. 3.5 GHz. GHz.5 GHz 5. GHz 5.5 GHz 6. GHz Attenuation (db) Rev /8/6 3 7-Bit.5 db Wideband Digital Step Attenuator

14 F956 TYPICAL OPERATING CONDITIONS (- -) Relative Insertion Phase vs Attenuation Phase (degrees) Phase (degrees) Relative Insertion Phase vs Frequency [All States] GHz 5.5 GHz 6. GHz 3.5 GHz 5. GHz 3. GHz.5 GHz 5.5 GHz. GHz 6. GHz 3.5 GHz 7.5 GHz Frequency (GHz) Attenuation (db) Input Compression (at GHz, Attn=6 db) Compression (db) Compression (db) Input Compression (at GHz, Attn= db) C +5 C -. - C +5 C C C Input Power (dbm)..3.3 Compression (db) C +5 C -. 6 Input Compression (at GHz, Attn=3.75 db) Input Power (dbm) Input Compression (at GHz, Attn= db) Compression (db) C +5 C C C Input Power (dbm) 7-Bit.5 db Wideband Digital Step Attenuator Input Power (dbm) Rev /8/6

15 Input IP3 (dbm) Input IP3 (dbm) Input IP3 (dbm) Compression (db) Compression (db) F956 TYPICAL OPERATING CONDITIONS (- 5 -) Input Compression (+5 C, GHz) Input Compression (+5 C, 6 GHz) GHz db GHz db GHz 8 db GHz 6 db GHz db 6 GHz db 6 GHz 8 db 6 GHz 6 db Input Power (dbm) Input Power (dbm) Input IP3 vs Attenuation [ GHz] Input IP3 vs Attenuation [3.9 GHz] C / Pin = dbm/tone - C / Pin = 5 dbm/tone 5 +5 C / Pin = dbm/tone +5 C / Pin = 5 dbm/tone +5 C / Pin = dbm/tone +5 C / Pin = 5 dbm/tone Attenuation (db) Attenuation (db) Input IP3 vs Frequency [Attn= db, Pin=+ dbm] IIP3-HS IIP3-LS Frequency (GHz) Rev /8/6 5 7-Bit.5 db Wideband Digital Step Attenuator

16 F956 PACKAGE DRAWING 5mm x 5mm 3-pin TQFN), Use Exposed PAD (EPAD) Option P 7-Bit.5 db Wideband Digital Step Attenuator 6 Rev /8/6

17 F956 LAND PATTERN DIMENSION PIN DIAGRAM TOP View (looking through the top of the package) NC CLK VDD LE V_MODE A 3 5 F956 Exposed pad () A A NC 6 RF 7 RF D D D D3 D D5 D6 DATA Rev /8/6 7 7-Bit.5 db Wideband Digital Step Attenuator

18 F956 PIN DESCRIPTION Pin Name Function DNC This pin must be left open. VDD Main Supply. Use 3.3 V or 5 V. Bypass capacitor as close to pin as possible. 3 V MODE A Address bit A connection. Logic low for parallel mode. Logic high or NC for serial mode. 5 Connect directly to paddle ground or as close as possible to pin with thru via. This pin is not internally connected 6 Connect directly to paddle ground or as close as possible to pin with thru via. 7 RF 3 Device RF input or output (bi-directional). AC couple to this pin unless V DC. 8 7 Connect each pin directly to paddle ground or as close as possible to pin with thru vias. 8 RF 3 Device RF input or output (bi-directional). AC couple to this pin unless V DC. 9 Connect directly to paddle ground or as close as possible to pin with thru via. NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). A Address bit A connection A Address bit A connection. 3 LE Serial interface latch enable input. CLK Serial interface clock input. 5 DATA Serial interface data input. 6 D6 Parallel control bit, 6 db. Ground pin if not used. 7 D5 Parallel control bit, 8 db. Ground pin if not used. 8 D Parallel control bit, db. Ground pin if not used. 9 D3 Parallel control bit, db. Ground pin if not used. 3 D Parallel control bit, db. Ground pin if not used. 3 D Parallel control bit,.5 db. Ground pin if not used. 3 D Parallel control bit,.5 db. Ground pin if not used. EP Exposed Paddle Connect to Ground with multiple vias for good thermal and RF performance. 7-Bit.5 db Wideband Digital Step Attenuator 8 Rev /8/6

19 F956 EVKIT PICTURE Rev /8/6 9 7-Bit.5 db Wideband Digital Step Attenuator

20 D 3 D 3 D 3 D3 9 D 8 D5 7 D6 6 DATA 5 F956 EVKIT / APPLICATIONS CIRCUIT J HEADER R C C 3 J6 5 R7 C7 C8 R C3 VDD R3 C R C5 R5 C6 R6 C7 R7 C8 3 5 SW pin DIP Swtich R8 R9 C9 C TP VDD J R C R U NC VDD V_MODE A RF PAD C F956 C9 HEADER x J R6 R5 C CLK LE 3 A A NC 9 RF 8 7 R6 - kohms % R5-6 kohms % J VDD HEADER x C5 3 5 J8 HEADER x J HEADER x J9 3 5 J Thru Cal 3 5 J3 J3 HEADER x J R R3 R C6 C C 3 5 J5 3 HEADER 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

21 F956 EVKIT BOM (REV ) Item # Part Reference QTY DESCRIPTION Mfr. Part # Mfr. C - C, C, C5, C6 pf ±5%, 5 V, CG Ceramic Capacitor () C8, C, C 3 pf ±5%, 5 V, CG Ceramic Capacitor () GRM555CHJ GRM555CHJ MURATA MURATA 3 C7, C9, C 3 nf ±5%, 5 V, X7R Ceramic Capacitor (63) GRM88R7H3J MURATA R7 Ω Resistors () ERJ-GERX PANASONIC 5 R - R Ω ±%, / W, Resistor () ERJ-RKFX PANASONIC 6 R kω ±5%, / W, Resistor () ERJ-RKF698X PANASONIC 7 R6 kω ±%, / W, Resistor () ERJ-RKFX PANASONIC 8 J3, J7, J9, J, J 5 CONN HEADER VERT SGL X POS GOLD 96-6-AR 3M 9 J5 CONN HEADER VERT SGL X POS GOLD 96-6-AR 3M J CONN HEADER VERT SGL X POS GOLD 96-6-AR 3M J, J, J6, J8, J, J3 6 Edge Launch SMA (.375 inch pitch ground, tab) Emerson Johnson SW SWITCH POSITION DIP SWITCH KATE E-Switch 3 U DSA F956 IDT Printed Circuit Board F955 EVKit Rev IDT TOP MARKINGS ASM Test Step IDT F956NBGI ZA55G QA6MY Lot Code Part Number Assembler Code Date Code [YYWW] (Week 5 of 5) Rev /8/6 7-Bit.5 db Wideband Digital Step Attenuator

22 F956 APPLICATIONS INFORMATION Power Supplies A common V DD power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply voltage change or transients should have a slew rate smaller than V/uS. In addition, all control pins should remain at V (+/-.3V) while the supply voltage ramps or while it returns to zero. Digital Pin Voltage & Resistance Values The following table provides open-circuit DC voltage referenced to ground and resistance values for each of the control pins listed. Pin Name Open Circuit DC Voltage 3 V MODE.5 V Internal Connection kω pullup resistor to internally regulated.5 V,, A, A, A V kω resistor to 3,, 5 LE, CLK, DATA.5 V 6 3 D6 D.5 V kω pullup resistor to internally regulated.5 V kω pullup resistor to internally regulated.5 V 7-Bit.5 db Wideband Digital Step Attenuator Rev /8/6

23 F956 REVISION HISTORY SHEET Rev Date Page Description of Change O 5-May- Initial Release 5-Sep-9 Datasheet Format Update Added Maximum Average Power Rating 6-Apr- Maximum operating frequency changed to 6 GHz. Added curves showing performance at higher frequencies. Corporate Headquarters 6 Silver Creek Valley Road San Jose, CA 9538 USA Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Copyright 6. Integrated Device Technology, Inc. All rights reserved. 7-Bit.5 db Wideband Digital Step Attenuator 3 Rev /8/6

24 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology): F956NBGI F956NBGI8