NJU7380 STEPPER MOTOR CONTROLLER

Transcription

1 PER TOR CTROER GENERA DESCRIPTI NJU7380 is a translator to convert the signal of the & input method into Phase signal. It can control the stepping motor driver with & input signal to Phase input methods such as NJM3775, NJM3777. NJU7380 is also including Auto Current Down() circuit witch is suitable for reducing power dissipation of power devices and motor. PACKAGE OUTINE NJU7380M FEATURES Operating Voltage 4.75V to 5.25V Internal Phase ogic Circuit Phase ogic Reset Function () Motor Origin Monitor Function () alf / Full Step Mode Select (SM) Auto Current Down Function () Specially matched to NJM37XX series Package DM4 BOCK DIAGRAM VDD POR SM SGND Phase ogic & ogic PGND - 1 -

2 PIN CNECTI 1 14 VDD 2 13 SM SGND 7 8 PGND DM4 PIN FUNCTI IST No. Pin Name Description 1 Direction command input for determining motor turning direction 2 Motor steeping pulse input, phase logic operation triggered by negative edge of signal 3 SM alf / Full step mode select input level in full step mode and level in half step mode 4 Phase logic initial input 5 Phase output initial status detection output 6 A value of connected capacitor determines lock detection time (t on ) and auto resume time (t ) 7 SGND 8 PGND SGND (ogic GND) and PGND (Analog GND) is not connect in the IC SGND and PGND pins should be connected ground respectively. Auto Current Down output terminal level in active Step sequence output terminals /(/) determine a sequence output on Phase1(2) for driver IC () determine a motor current direction on Phase1(2) for driver IC () determine a phase current mode at the half-step 14 VDD ogic power supply voltage terminal - 2 -

3 ABSOUTE MAXIMUM RATINGS (Ta=25 C) PARAMETER SYMBO RATINGS UNIT NOTE Supply Voltage V DD +7.0 V Input Voltage V ID -0.3 V DD +0.3 V Output Current I O 10 ma Operating Temperature Range T opr ºC Storage Temperature Range T stg ºC Power Dissipation P D 300 mw Device itself RECOMMENDED OPERATING CDITI V DD = 4.75V to 5.25V EECTRICA CARACTERISTICS (V DD =5V, Ta=25ºC) PARAMETER SYMBO TEST CDITI MIN. TYP. MAX. UNIT Quiescent Current I DD No Signal ma evel Input Voltage V I V evel Input Voltage V I V evel Input Current I I µa evel Input Current I I µa Phase Output V P I P =5mA V DIS Output V DIS I DIS =5mA V Output V I =5mA V Output V I =5mA V Output eak Current I EAK V DD =7V µa Auto Current Down Time t C T =0.068µF ms Turn Time t d R =1kΩ µs Set-up Time t S ns Step-pulse Continuation Time t p ns - 3 -

4 APPACATI CIRCUIT V CC (+5V) V MM 4.7µF R3 R1 10kΩ 10kΩ 10kΩ 10kΩ 10kΩ 0.1µF + 10µF VDD V CC V MM1 V MM2 Pulse Direction Select alf / Full Select NJU SM 7380 SGND PGND Phase1 Dis1 V R1 Phase2 Dis2 NJM3775 V R2 RC GND C 1 E 1 C 2 E 2 M A1 M B1 M A2 M B2 PER TOR GND(V CC ) R2 +5V 12Ω 4700pF RS 0.47Ω RS 0.47Ω GND(V MM ) FUNCTI DESCRIPTI NJU7380 is a controller for driver of 2-phase stepper motor. It can control the stepping motor driver with & input signal to Phase input methods such as NJM3775, NJM3777. NJU7380 is also including Auto Current Down() circuit witch is suitable for reducing power dissipation of power devices and motor. OGIC BOCK NJU7380 contains all phase logic necessary to control the motor in a proper way. If any of the logic inputs are left open, the circuit will accept it as a IG level. In order to make noise-proof nature into the maximum, it is necessary to connect an idle input terminal to V DD level. Stepping pulse The built-in phase logic sequencer counts up on every negative edge of the signal (pulse). In full step mode, the pulse turns the stepping motor at the basic step angle. In half step mode, two pulses are required to turn the motor at the basic step angle. The (direction) signal and SM (half/full mode) are latched to the negative edge and must therefore be established before the start of the negative edge. Note the setup time ts in Figure 1. Direction The signal determines the step direction. The direction of the stepping motor depends on how the NJU7380 and the driver are connected to the motor. Although can be modified this should be avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge

5 SM alf / Full step mode select This signal determines whether the stepping motor turns at half step or full step mode. The built-in phase logic is set to the half step mode when SM is low level. Although SM can be modified this should be avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every eight pulses in the half step mode. forces to initialize the phase logic to sequence start mode. When is at level, the phase logic is initialized and the energizing pattern of phase logic at sequence start is output. At this time, the input of phase logic will be ignored during the is at level. SM,, t S t P V P t d Fig 1 : Timing chart POR Power on and reset function The internal power-on and reset circuit, which is connected to V DD, resets the phase logic and turns off phase output when the power is supplied to prevent missteps. Each time the power is turned on, the energizing pattern of phase logic at sequence start is output. Origin monitor At sequence start of the phase logic or after POR or external, an level output is made to indicate to external devices that the energizing sequence is in initial status. In a system using a stepping motor, the device sensor and the AND function enable a higher resolution detection of motor origin

6 Auto Current Down function The monitors step signals and sets the pin output to when the negative edge of a signal is input. It then sets the output to after a time (t ) that is fixed by the capacitor that is connected to the pin. By combining this pin with the VR pin that determines motor current for the motor, it is possible to reduce current when stopping the motor. If the next negative edge of a is input during the time t, an internal retrigger will operate, maintaining the pin's output. That is, after the final negative edge of a is input, output is maintained during the time t, after which it is set to. The time t must be long enough to securely stop the stepping motor. Approximately 100mS is usually sufficient for normal applications. The following expression determines the time t. t [ms] = [F] t t Normal Revolution State Operation State Fig2 : Operation Timing Diagram - 6 -

7 INPUT / OUTPUT SEQUENCE It is timing chart of the input / output signal in each drive mode. The state of the input / output signal after POR is shown in left side. Full-step mode Forward 4-step sequence SM Full-step mode Reverse 4-step sequence SM alf-step mode Forward 8-step sequence SM alf-step mode Reverse 8-step sequence SM [CAUTI] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights