NJU7388B. 3-PHASE BRUSHLESS DC MOTOR CONTROL IC with 150 SQUARE WAVE

Transcription

1 3-PHASE BRUSHLESS DC MOTOR CONTROL IC with 150 SQUARE WAVE NJU7388B GENERAL DESCRIPTION The NJU7388B is a 3-phase brushless DC motor controller with 150º commutation and lead angle control functions, which provides low vibration, low noise and high efficiency motor driving. The NJU7388B generates 150º commutation 3-phase sequence based on external hall signal and arbitrary lead angle setup. It has Clock Generator for reference clock of various functions such as conduction angle, lead angle, PWM, lock protection, current detection. The NJU7388B is a 5V logic operation-specific control IC. Therefore, it corresponds to various applications by selecting Pch MOSFETs and Nch MOSFETs as power stage. PACKAGE OUTLINE NJU7388BVC3 FEATURES Operating Voltage V DD =4.5V to 5.5V 150 Commutation Control Lead Angle Control 4bit A/D Input (0 to / 16 steps) Internal Clock Generator f PWM =20kHz ±5% Hall Element Input Current Detection V DETLIM =0.5V 5% (Pulse by pulse) PWM Control 6bit A/D (Duty=98.43% max. / 63 steps) FG Output Synchronized with H1 Forward / Reverse Direction Lock Protection (Latching type) UVLO Protection Package SSOP20-C3-1 -

2 BLOCK DIAGRAM FG VDD VREF UVLO H1+ H2+ UH H3+ H1- H2- H3- VH VLA Lead Angle 4Bit A/D Conv. Control Logic Output Logic WH CT Lock Det UL FR Clock Generator VL WL VERR 6Bit A/D Conv. + - PWM Logic ILIMIT GND - 2 -

3 PIN CONFIGURATION H1- H1+ H2- H2+ H3- H3+ VLA VERR FR FG VDD UL VL WL UH VH WH ILIMIT GND CT SSOP20-C3 PIN DESCRIPTION PIN No. PIN NAME FUNCTION NOTE 1 H1- Hall Input Pin H H1+ Hall Input Pin H H2- Hall Input Pin H H2+ Hall Input Pin H H3- Hall Input Pin H H3+ Hall Input Pin H VLA Lead Angle Setting Pin Input the DC voltage for setting the lead angle At not using, connect to ground or OPEN 8 VERR Speed Control Pin Input the DC Voltage for setting the PWM Duty 9 FR Direction Setting Pin L or OPEN= Forward Rotation H= Reverse Rotation 10 FG FG Output Pin Rotation signal output synchronized with H1 11 CT Lock Protection Setting Pin Connect a capacitor between GND for setting ON time of lock protection. At not using, connect to Ground 12 GND Ground Pin Connect to Ground 13 ILIMIT Over Current Detection Pin Connect a detection resistor to the motor output element side to detect the motor current. At not using, connect to Ground 14 WH WH Output Pin W Phase High Side Output 15 VH VH Output Pin V Phase High Side Output 16 UH UH Output Pin U Phase High Side Output 17 WL WL Output Pin W Phase Low Side Output 18 VL VL Output Pin V Phase Low Side Output 19 UL UL Output Pin U Phase Low Side Output 20 VDD Power Supply Pin

4 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT NOTES Power Supply Pin Voltage V DD 7 V VDD Pin Output Pin Voltage Vo -0.3 to 7 V UH, VH, WH, UL, VL, WL Pin Output Pin Current Io 10 ma UH, VH, WH, UL, VL, WL Pin Hall Input Pin Voltage V IH -0.3 to 7 V H1+, H1-, H2+, H2-, H3+, H3- Pin A/D Input Pin Voltage V IN -0.3 to 7 V VLA, VERR Pin FR Input Pin Voltage V FR -0.3 to 7 V FR Pin ILIMIT Pin Voltage V ILIM -0.3 to 7 V ILIMIT Pin FG Output Pin Voltage V FG -0.3 to 7 V FG Pin FG Output Pin Current I FG 5 ma FG Pin Power Dissipation (Ta=25 C) P D 1.0 W Mounted on 2Layers PCB (*1) 1.5 W Mounted on 4Layers PCB (*2) Junction Temperature Tj -40 to +150 C - Operating Temperature Topr -40 to +105 C - Storage Temperature Tstg -50 to +150 C - (*1): Mounted on glass epoxy board. ( mm: based on EIA/JEDEC standard, 2Layers FR-4) (*2): Mounted on glass epoxy board. ( mm: based on EIA/JEDEC standard, 4Layers FR-4, inner Cu area mm) RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Power Supply Pin Voltage V DD V Output Pin Current Io -3-3 ma A/D Input Pin Voltage V IN V FG Output Pin Voltage V FG V PIN OPERATING CONDTIONS (V DD =5V, Ta=25 C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Hall Input Pin (H1+, H1-, H2+, H2-, H3+, H3- Pin) Hall Input Sensitivity V MIH peak to peak V Hall Input Voltage Range V ICMIH V ILIMIT Pin ILIMIT Input Voltage Range V ICMILIM V FR Pin H Level Input Voltage V HFR V L Level Input Voltage V LFR V - 4 -

5 ELECTRICAL CHARACTERISTICS (V DD =5V, Ta=25 C) GENERAL PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Operating Voltage V DD V Quiescent Current I DD Non Load ma Internal Reference Voltage Vref V UNDER VOLTAGE LOCK OUT BLOCK UVLO Detection Voltage V DUVLO Output Disable, V DD Decreasing V UVLO Recovery Voltage V RUVLO Output Enable, V DD Increasing V UVLO Hysteresis Voltage V UVLO V HALL INPUT BLOCK Hysteresis Voltage Range V HYSIH mv Input Bias Current I BIH Per 1 Input µa HIGH SIDE / LOW SIDE OUTPUT BLOCK H Level Output Voltage V OH I SOURCE=3mA V L Level Output Voltage V OL I SINK=3mA V FG OUTPUT BLOCK L Level Output Voltage V FGL I FG=2mA V Leak Current I FGLEAK V FG=5.5V µa OVER CURRENT DETECTION BLOCK Detection Voltage V DETLIM V Input Bias Current I BLIM V LIM=0.5V µa Blanking Time t BLIM µs Delay Time t DLIM ns VLA BLOCK Lead Angle 1 Lead Angle 2 Ф VLA1 Ф VLA2 V INVLA=0V, f IH=100Hz, Ф IH(H1,H2,H3)=120 V INVLA=4.5V, f IH=100Hz, Ф IH(H1,H2,H3)= Input Bias Current I BVLA V INVLA=0V µa Input Pull Down Resistance R VLA kω VERR BLOCK PWM Oscillation Frequency f PWM khz Minimum PWM Duty PWM MIN V INVERR=1.317V % Maximum PWM Duty PWM MAX V INVERR=4.5V % LSB Threshold Voltage V PWMMIN V Input Bias Current I BVERR V INVERR=0V µa Input Pull Down Resistance R VERR kω FR BLOCK Input Bias Current I BFR V FR=0V µa Input Pull Down Resistance R FR kω LOCK DETECTION BLOCK Lock Protection ON Time t ONCT C CT=0.01µF s H Level Detection Voltage V HCT V L Level Detection Voltage V LCT V Lock Charge Current I CHGCT µa Lock Discharge Current I DCHGCT µa - 5 -

6 OPERATIONAL DEFINITION (PIN and CIRCUIT) Hall Input Pin Input Voltage Range 4.0V V ICMIH <At V DD =5V> Hall Input Hysteresis Voltage Width 4.0V V ICMIH <At V DD =5V> Logic Inversion Logic Inversion ΔV HYSIH 0.6V 0.6V Under Voltage Protection Operating Voltage V DD 5.5V Recommended Operating Voltage (max.) 4.5V V RUVLO V DUVLO Recommended Operating Voltage (min.) UVLO Recovery Volage(Nomral Operation) ΔV UVLO : Hysteresis Voltage UVLO Detection Voltage(Output Stop) 0V - 6 -

7 VLA Pin Input the DC voltage for setting the lead angle. The VLA function has a built-in 4-bit A/D converter, and it can set the range of lead angle 0 to in 16 steps. VLA Pin Voltage [V] Lead Angle [ º] *Design Value Lead Angle [ º] VLA Pin Voltage vs. Lead Angle (Theoretical Value) VLA Pin Voltage [V] - 7 -

8 VERR Pin Input the DC voltage for speed control. The VERR function has a built-in 6-bit A/D converter, and it can set the PWM Duty in 63 steps. The maximum PWM duty is 98.43%. When 0V V INVERR < 1.294V typ., both high side and low side are L outputs. Also, if the speed command is directly supplied PWM signal, input after converting it into a DC signal by configuring two RC filters externally. VERR Pin Voltage [V] PWM Duty [%] *Design Value PWM Duty [%] VERR Pin Voltage vs. PWM Duty (Theoretical Value) Output ON Period VERR Pin Voltage [V] Output OFF Period - 8 -

9 ILIMIT Pin The LIMIT function detects the over current of the motor current. When an overcurrent is detected, the low side outputs become L level after the internal circuit delay time (t DELAY ). It resets the overcurrent function at f PWM cycle so that it operates with pulse-by-pulse. The detection voltage is 0.5 V typ. Set the current detection resistance according to the detecting current value. When a spike current occurs due to the capacitance component of the output element etc., configure a low pass filter externally for preventing false detection. For the low pass filter, the resistance is 5k to 10kΩ and the capacitor is about 1000pF as a guide. PWM DUTY PWM DUTY PWM DUTY PWM DUTY High Side Output I LIMIT Detection Signal (H=Detection) Detection L Output t DELAY Detection L Output t DELAY CT Pin The lock status of motor rotation is detected by the time between the edges of each hall signal input. If the time between the edges of each hall signal input exceeds t H_LOCK (102.4ms typ.), the lock protection is activated. During lock protection operation, CT pin performs charge / discharge operation to C CT. This cycle is internally counted, and an output period (t ON ) is generated. Even in the output period (t ON ), the lock detection is continued, and if the hall input signal period less than t H_LOCK is detected, it becomes the normal operation state. The state of the lock protection circuit is reset when the power restart or V INVERR voltage is less than V typ. If there is a possibility of misdetection of lock protection like low speed startup, it should be set enough output period (t ON ). <Calculation formula> t ON [s] = 500 C CT [µf] e.g.) C CT =0.01µF: t ON = = 5 [s] Stopped Motor Rotation Release the latching status Release the latching status Operation Normal Lock Protection Output, Lock Detecton Status Output ON, Lock Detection Period Output OFF, Lock Non-Detection Period V HCT CT Pin Voltage V LCT t t ON t ON VERR Pin Voltage 1.294V typ. Power Supply Pin Voltage 4.1V typ

10 INPUT vs. OUTPUT TRUTH TABLE (H1+>H1-,H2+>H2-,H3+>H3-="H", Don't Care="X") No. H1 H2 H3 FR UVLO VERR ILIMIT CT UH VH WH UL VL WL FG STATUS 1 H L L L L H H/L L L L 2 H H L L L H L H/L L L 3 L H L H L L L H/L L Hi-Z OFF H L L 4 L H H H L L L L H/L Hi-Z 5 L L H L H L L L H/L Hi-Z 6 H L H L H L H/L L L L 1 H L L L 2 H H L L 3 L H L Hi-Z OFF L X X L L L L L L 4 L H H Hi-Z 5 L L H Hi-Z 6 H L H L 1 H L L L L H L 2 H H L L L H L 3 L H L H L L Hi-Z L OFF X X H L L L 4 L H H H L L Hi-Z 5 L L H L H L Hi-Z 6 H L H L H L L 1 H L L L L H L 2 H H L L L H L 3 L H L H L L Hi-Z OFF X H X L L L 4 L H H H L L Hi-Z 5 L L H L H L Hi-Z 6 H L H L H L L 1 H L L L 2 H H L L 3 L H L Hi-Z ON X X X L L L L L L 4 L H H Hi-Z 5 L L H Hi-Z 6 H L H L 1 H L H H L L L H/L L L 2 L L H L L H L H/L L Hi-Z 3 L H H L L H H/L L L Hi-Z OFF H L L 4 L H L L H L H/L L L Hi-Z 5 H H L L H L L L H/L L 6 H L L H L L L L H/L L 1 H L H L 2 L L H Hi-Z 3 L H H Hi-Z OFF L X X L L L L L L 4 L H L Hi-Z 5 H H L L 6 H L L L 1 H L H H L L L 2 L L H L L H Hi-Z 3 L H H L L H Hi-Z H OFF X X H L L L 4 L H L L H L Hi-Z 5 H H L L H L L 6 H L L H L L L 1 H L H H L L L 2 L L H L L H Hi-Z 3 L H H L L H Hi-Z OFF X H X L L L 4 L H L L H L Hi-Z 5 H H L L H L L 6 H L L H L L L 1 H L H L 2 L L H Hi-Z 3 L H H Hi-Z ON X X X L L L L L L 4 L H L Hi-Z 5 H H L L 6 H L L L <Hall Input pattern> The logic control block can receive the following input pattern only. Normal Operation (Forward) 1.294V typ. VERR Pin Voltage Low Side PWM Output Output OFF Operation (Forward) VERR Pin Voltage < 1.294V typ.. Lock Detection (Forward) (Output OFF Period) Over Current Detection (Forward) (Output OFF Period) UVLO Detection (Forward) Normal Operation (Reverse) 1.294V typ. VERR Pin Voltage Low Side PWM Output Output OFF Operation (Reverse) VERR Pin Voltage < 1.294V typ.. Lock Detection (Reverse) (Output OFF Period) Over Current Detection (Reverse) (Output OFF Period) UVLO Detection (Reverse) *The Starting point is free. If inputting other patterns, there is a possibility which causes a malfunction

11 TIMING CHART (1) 120º Commutation Mode (At FR=L) High side and low side commutation periods at H level output is 120. The PWM output is controlled on the low side, and the high side is 100% output. No H1 60º H2 H3 UH VH WH UL VL WL Zoom in UH UL t PWMMAX t PWMMIN Low Side Maximum PWM Width : t PWMMAX =49.22µs typ. Low Side Minimum PWM Width : t PWMMIN =0.78µs typ

12 (2) 120º Commutation Mode (At FR=H) High side and low side commutation periods at H level output is 120. The PWM output is controlled on the low side, and the high side is 100% output. No º H1 H2 H3 UH VH WH UL VL WL Zoom in WH WL t PWMMAX t PWMMIN Low Side Maximum PWM Width : t PWMMAX =49.22µs typ. Low Side Minimum PWM Width : t PWMMIN =0.78µs typ

13 (3)150º Commutation Mode (At FR=L) High side and low side commutation periods at H level output is 150. It overlaps 15 before and after compared with 120 commutation mode. The PWM output is controlled on the low side, and the high side is 100% output. No º H1 H2 H3 UH VH WH UL VL WL Zoom in UH UL t PWMMAX t PWMMIN Low Side Maximum PWM Width : t PWMMAX =49.22µs typ. Low Side Minimum PWM Width : t PWMMIN =0.78µs typ

14 (4)150º Commutation Mode (At FR=H) High side and low side turn-on periods at H level output is 150. It overlaps 15 before and after compared with 120 commutation mode. The PWM output is controlled on the low side, and the high side is 100% output. No º H1 H2 H3 UH VH WH UL VL WL Zoom in WH WL t PWMMAX t PWMMIN Low Side Maximum PWM Width : t PWMMAX =49.22µs typ. Low Side Minimum PWM Width : t PWMMIN =0.78µs typ

15 APPLICATION NOTE (1)Commutation Control and Lead Angle Control At start-up, it operates with 120 commutation. When the following conditions A, B, and C are satisfied in order, the operation shifts to 150 conduction angle operation and the lead angle setting becomes effective. A) Hall signal period is detected When the time between the edges of each hall signal input is less than t HALL (37.5ms typ.). B) The hall pattern is confirmed In order to prevent malfunctions from noise etc., the pattern of hall signal input is simply confirmed. At FR=L : When detected "H2=H L" and "H3=H L" sequentially from point of "H1=H L". At FR=H : When detected "H3=H L" and "H2=H L" sequentially from point of "H1=H L". (Refer to "a b c" in below figure) C) The number of pulses for hysteresis is counted When detected 5 edges of each hall signal input. (Refer to " " in below figure) If the time between edges of each hall signal input becomes less than t HALL (51.1ms typ.) during 150 commutation mode, the commutation mode is switched to 120 commutation and the lead angle setting becomes ineffective

16 (2) Low Side Output (UL, VL, WL) These are composed totem-pole outputs for the low side control of 3-phase motor. The PWM function and LIMIT function are controlled by this low side outputs. Although these can directly drive external output FETs, the output current rating is 10 ma. If the large output current for driving FETs are required, configure buffer circuits externally. Transient current and ringing during switching can be reduced by inserting output series resistors externally. Especially when driving FETs directly, these should be used resistors larger than 500Ω. (3) High Side Output (UH, VH, WH) These are composed totem-pole outputs for the high side control of 3-phase motor. These pins can t directly drive FETs, therefore constitute drive circuits using one external transistor. (4) Hall Input (H1+, H1-, H2+, H2-, H3+, H3-) These are hall signal input pins. These are connected to input differential amplifiers (hall amplifiers) internally. The internal circuit detects the voltage level like following that H+ > H- is H and H+ < H- is L. The hall amplifiers have the input hysteresis voltage range of 30mV (max). Therefore, it should be input the amplitude larger than 100mVp-p with considering the margin. And, the hall signal peak value must not exceed the hall input voltage range V ICMIH. V ICMIH 4.0V 0.6V Some noise might overlap to the hall signal based on the GND level fluctuations by phase current or the unbalance of output signal path, etc. If the malfunction of the output chattering etc. occurs, it should be connected between the positive pins and the negative pins with filter capacitors in range of 1nF to 100nF. t e.g.) Application circuit at using Hall IC 5V Hall ICs R3/R6/R9 4.7kΩ R1 4.7kΩ H1+/H2+/H3+ Input signal Hall input pin voltage 4.0V R5/R8/R11 1kΩ R4/R7/R10 12kΩ R2 4.7kΩ H1- to H3- Common reference voltage Hall input voltage range 0.6V H1- to H3- Common reference voltage H1+/H2+/H3+ Input signal t

17 (5)FG Output FG pin outputs the signal synchronized with H1 as a pulse with a cycle proportional to motor rotation. FG pin is an open-drain output with an absolute maximum rating of 7 V, so it should be connected to the power supply up to 5V with a pull-up resistor. Do not connect this pin to power supply for motor (V M ). <FG Truth Table (the signal synchronized with H1)> Forward Rotation (FR=L) Reverse Rotation (FR=H) H1 H2 H3 FG H L L L H H L L L H L Hi-Z L H H Hi-Z L L H Hi-Z H L H L H1 H2 H3 FG H L H L L L H Hi-Z L H H Hi-Z L H L Hi-Z H H L L H L L L

18 (6) VLA Input Generally, the period of current flow to the motor becomes shorter as the higher rotation speed, because the ratio of electrical delay increases. Therefore, when using at high-speed rotation, it is necessary to consider efficiency and speed performance in particular. The lead angle function can arbitrarily correct the commutation phase which is delayed from the predetermined value. < When setting fixed lead angle value > V DD VLA < Application for simply automatic lead angle control > As an easy way to apply the automatic lead angle control, set the VLA pin voltage to be linked with the VERR pin voltage according to the rotation speed. 1. When VERR=VLA setting Speed Control VERR VLA 2. When arbitrarily setting with R1/R2 Speed Control VERR R1 VLA R2 Lead Angle[ ] VERR Pin Voltage vs. Lead Angle (Theoretical Value) 1. VERR=VLA Setting VERR Pin Voltage [V] 2. R1/R2=0.9 Setting V INVLA = R1 V INVERR R2 e.g.) When setting to the lead angle of 15 at the maximum rotation speed V VERR =4.5 V. The VLA pin voltage required to set the lead angle of 15 is 2.36V. Therefore, the resistance ratio of R1 and R2 is as follows. R1 R2 = V INVERR V INVLA 1 = = For example, there is a combination of R1=9.1kΩ and R2=10kΩ

19 TYPICAL APPLICATION 5V Reg FG VDD +24V VREF UVLO GND H1+ H2+ UH H3+ H1- H2- H3- VH VLA Lead Angle 4Bit A/D Conv. Control Logic Output Logic WH Motor N CT Lock Det S N S UL FR Clock Generator VL WL VERR 6Bit A/D Conv. + - PWM Logic ILIMIT GND *FR pin must not switch until motor stopped completely. When switching the direction of rotation, FR pin should be switched after motor stopped completely

20 TYPICAL CHARACTERISTICS 3.0 I DD vs. V DD Ta=25ºC, Io=0mA 22 f PWM vs. V DD Ta=25ºC I DD [ma] 1.5 f PWM [khz] V DD [V] V DD [V] 5 V OH vs. I O_SOURCE V DD =5V, Ta=25ºC 0.2 V OL vs. I O_SINK V DD =5V, Ta=25ºC V OH [V] 4.5 V OL [V] I O_SOURCE [ma] I O_SINK [ma] 0.1 V FGL vs. I FG V DD =5V, Ta=25ºC 28 V HYSIH vs. V ICMIH V DD =5V, Ta=25ºC V FGL [V] 0.05 V HYSIH [mv] I FG [ma] V ICMIH [V]

21 TYPICAL CHARACTERISTICS 2.8 I DD vs. Tj V DD =5V, Io=0mA 24 f PWM vs. Tj V DD =5V I DD [ma] 2.2 f PWM [khz] Tj [ºC] Tj [ºC] 5 V OH vs. Tj V DD =5V, I O_SOURCE =3mA 0.1 V OL vs. Tj V DD =5V, I O_SINK =3mA V OH [V] V OL [V] Tj [ºC] Tj [ºC] 4.4 V DUVLO,V RUVLO vs. Tj 40 V HYSIH vs. Tj V DD =5V, V IH =2V V DUVLO, V RUVLO [V] V RUVLO V DUVLO V HYSIH [mv] Tj [ C] Tj [ºC]

22 TYPICAL CHARACTERISTICS 5.0 I CHGCT,I DCHGCT vs. Tj V DD =5V 4.0 V HCT,V LCT vs. Tj V DD =5V I CHGCT, I DCHGCT [µa] V HCT,V LCT [V] V HCT V LCT Tj [ºC] Tj [ºC] 0.6 V DETLIM vs. Tj V DD =5V 130 R VLA,R VERR vs. Tj V DETLIM [V] Tj [ºC] R VLA,R VERR [kω] Tj [ºC] 140 R FR vs. Tj 130 R FR [kω] Tj [ºC]

23 [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights