A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process Hyung-Gu Park, Jeong-A Jang, Sung Hun Cho, Juri Lee, Sang-Yun Kim, Honey Durga Tiwari, Young Gun Pu, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee, and Munkyo Seo Abstract This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using 0.18 mm BCD process with high power MOSFET options, and the die area is 1870 mm x 1430 mm. The power consumption of the charge pump itself is mw when the output power is mw at the high voltage mode, while it is mw when the output power is mw at the low voltage mode. The measured maximum power efficiency is %, when the output voltage is from 7.43 V to V. Index Terms Charge pump, reconfigurable, high power efficiency, wide output range Manuscript received Jul. 11, 2014; accepted Oct. 1, 2014 College of Information and Communication Engineering, Sungkyunkwan University mkseo@skku.edu I. INTRODUCTION A Charge Pump that generates higher voltage than the supply voltage is used for flash memories or touch panel application. These charge pumps should be able to drive the intrinsic panel resistance, because all the panels of a touch panel application include panel resistance. Recently, the need has increased for a charge pump that can drive various resistances of panels due to increasing demands for touch panels with various sizes and performance. To drive panels with a wide range of variable resistance, the range of charge pump output voltage should be as wide as possible. Hence, high output voltage of the charge pump is needed to drive high resistance inside the panel. The structures of the Dickson charge pump and Wu and Chang s Charge Pump have been used as a charge pump, since they can generate higher voltage than input voltage [1]. However, in these structures, the overall power consumption increases due to the power consumption of mode control blocks, and leakage current of charge pump core at low output voltage mode. Hence, it is difficult to adopt these structures for multi-mode charge pump architecture. In other existing charge pump circuits, the output voltage can increase using additional stages of a charge pump [2]. However, to be applied to touch panels, a charge pump must not only have high output voltages, but also enough output current to drive the resistance of the external panel. In this paper, a clock driver and switch (SW0) are activated or deactivated by the mode control signal to minimize the degradation of power efficiency. Also, a method is proposed to block all current paths except the

2 778 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN MOD_CON CPCLK DCON<2:0> VCON<6:0> VREF Φ1B,Φ2B,Φ3B,Φ4B Φ1,Φ2,Φ3,Φ4 Fig. 1. Block diagram of the proposed Automatic Reconfigurable Charge Pump. one used for charging the pumping capacitors and output capacitor. This paper also proposes a method to reduce the leakage current that flows in a charge pump core, at the moment of transition of clock driver output signals. Section II describes the reconfigurable charge pump architecture. Section III presents the building blocks, and Section IV presents the experimental results. Finally, the conclusion is presented in Section V. II. RECONFIGURABLE CHARGE PUMP ARCHITECTURE Fig. 1 shows a block diagram of the proposed automatic reconfigurable charge pump. The proposed reconfigurable charge pump is composed of the a Charge Pump Core, Clock Driver, Output Voltage Sense Network, MUX, Low Pass Filter (LPF), Reference Voltage Generator, Control Signal Generator (CSG) and Switch (SW0) connected to the External IC. Its configuration is automatically changed to generate the dual outputs, V OUT_LV and V OUT_HV, from the second stage and fourth stage, respectively. Two modes of reconfigurable charge pump are determined between high voltage mode and low voltage mode, according to the level of output voltages. The entire reconfigurable charge pump operations can be controlled by mode control signal, MOD_CON. Since the control signals, VCON<6:0> decide the voltage level of the charge pump output, multi-mode operations of the charge pump can be controlled. The clock driver outputs signals that control on/off operation of switch devices that transfer charges stage-tostage inside the charge pump core. The clock driver consists of a clock generator and mode controller. The clock generator proposed in this paper produces 4 phase clocks; each clock (CLK 1, CLK 2, CLK 3, and CLK 4 ) has a certain fixed delay, unlike other references [9-12, 16]. The reason why each clock of the clock driver has a certain fixed delay is to minimize charge loss, when clock transition occurs at the driver outputs. If the clocks have the same phase as the clock transition, PMOS and NMOS of neighbor stages turn on at the same time, and charges are transferred to the reverse direction, by the difference of potential between adjacent stages. The entire system operation is automatically controlled by mode controller, according to modes of the reconfigurable charge pump. In the mode controller, each clock (CLK 1, CLK 2, CLK 3, and CLK 4 ) is activated or deactivated, respectively, and the whole operation of multi-mode is also decided by the mode controller.

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, CPLV0 Fig. 2. Detailed schematic of the Charge Pump Core. VOUT_LV III. BUILDING BLOCKS Fig. 2 shows a detailed schematic of the charge pump core. The charge pump core uses 4 stages to increase the output voltage range. The circuit consists of charge transfer switches (MN 1 -MN 8, MP 1 -MP 8 ), pumping capacitors (CT 1, CT 2, CT 3, CT 4, CB 1, CB 2, CB 3 and CB 4 ), output capacitors (C LV, C HV ) and output nodes of each stage (CP LV0, V OUT_LV, CP HV0, and V OUT_HV ). In the high voltage mode of the multi-mode charge pump, the operation is similar to the operations of the low voltage mode, except that the voltage levels of Φ 3, Φ 4,Φ 3B and Φ 4B are maintained to zero (Φ 3, Φ 4 ) or VIN (Φ 3B, Φ 4B ), equaling the supply voltage of the process, in the low voltage mode. In the low voltage mode, the voltage levels of Φ 3, Φ 3B, Φ 4, and Φ 4B are maintained to DC voltages (zero or VIN), which are connected to only one end of CT 3 (or CB 3 ) or CT 4 (or CB 4 ) respectively. Consequently, the other end of CT 3 (or CB 3 ) or CT 4 (or CB 4 ), which is defined as nodes N 5, N 6, N 7, and N 8 in Fig. 2., is floated. Because the power efficiency is degraded, the 3 rd and 4 th stages are certainly turned off in the low voltage mode. If N 5, N 6, N 7, and N 8 nodes remain as floating nodes, the reliability of the off state of the 3 rd and 4 th stages is not guaranteed, although Φ 3, Φ 3B, Φ 4, and Φ 4B are maintained to zero or VIN. If MP 5 -MP 8 and MN 5 -MN 8 are turned on in the low voltage mode, charges will be transferred to the 3 rd stage, resulting in leakage current at the output of the charge pump. This is the main cause of difference in power efficiency between the low voltage mode and high voltage mode. In order to disable the 3 rd stage and 4 th stage at low voltage mode, the states of N 5, N 6, N 7, and CPHV0 VOUT_HV N 8 transistors need to be defined. Adding switches to N 5, N 6, N 7, and N 8, respectively, can avoid leakage current. Specific input voltages must be defined, to turn on N 5, N 6, N 7, and N 8 nodes in low voltage mode. As a result, the output voltages of the 3 rd and 4 th stages are completely defined. This method does not require additional circuitry that may increase the current consumption, degrading the power efficiency. Additionally, since these switches will have small parasitic capacitance and resistance, they will have minimal impact on the charge pump operation, and additional area will not be needed, in terms of chip area. The charge pump core proposed in this paper does not suffer from voltage drop due to the threshold voltage, body-effect and gate oxide breakdown, as compared to the conventional Dickson charge pump [6-14]. Gate oxide breakdown occurs when Φ 1 - Φ 4 and Φ 1B - Φ 4B are directly applied to the gate of MOSFETs in the charge pump core. By the boosting operation of the charge pump, the sources of MOSFETs have high voltage level, but the gates of MOFSETs are limited by VIN voltage. An additional control circuit has been used to solve the gate oxide breakdown issues, by turning on and off the MOSFETs. In the proposed charge pump structure, one end of each pumping capacitors (CT 1 -CT 4 and CB 1 -CB 4 ) is connected to the respective output of the clock driver (Φ 1 -Φ 4, Φ 1B -Φ 4B ), and the other end is connected to the respective drain and gate of MOSFETs inside the charge pump core. Φ 1 -Φ 4 and Φ 1B -Φ 4B are not directly connected to gate nodes for turning on and off these MOSFETs. Instead, the operation to turn on and off the MOSFETs can be achieved from voltage differences between the gates, and sources, generated by the charge transfer. This voltage is not allowed to exceed the normal operation points of MOSFETs, so that the gate oxide breakdown issues can be resolved, even though the voltage level rises step-by-step more than the front stage. To minimize the voltage drop due to the threshold voltage and the body effect issues, the sources and bodies of all MOSFETs in the charge pump core are connected to each other. Fig. 3 shows a detailed schematic of the Clock Driver and a timing diagram. The Clock Driver is composed of the Clock Generator and Mode Controller, and is an important block, in terms of the power efficiency in the

4 780 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN (a) Φ 1 Φ 1B Φ 2 Φ 2B Φ 3 Φ 3B Φ 4 Φ 4B t (a) (b) Fig. 3. (a) Detailed schematic of the Clock Driver, (b) Timing Diagram. proposed charge pump. To obtain high power efficiency, the Clock Generator produces 4-phase clocks (Φ 1, Φ 2, Φ 3, and Φ 4 ) from the reference clock (CP CLK ). If all clock phases for the pumping capacitor are the same during clock transition, NMOS s and PMOS s between neighboring stages are in the on state at the same time. Hence, due to the potential difference between the two stages, charge is transferred to the reverse direction in the charge pump, and the (b) Fig. 4. (a) Timing diagram of the Clock Driver, (b) PMOS of the 1 st stage, and NMOS of the 2 nd stage. power efficiency of the reconfigurable charge pump is degraded. The output capacitors of the charge pump (C HV or C LV ) need a certain amount of charge to reach the expected output voltage. Therefore, charge transfer in the reverse direction during the clock transition results in more current consumption to supply the required amount of charge to output capacitors (C HV or C LV ), and as a result, decreases the power efficiency of the multi-mode charge pump. The Mode Controller decides the system operations by a signal (MOD_CON), which controls the output voltage of the charge pump. The reconfigurable charge pump is operated in high voltage mode, when MOD_CON equals high ; and is operated in low voltage mode, when MOD_CON equals low. In addition, the Mode Controller plays the role of buffers and gate driver that generates clock signals, which drive pumping capacitors of the reconfigurable charge pump core. Fig. 4(a) shows the timing diagram of the 4-phase clock during the transition. The operations of MOSFETs related to the pumping capacitances, CB 1 and CB 2 between the 1 st and 2 nd stage, are shown in Fig. 4(b). Different time stamps during the clock transition are marked from T1 to T6. The method to reduce the current loss from the discharging path will be explained later. At time T1, the gate of MP 1 goes low, and MP 1 is turned on. Since MN 3 is off at time T1, the charge on N 3

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, (a) Fig. 5. A detailed schematic of the Delay Cell. i.e. the charge in CB 2 is not transferred from the 2 nd stage to the 1 st stage (reverse direction). At time T2, the gate of MN 3 goes high, and MN 3 is turned on, transferring charge from the 1 st stage to the 2 nd stage (forward direction). At time T3, the charge in CB 2 will be kept. At time T4, MN 3 maintains on state, and MP 1 is turned off, since the gate of MP 1 goes high. At T5, MP 1 is already off, and the gate of MN 3 goes low, turning off the MN 3. During T6, MP 3 and MN 1 keep the off state. The Clock Generator in the proposed Clock Driver has delay cells that generate 4 phase clocks, so that the charge transfer in the reverse direction between adjacent stages can be blocked, during transition in each clock. The proposed Clock Generator produces 4-phase clocks, by adding only delay to each clock, and the structure is simple, against the previous complicated 4-phase clock generators [9-12, 16]. Fig. 5 shows a detailed schematic of the Delay Cell inside the Clock Generator. This is composed of an inverter buffer and Delay Control block. The Delay Control block is equivalent to an RC delay bank consisting of transmission gates and active capacitors (MOSCAP). The delay can be controlled by the delay control signals (DCON<2:0>), to obtain the optimized power efficiency. The proposed Delay Cell can control the delay when the operation condition has changed, so that the charge pump achieves the optimized power efficiency. Fig. 6(a) shows the operation of the charge pump core at high voltage mode. All the multi-phase signals are (b) Fig. 6. Operation of charge pump core (a) at high voltage mode, (b) at low voltage mode. MOD_CON CP_CLK Clock Driver Φ 1,Φ 1B Φ 2,Φ 2B Φ 3,Φ 3B Φ 4,Φ 4B V SENSE Charge Pump Core V OUT_HV V OUT_LV V REF generated from the clock driver, and activate all stages of the charge pump core. Thus, the charge is transferred from stage 1 to the output node of stage 4 (V OUT_HV ), so that high voltage can be generated in the high voltage mode. Fig. 6(b) shows the operation of the charge pump at low voltage mode. Φ 3, Φ 3B, Φ 4, and Φ 4B signals are not generated in the low voltage mode. The voltage levels of Φ 3, Φ 3B, Φ 4, and Φ 4B are maintained at zero (Φ 3, Φ 4 ) or VIN (Φ 3B, Φ 4B ). Only Φ 1, Φ 1B, Φ 2, and Φ 2B activate stages 1 and 2 of the charge pump core. Thus, the charge is transferred from stage 1 to the output node of stage 2 (V OUT_LV ), so that low voltage can be generated in the low voltage mode. Fig. 7 shows the system of the reconfigurable charge pump. In high voltage mode, the mode control signal M U X R1 V CP_OUT V FB VCON<0> VCON<6> R2 R3 R9 Fig. 7. The system of the reconfigurable charge pump.

6 782 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN Start Select Charge Pump Mode (HV or LV) Step-up Operation (Charge pump) V CP_OUT > V REF Yes Non-Operate Clock Driver NO Operate Clock Driver Non-Step-up Operation (Charge pump) Fig. 9. Timing diagram of the reconfigurable charge pump. NO V CP_OUT > V REF Yes Fig. 8. A flow chart of the proposed multi-mode charge pump. (MOD_CON) is high, and the output node of the reconfigurable charge pump (V CP_OUT ) is the same as the output node of the 4 stages (V OUT_HV ) by MUX operation. In low voltage mode, the output node of the reconfigurable charge pump (V CP_OUT ) becomes equal to the output node of stage 2 (V OUT_LV ). In the Mode Controller of the Clock Driver in Fig. 3(a), CLK 1 and CLK 2 nodes and mode control signal (MOD_CON) are input to a NAND gate, respectively. Since the mode controller (MOD_CON) signal is low, the output node of the reconfigurable charge pump (V CP_OUT ) is the same as the output node of 2 stages (V OUT_LV ) by MUX operation. The DC voltage values are generated to Φ 3, Φ 3B, Φ 4, and Φ 4B nodes, thus the stages 3 and 4 of the charge pump core are deactivated. Therefore, low output voltage of the reconfigurable charge pump (V CP_OUT ) can be obtained. Fig. 8 shows a flow chart of the reconfigurable charge pump. The entire operation of the reconfigurable charge pump is continuous, with a negative feedback system. First, the step-up operation is started, once the VIN (charge pump input voltage) and signals from CSG are applied. The Step-Up Operation is a series of processes increasing the output voltage stage-by-stage. Pumping capacitors in the charge pump core are charged, and the charge is transferred to the next stage, consequently increasing the output voltage level consequently. As shown in Fig. 7, the V CP_OUT is divided by the resistor divider, which in turn is controlled by the digital control signal, VCON<6:0>. V CP_OUT is compared with the reference voltage (V REF ) generating the V SENSE voltage. V SENSE is the input to the clock driver, and is used to determine whether to continue step-up operation of the charge pump, or not. Fig. 9 shows a timing diagram of the multi-mode charge pump that shows the clock driver operation at high voltage mode and low voltage mode, which was explained in Fig. 7. A reference clock, CP CLK, is used for generating the clock driver outputs (Φ 1 -Φ 4, Φ 1B -Φ 4B ). SW0 is a control signal that turns on and off the switch connecting the reconfigurable charge pump circuit to the external IC. During the initial step-up operation, the SW0 signal is low, and the operation of the charge pump does not suffer from high load resistance or parasitic capacitance. In the high voltage mode, all the output signals of the clock driver, Φ 1 -Φ 4 and Φ 1B -Φ 4B, are activated, and high voltage is generated at the output of the reconfigurable charge pump. In the low voltage mode, only Φ 1 -Φ 2 and Φ 1B -Φ 2B

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, Output Current(mA) Output Load(Ω) (a) Fig. 10. Chip layout pattern. signals are activated, and Φ 3 -Φ 4 and Φ 3B -Φ 4B signals are deactivated. Thus, the output voltages of stage 3 and stage 4 (CP HV0, V OUT_HV ) are fixed in this mode. As a result, the charge is transferred from stage 1 to stage 2, and the output voltage of stage 2 (V OUT_LV ) increases. Since the charge is not transferred to stages 3 and 4, the output voltages of the these two stages are not increased. Output Voltage(V) Output Current(mA) (b) IV. EXPERIMENTAL RESULTS 86 The proposed chip is fabricated in 0.18 mm BCD technology, a single poly layer, four layers of metal, options of metal-insulator-metal (MIM) capacitors, and high sheet resistance poly resistors. The chip layout pattern is shown in Fig. 10. The chip layout pattern shows the clock driver, bandgap reference (BGR) for generating VREF in the feedback system, 2-to-1 MUX for choosing high voltage mode or low voltage mode, and 4 stages charge pump core. The die area of the multi-mode charge pump is 1870 mm x 1430 mm. Figs. 11(a)-(c) show measurement results of the designed reconfigurable charge pump. Since the proposed reconfigurable charge pump is applied to a touch panel, it should be able to provide a high output current, even at hundreds ohms of resistance. Therefore, the output load is swept from 150 Ω to 1.25 kω. Fig. 11(a) shows measurement results of the output current range of the reconfigurable charge pump. The maximum current is 63 ma at 150 Ω load condition, and at the load condition of 1 kω, the output current is still approximately 11.8 ma, which is enough to drive the high resistances in touch panels. Fig. 11(b) shows the Power Efficiency(%) Output Load(Ω) (c) Fig. 11. Measurement results of (a) the output current range, (b) the output voltage range, (c) the power efficiency range, within the variable output load conditions. output voltage range of the reconfigurable charge pump. The output voltage with respect to the output current is from 10.5 V to V, and the current condition is based on the same load condition from 150 Ω to 1.25 kω. The maximum power efficiency is 84 % at the load condition of 360 Ω in Fig. 11(c). Therefore, the designed reconfigurable charge pump can maintain a high voltage of about 12 V, and at the same time generate an output current of over 10 ma at the high load condition. Thus, it can operate a touch

8 784 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN V CP_OUT = 8.99V V CP_OUT = 8.47V V CP_OUT = 8.03V V CP_OUT = 7.42V [V] V CP_OUT = 8.99V(@VCON<6:0> = ) V CP_OUT = 8.47V(@VCON<6:0> = ) V CP_OUT = 8.03V(@VCON<6:0> = ) V CP_OUT = 7.42V(@VCON<6:0> = ) Fig. 12. Measurement environment of the proposed reconfigurable charge pump. 3 Fig. 14. Measured output voltage of the charge pump at the low voltage mode. (a) (b) Fig. 13. Measured results of the (a) output voltage of the reconfigurable charge pump, (b) output signals of an external circuit driven by the reconfigurable charge pump. panel with high resistance. Fig. 12 shows the measurement environment with the test board. The V CP_OUT, the final output node of the reconfigurable charge pump, and V EXT_OUT, the output node of the external IC are measured, as shown in Fig. 13. The output voltage of the reconfigurable charge pump (V CP_OUT ) is equal to 10.8 V, as shown in Fig. 13(a). Fig. 13(b) shows the output signal of the external circuit (V EXT_OUT ), which is used to drive the touch panel in real applications. V CP_OUT is used as the supply voltage to the external circuit. The peak-to-peak voltage range of the external output signal (V EXT_OUT ) is determined by the voltage level of V CP_OUT. Measurement shows that V EXT_OUT has the peak-to-peak amplitude of 10.1 V. Based on the measurement results, in the case of connecting a panel with a high resistance of about 300 Ω, the designed reconfigurable charge pump has enough capability to drive the touch panel. Fig. 14 shows the measured output voltage of the charge pump at the low voltage mode. The VCON<6:0> are used to control the output voltage of the charge pump. The power efficiency of the charge pump is calculated by the ratio between the input power and output power, based on the measurement results. In Eq. (1), IOUT and VOUT can be obtained at the output node of the charge pump (V CP_OUT ), respectively. V DC_IN is the input voltage of the charge pump and the supply voltage of all sub-blocks. I DC_IN is the average DC current value of the current consumption by the supply voltage (V DC_IN ). IOUT VOUT Efficiency(%) = 100 (1) I V DC _ IN DC _ IN The measurement results regarding the output voltage, output current, and power efficiency are summarized in Table 1, under the load conditions from 150 Ω to 1.25 kω. All 4 stages of charge pump core are active at the high voltage mode, whereas only 2 stages of charge pump core are active at the low voltage mode. Thus, the

9 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, Table 1. Summary of the measured power efficiency Type Low Voltage Mode High Voltage Mode Input Power 110mW mw Output Voltage 7.43V V Output Current 12.1mA ma Output Power mW mw Power Efficiency 81.73% 84.01% Table 2. Summary of the performance Reference [2] [6] [17] This work Process Supply Voltage Output Voltage Range Output Current Power Efficiency Die area 0.35 um SOI CMOS 0.35 um n-well CMOS power efficiency at the low voltage mode is degraded by approximately 2.28 %, compared with the power efficiency at the high voltage mode. The leakage current path is formed by the inactive charge pump stages because they are not perfectly turned off. As a result, the power efficiency is degraded by the leakage current of 2 stages of charge pump which is inactive at the low voltage mode. Table 2 summarizes the performance comparison with other references based on the charge pump. Generally, the panel resistor and required driving current can be varied depending on the structure and the application of the touch panel. Therefore, the output voltage range of Tx driver needs to be wide, which could be achieved by the charge pump in this paper controlling and maintaining the output voltage range with the help of control bits. As a result, by using the output voltage ranging from 7.43 V to V, various kinds of panels in many applications can be covered. V. CONCLUSIONS 0.18 um CMOS 0.18 um BCD 3.3 V 1.6 V 1.8 V 1.8 V 20V 3.6-6V V 20 ua 5 ma 0.7 ua 72 % 84 % N/A N/A x 0.7 mm 1.56 x 4.13 mm 2 (charge pump only) V ma % 1.43 x 1.87 mm 2 In this paper, a reconfigurable charge pump architecture with 4 stages for the touch panel is presented. The designed charge pump can generate variable output voltage. Therefore, the charge pump can drive touch panels with high resistance. The main issue concerning the use of a reconfigurable charge pump is the degradation of power efficiency at low voltage mode. To reduce the degradation of power efficiency, stages 3 and 4 are not activated at low voltage mode, to prevent leakage current. Non-overlapping 4 phase clocks are used to improve the power efficiency. To reduce power loss, a switch is used to disconnect the charge pump and external panel IC, before the charge pump output voltage is settled. The proposed chip is fabricated with 0.18 um BCD process, which uses 1.8 V supply voltage. At high voltage mode, the highest output voltage is V, the output current is ma, and the power efficiency is %. At low voltage mode, the lowest output voltage is 7.43 V, the output current is 12.1 ma, and the power efficiency is %. ACKNOWLEDGMENTS This research was supported by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (NIPA-2014-(H )) supervised by the NIPA (National IT Industry Promotion Agency). This work was supported by IC Design Education Center (IDEC). REFERENCES [1] M.-D. Ker, S.-L. Chen and C.-S. Tsai, Design of charge pump circuit with consideration of gateoxide reliability in low-voltage CMOS processes, IEEE J. Solid-State Circuit, vol 41, no. 5, pp , May [2] M. Hoque, T. McNutt, J. Zhang, A. Mantooth and M. Mojarradi, A High Voltage Dickson Charge Pump in SO1 CMOS, in Proc. Custom Integrated Circuits Conference, pp , Sep [3] J.-Y. Park and Y. Chung, A Low-Voltage Charge Pump Circuit with High Pumping Efficiency in Standard CMOS Logic Process, in Proc. IEEE Electron Devices and Solid-State Circuits, pp , Dec [4] O.-Y. Wong, W.-S. Tam, C.-W. Kok and R. Wong, A novel gate boosting circuit for 2-phase high

10 786 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN voltage CMOS charge pump, in Proc. IEEE Electron Devices and Solid-State Circuits, pp , Dec [5] A. Richellil, L. Mensil, L. Colalongol, P. L. Rolandi and Zs. M. Kovacs-Vajnal, A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatile Memories, In Proc. IEEE Int. Solid- State Circuits Conference, pp , Feb [6] X. Zhang and H. Lee, An efficiency-enhanced auto-reconfigurable 2x/3x SC charge pump for trans-cutaneous power transmission, in Proc. Custom Integrated Circuits Conference, pp , Sept [7] K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung and K.-D. Suh, Floating-well charge pump circuits For sub-2.0 V single power supply flash memories, in Symp. VLSI Circuits Dig. Tech. Papers, pp , Jun [8] J. Shin, I.-Y. Chung, Y. J. Park and H. S. Min, A new charge pump without degradation in threshold voltage due to body effect, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp , Apr [9] J. C. Chen, T. H. Kuo, L. E. Cleveland, C. K. Chung, N. Leong, Y.K. Kim, T. Akaogi, and Y. Kasa, A 2.7 V only 8 Mbx16 NOR flash memory, in Symp. VLSI Circuits Dig. Tech. Papers, pp , Jun [10] K. Sawada, Y. Sugawara and S. Masui, An onchip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V, in Symp. VLSI Circuits Dig. Tech. Papers, pp , Jun [11] S. Atsumi, M. Kuriyama, A. Umezawa, H. Banba, K. Naruke, S.Yamada, Y. Ohshima, M. Oshikiri, Y. Hiura, T. Yamane and K.Toshikawa, A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation, IEEE J. Solid- State Circuits, vol. 29, no. 4, pp , Apr [12] H. Lin and N.-H. Chen, New four-phase generation circuits for low voltage charge pumps, in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, pp , May [13] S.-Y. Lai and J.-S. Wang, A high-efficiency CMOS charge pump circuit, in Proc. IEEE Int. Symp. Circuits Syst., vol. 4, pp , May [14] H. Lin, K.-H. Chang and S.-C. Wong, Novel high positive and negative pumping circuits for low supply voltage, in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, pp , Jul [15] C. Lauterbach, W. Weber and D. Romer, Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps, IEEE J. Solid-State Circuits, vol. 35, no. 5. pp , May [16] J.-T.Wu and K.-L. Chang, MOS charge pump for low-voltage operation, IEEE J. Solid-State Circuits, vol. 33, no. 4, pp , Apr [17] M. Innocent, P. Wambacq, S. Donnay, W. Sansen and H. De Man, A Linear High Voltage Charge Pump For MEMS Applications in 0.18um CMOS Technology, in Proc. European Solid-State Circuits Conference, ESSCIRC '03, pp , Sept [18] M.R. Hoque, T. Ahmad, T. McNutt,, A. Mantooth and M. M. Mojarradi, Design Technique of an On-Chip, High-Voltage Charge Pump in SOI, in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, pp , May Hyung-Gu Park was born in Seoul, Korea. He received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2010, where he is currently working toward the Ph.D. degree in School of Information and Communication Engineering, Sungkyunkwan University. His research interests include high-speed interface IC and CMOS RF transceiver. Jeong-A Jang received the B.S. degree from Konkuk University, Seoul, Korea, in She is currently working toward the combined M.S. and Ph.D. degree at the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea. Her research interests include dc dc converters and CMOS RF transceivers.

11 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.6, DECEMBER, Sung Hun Cho was born in Seoul, Korea. He received his B.S. degree from the Department of Electronic and Electrical Engineering at Hongik University, Seoul, Korea, in 2013, where he is currently working toward the M.S. degree in School of Information and Communication Engineering, Sungkyunkwan University. His research interests include DC-DC converter and CMOS RF IC. Juri Lee received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013, where she is currently working toward the combined Ph.D. & M.S degree in School of Information and Communication Engineering, Sungkyunkwan University. Her research interests include VCSEL driver and CMOS RF transceiver. Sang-Yun Kim received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2013, where he is currently working toward the combined Ph.D. & M.S. Course in School of Information and Communication Engineering, Sungkyunkwan University. His research interests include high-speed interface IC and CMOS RF transceiver. Honey Durga Tiwari received a Bachelor s in Technology degree in Electronics Engineering from Nagpur University, Nagpur, India, in He received a Master s degree in Embedded System Design from VNIT, Visvesvaraya National Institute of Technology, Nagpur, India in He received his Ph.D. degree in 2012 from Konkuk University, Seoul, South Korea. From 2012 to 2013, he worked as Post- Doctoral researcher in School of Information and Communication Engineering, Sungkyunkwan University. Currently, he is working as Research Professor in School of Information and Communication Engineering, Sungkyunkwan University. His research interests include forward error control coding system development, hardware-software co-design of communication systems, multi-carrier systems and image processing. Young Gun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2006, 2008 and 2012, respectively. His research interest is focused on CMOS fully integrated frequency synthesizers and oscillators and on transceivers for lowpower mobile communication. Keum Cheol Hwang received his B.S. degree in electronics engineering from Pusan National University, Busan, South Korea in 2001 and M.S. and Ph.D. degrees in electrical and electronic engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea in 2003 and 2006, respectively. From 2006 to 2008, he was a Senior Research Engineer at the Samsung Thales, Yongin, South Korea, where he was involved with the development of various antennas including multiband fractal antennas for communication systems and Cassegrain reflector antenna and slotted waveguide arrays for tracking radars. He was an Associate Professor in the Division of Electronics and Electrical Engineering, Dongguk University, Seoul, South Korea from 2008 to In 2015, he joined the Department of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon, South Korea, where he is now an Associate Professor. His research interests include advanced electromagnetic scattering and radiation theory and applications, design of multi-band/broadband antennas and radar antennas, and optimization algorithms for electromagnetic applications. Prof. Hwang is a lifemember of KIEES, a senior member of IEEE and a member of IEICE.

12 788 HYUNG-GU PARK et al : A WIDE OUTPUT RANGE, HIGH POWER EFFICIENCY RECONFIGURABLE CHARGE PUMP IN Youngoo Yang (S'99-M'02) was born in Hamyang, Korea, in He received the Ph.D. degree in electrical and electronic engineering from the Pohang University of Science and Technology(Postech), Pohang, Korea, in From 2002 to 2005, he was with Skyworks Solutions Inc., Newbury Park, CA, where he designed power amplifiers for various cellular handsets. Since March 2005, he has been with the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea, where he is currently an associate professor. His research interests include power amplifier design, RF transmitters, RFIC design, integrated circuit design for RFID/USN systems, and modeling of high power amplifiers or devices. Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc., San Jose, CA, where he was a Manager of the Analog Division and worked on the design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of Information and Communication Engineering, Sungkyunkwan University, where he is currently an Associate Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixedmode VLSI system design. Munkyo Seo received the Ph.D. degree in electrical engineering from the University of California, Santa Barbara (UCSB), in From 1997 to 2002, he was a RF Engineer with LG Electronics Inc., designing RF/microwave subsystems for wireless communication. He was an Assistant Project Scientist with UCSB from 2008 to His research at UCSB focused on signal processing techniques for timeinterleaved analog-to-digital converters, novel millimeterwave communication/sensor network systems, and millimeter-wave IC designs in advanced CMOS and HBT technologies. In 2009, he joined Teledyne Scientific Company, Thousand Oaks, CA, where he worked on the design of mixed-signal and submillimeter-wave circuits. Since Mar. 2013, he has been with Sungkyunkwan University, Korea, as an assistant professor.