Hands-on Homework 2: Modeling transmission lines

Transcription

1 Hands-on Homework 2: Modeling transmission lines ntroduction n class, we developed a model for a infinite length lossless transmission line (t-line). t was configured as a ladder network of vanishingly small, identical, series and shunt elements. Such a transmission line will have a fixed characteristic impedance Z o and time-of-flight delay T f which we derrived. Using circuit simulation we will confirm the models validity. Then using this model, you will build a delay line with a specified Zo and delay. This exercise also serves as a jumpstart to driving spice (specifically ngspice) from a netlist. A detailed examination of the simulation files used will be given. Feel free to copy and modify for your needs. However, you are not relieved of understanding what is going on in the files. Spice Simulation of the nfinite ength T-line Model onsider the infinite length t-line model we developed. Vin Zo Figure : nfinite length t-line model The characteristic 2 impedance Z o and the flight time T f of such a line was developed in lecture. The values of and are measured on a per-unit-length basis. Note that the series, shunt configuration a low pass filter. f however, and are allowed to be arbitrarily small, the transimssion line will have a correspondingly large bandwidth. A network with a large bandwidth will allow digital pulses to traverse the network with low distortion. n lecture we found that: T f = Z MP o = 2 We now confirm these results by building a slightly Vin simplified Vout 3 t-line model. onsider a digital wave edge propagating downb the network GND 2 as shown in Figure 2. Behind the edge, constant current 4.5V U 0uF 3 AO20EK 4 VDD 7 GND U2 N 8 OUT Zo

2 9 i 0 out Vin tline_seg in out flows. n front of the edge, no current flows. Only at the edge, is there a changing current. Thus, Zo we can look at one section of the network composed of two s and one. Since this is a series circuit, we can simplify it by consolidating the two inductors into one. 2 ten instances of the subcircuit R2 80 Figure 2: ombining two series inductors into one MP Vin Vout 3 The second simplifcation is to limit the size of the network to one-hundred B and elements. GND Although it s nowhere near an infinite number of elements, we will 4.5Vfind that it s actually quite U accurate for our situation. n addition, with a termination resistor at the end of the network, it will look infinitely long. AO20EK et s build our test case around a 80 ohm transmission line that exhibits a 4ns delay. Using the 4 VDD N equations we derived for delay T f, and characteristic impedance Z o, the values for total 2 and 7 GND OUT 8 are easily determined. Dividing the total and 3 by 00, we know the value of each incremental U2 Zo4 and element. Below, we will develop the ngspice file for simulating the 00 element-lengthline. f you a concatenate b inc order, each piece shown, you will have a complete, executable ngspice file. nh network simulating 4ns, 80ohm line 2 *This model uses 3 00 sections 4 to create the 4ns line.param Vdd = 3.3 ;Vdd is assumed to be 3.3 Volts.param Vth = 3.3/2 ;set the swithing threshold to /2 Vdd 3 2 0uF 3 The first line in any spice file is the title line. Wether TTE or you use line one as a title line, its still a title. f you put a netlist element or simulationfe: command here, it will become the title REVSON: and otherwise ignored. There is no need for a comment PAGE character in the title. OF You may also DRAWN remindby: yourself that line one is the title by putting.title on line one. omment lines in spice usually begin with a *. A semicolon may be used as an end of line comment delimiter as well. Two parameters are defined; one for V dd and V th. They allow the use of a text variable in the spice file improving readability and flexibility. For example, if the supply voltage changes, we can change it in one place instead of everywhere it was used. Smart software practices hold true in spice files too! Since we are going to build a model with 00 sections, a hierarchical approach is the only practical way. magine trying to draw a schematic with 00 and elements. We build the spice model by using ten subcircuits that each hold ten and elements. A spice subcircuit is a hierarchical block that contains another spice netlist. t is placed within a top-level netlist to encapsulate circuitry for complexity hiding. 2

3 A subcircuit is analogous to a function call in. t is called from another body of code. t is supplied arguments, but they are the ports on the subcircuit block. Our subcircuit internal representation and equivalent block diagram are shown below. in a 2 9 i 0 out tline_seg in out Figure 3: Encapsulation of 0 sections into one subcircuit The subcircuit below creates a 0 element portion of a 00 element, 80 ohm t-line. ********************************************************************** *subcircuit composed of 0 v_in sections useddly_in to make up the longer tline.subckt tline_seg in out _val=3.2nh _val=0.5pf ten instances of the subcircuit l in a _val 0. l2 a b _val l3 b c _val V l4 c d _val l5 d e _val l6 e f _val l7 f g _val l8 g h _val l9 h i _val l0 i out _val c a _val c2 b _val c3 c _val c4 d _val c5 e _val c6 f _val c7 g _val c8 h _val c9 i _val v_in dly_in c0 out _val Zo.ends tline_seg ************************************************************ V 2 a 2 b 3 c R Subcircuits begin with.subckt followed by the subcircuit name then the names of its ports. The port names are understood internal to the subcircuit. The elements in the subcircuit are connected as with any spice netlist. The subcircuit ends with the.ends command. n cases where there are many elements of the same value, or where you may want to override values, parameters may be added to the subcircuit. Here val and val at the subcircuit call set the values of all the and elements. These values are defaults and my be overridden at instaniation time. v 3 3

4 To use the subcircuit in the top level circuit, it is called with a line that begins with an X, followed by a unique number if there are multiple instances of the subcircuit. A small x will also work, but the capital version stands out more in the netlist. Wires are connected to the subcircuit in the same order in in whichathey were 2 declared in the subcircuit 9 i declaration. 0 outat the end of the line, the name of the subcircuit being used is named. Below we see ten instantiations of the subcircuit called.. tline seg tied in series. Pay attention to indentation. t s not just pretty; it2 helps prevent mistakes. 9 0 Vin *0 subcircuit calls to the tline segments * input output name X dly_in a tline_seg X2 a b tline_seg X3 b c tline_seg X4 c d tline_seg X5 d e tline_seg X6 e f tline_seg X7 f g tline_seg X8 g h tline_seg X9 h i tline_seg X0 i tline_seg tline_seg in out Below is the entire circuit we are modeling. V v_in 0. dly_in ten instances of the subcircuit R2 80 Figure 4: Top level schematic *input source with ns delay, 2nS edges, 25ns pulse width, 50ns cycle time V vin 0 PUSE(0 Vdd ns 2ns 2ns 25ns 50ns) vin dly_in 0. ;0. ohm resistor used to determine the input current R2 80 ;terminating resistor at end of network v_in dly_in a 2 b 3 c 4 A pulsed source is declared along with a 0. ohm current sensing resistor. This resistor is used to determine the input current Zo into the network. We will need it to determine the input impedance of the network. You will see how this is done later. We have also placed an 80 ohm resistor at the V end of the network to terminate it. This makes the network look like it is infinitely long as any cannot tell the difference from looking into a longer segement of 80 ohm transmission line and a resistor. This completes our circuit netlist. We need to tell the simulator what to do. This is done via simulation directives. n this case we use the.tran command to run a transient simulation. The simulation will run for 50ns and sample data every 00ps. 3 4

5 .tran 00ps 50ns ;run tranisient simulation for 50ns *measure the time delay at switching threshold (Vth) from input to output of tline.meas tran tdelay trig v(dly_in) val=vth rise= td=00ps targ v() val=vth rise= td=00ps *measure the input impedance during the rising edge at the switching threshold.meas tran z_in find par( (v(dly_in)/((v(vin)-v(dly_in))/0.)) ) when v(dly_in)=vth.control * plot v(dly_in) v() v(vin) xl 00ps 50ns * gnuplot gnuplt_4ns_80ohm v(dly_in) v() v(vin) xl 00ps 50ns.endc.end Once the simulation has run, we can gather data and make automated measurements. We use the.meas command to do this. The.meas command is complex with many options and possibilities for making measurements. With the measure command, we confirm the t-line delay and determine its input impedance. The first.meas command measures the delay. The result generated is called tdelay. The measurement is triggered when the first rising edge of node v(dly in) reaches V th. The check for the trigger begins after a 00ps delay. The target or point at which the measurement is ended is reached when first rising edge of node v(dly out) reaches V th. The second.meas command measures the input impedance. We choose V th as the point on the rising edge to take the measurement. The result generated is called zin. The input impedance is determined by dividing the voltage at the input of the network by the current flowing into the network. The current into the network is sampled by the 0. ohm resistor. After we run the simulation, ngspice prints results into the invoking shell window showing the delay to be close to 4ns and the input impedance to be about 82 ohms. Measurements for Transient Analysis tdelay = e-09 targ= e-09 trig= e-09 z_in = e0 ts also important to also see the waveforms of the signals generated. This maybe done with either the plot or gnuplot command inside the.control and.endc commands. Uncomment plot to see results interactively or use gnuplot for nice looking plots. The simulation result from gnuplot here shows an approximate 4ns delay and good pulse shape fidelity. 5

6 in a 2 9 i 0 out lc network simulating 4ns, 80ohm line 0 v(dly_in) v() v(vin) Vin V tline_seg in out V v_in 0 dly_in ten instances of the subcircuit 5e-09 e-08.5e-08 2e e-08 3e e-08 4e e-08 5e s R2 80 Figure 5: Pulse applied to 00 section t-line model Building a working delay line The last digit of your student D will determine the characteristics of the delay line you will build. See the table in the grading section to find your variation of the network parameters. Develop the spice circuit simulation model of your delay line and then physically build the circuit. Here is the 3 schematic of the simulation model. AO 4 VD 7 GN V v_in Zo dly_in a 2 b 3 c Figure 6: Simulation model of the circuit to build This circuit is slightly different than the first model. nstead of a parallel termination resistor at the output of the network, there is a Z o ohm series termination resistor at the input. Another difference is that to simplify the circuit, only four sections are used instead of one-hundred. The oscillator is modeled using the same pulse statement as before. For an example, suppose you are building a 50 ohm, 5ns delay line with four sections. Our spice netlist would look like the following. TTE FE: PAGE 6

7 network simulating 5ns, 50ohm line.param Vdd = 3.3 ;Vdd is 3.3 Volts.param Vth =.5 ;set the sampling voltage to.5 volts *input source with ns delay, 2nS edges, 25ns pulse width, 50ns cycle time Vin vin 0 PUSE(0 Vdd ns 2ns 2ns 25ns 50ns) ********************************************************************** *subcircuit composed of section used to make up the longer tline.subckt tline_seg in out in out ; student supplied out ; student supplied.ends tline_seg ************************************************************ vin dly_in 50 ;series termination resistor X dly_in a tline_seg X2 a b tline_seg X3 b c tline_seg X4 c tline_seg.control tran 00ps 50ns plot v(dly_in) v() xl 00ps 50ns.endc *measure the time delay at switching threshold (Vth) from input to output of tline.meas tran tdelay trig v(dly_in) val=vth rise= td=00ps targ v() val=vth rise= td=00ps *measure the input impedance during the rising edge at the switching threshold.meas tran z_in find par( (v(dly_in)/((v(vin)-v(dly_in))/50)) ) when v(dly_in)=vth.end Here are the simulation results from ngspice. The delay is pretty close to our target values even with only four sections. The input impedance is rather off. This may be an artifact of the small number of elements in the delay line. Measurements for Transient Analysis tdelay = e-09 targ= e-09 trig= e-09 z_in = e0 Note that the voltage at which the delay and input impeadance was changed to allow a measurement with the voltage pedestal present at the network input. 7

8 simulation of 4 section, 5ns, 50ohm line 3.5 v(vin) v(dly_in) v() V.5 Vin Zo e-09 e-08.5e-08 2e e-08 3e e-08 4e e-08 5e-08 Figure 7: Waveforms from 5ns, 50ohm delay network s Build the real thing Here is the circuit you will build. t is the physical realization of the model we just developed. B 4.5V MP Vin Vout 3 GND U 2 0uF 4 F 3 4 VDD PAGE AO20EK 7 GND U2 N 8 OUT Zo4 OF 2 2 DRAWN BY: 3 3 Figure 8: Breadboard circuit of delay line to build 4 4 The value of the termination resistor depends on the output impedance of the oscillator. The oscillator has an output impedance of about 4 ohms. So the value of to properly terminate the network is Z o 4. The inductors are built using toroidal cores. The physical shape of the toroids keep the magnetic field well contained and lessens interaction with nearby objects. One turn on a toroid is TTE FE: REVSON: defined as one pass through the toroid, not a lap around the core. The winding on the toroids 8

9 should occupy about two thirds of the form. Don t allow the turns to overlap. On the protoboard, keep the toroids spaced a bit so they do not capacitively or inductively couple. The number of turns required for a Micrometals T25-2 with an A l value of.2 is given by: N = desired inductance in nh Determine the turns required and wind all four inductors. Remembering that wires are inductors, assemble the circuit on the breadboard using short leads. However, leave yourself enough room to make measurements. Also, remember that your scope probe tip will change the capacitance required at the end of the delay network. Here is a a picture of a 5ns, 50 ohm delay network built on the protoboard to give you a rough idea of what it should look like. Note both probes are using short ground leads..2 Figure 9: Delay line built on protoboard Measure the delay by using two scope probes (borrow one from a friend). This will be measured at the same points as your simulation. apture the waveform at both points with the scope and include in your lab report. Here is a scope capture of my 5ns, 50 ohm delay network. The actual delay is 5.7ns. The output waveform shape is maintained fairly well. The top trace is dly out, the bottom trace dly in. Note that the pedestal on dly in is 0ns; or twice the delay of the network. The network is working like an actual transmission line. The end of the pedestal on dly out corresponds to the reflection returning from the end of the network. You will learn more about this soon. 9

10 Figure 0: dly out (top) dly in (bottom) from 5ns, 50 ohm delay network Using the characteristics of voltage dividers and your measurements, determine the input impedance of your delay line. nclude your calculations in your lab report. Grading ast digit of student D T f Z o 0-5ns 00 ohms 2-3 0ns 00 ohms ns 70 ohms 6-7 7ns 70 ohms 8-9 7ns 4 ohms Table : Ds verses network values 0

11 Deliverable Grade Weighting Demonstratable, working prototype of delay line 30% Report, consisting of : spice file used to simulate the delay line you built 0% output from spice run showing delay and input impedance 0% scope picture showing dly in, dly out, and delay 30% calculation of input impedance 20% Poorly formatted writeup -0% an t make measurement from scope picture -20% ncorrect scope reading -20% an t read scope settings -20% Prototype circuit is obviously wrong -40% ate, up to one week -20% Table 2: Grading metrics