Novel Transient Cancellation Control Method for Future Generation of Microprocessors

Transcription

1 Novel Transient Cancellation Control Method for Future Generation of Microprocessors J.. bu-qahouq, N. Pongratananukul, I. atarseh, and T. Kasparis School of Electrical Engineering and Computer Science University of Central Florida Orlando, Florida 86, US STRCT - Future on-board low-voltage, high-current dcdc voltage regulator module (RM) requirements for a new generation of microprocessors are increasingly becoming stricter than ever as the demand for high dynamic performance and high power density converters with very small and limited output voltage deviation continues to increase. Future RMs may have to be proactive instead of reactive so that it can respond before the upcoming large load transients. new method to limit the RM output voltage variation under large load transients is proposed. This method to be known as Transient Cancellation Control will be presented in this paper and how it reduces the output voltage overshoot/undershoot. I. INTRODUCTION It is expected that the required operating voltages for the microprocessors will decrease below in the next years while the drawn current from the power supply will increase, in order to reduce the power consumption while increasing the microprocessor speed and its integration density. s a result, one of the design challenges is to limit the output voltage deviation below % of the nominal output voltage. Moreover, overshoots and undershoots under transients are more prominent and still must be limited below % of the nominal output voltage. s the processor supply voltage becomes lower, the allowed voltage deviation during the load transient becomes tighter [-6]. Distributed power system can be used to satisfy the overall system requirements by using on-board voltage regulator module (RM) located near the processor. To achieve high current slew rate at both step-up and step-down transients, assuming that the closed loop has sufficient bandwidth, the low voltage RM output inductor ( L o ) should be as small as possible. Unfortunately, using small output inductor to achieve faster transient response will cause the output voltage ripple to increase and push the RM operation towards discontinuous mode of operation. In order to reduce output voltage ripple, it is required that the switching frequency be increased. However, the higher the switching frequency, the lower the efficiency, making the selection of the switching devices very important step in the converter design process. It is also possible to reduce the output voltage ripple by increasing the output capacitor, resulting in a physically large size for practical design. In order to achieve the tight allowable deviation requirement of less than % out of output voltage of or lower with a fast transient response, the future RMs may have to be proactive instead of reactive. This means that the RM has to take a response action before the load transients occur instead of after. To make this possible, the RM controller somehow has to know that the load is going to change. This can be achieved if the RM controller receives a signal of an upcoming transient, this signal can be provided by a hardware or software, or maybe it can be predicted. In this paper, a new overshoot/undershoot cancellation control scheme that can reduce the overshoot and undershoot at large load transients by about % will be proposed. This control scheme can be applied to any RM, single-phase or multiphase, with any control method and makes it possible to allow the RM to be proactive (respond before transients occur) instead of being reactive (respond after transients occur). In the next section, the proposed method will be presented. Section III will show how to apply it to a Hysteretic Controlled RM for a Microprocessor. Simulation results will be shown in Section I followed by experimental work in Section. Section I will present a future look. Finally, Section II will present the conclusion. II. PROPOSED TRNSIENT CNCELLTION CONTROL SCHEME The idea of the transient cancellation control scheme is to create a deliberate undershoot before an expected overshoot and vice versa to cancel the expected large overshoot to keep the output voltage within the allowable output voltage deviation limit. s an example, Figure (a) shows a typical output voltage waveform at high-to-low load transient with an overshoot of OS. Let us assume that the maximum allowable voltage deviation (that is required to be achieved) is % of the current OS that certain RM has. Then, by creating an opposite undershoot with about % OS peak we can reduce the overshoot peak to about % OS as shown in Figure (b). This is obvious since the overshoot in this example will starts from o,n ( % OS ), where o,n is the nominal output voltage in steady state operation, and overshoot to -78--//$7. (c) IEEE 6

2 o,n ( % OS ) instead of starting at o,n and overshoot to o,n ( % OS ). The Transient Cancellation Controller should act only for a very short time exactly before the high-to-low load transient overshoot (or low-to-high load transient undershoot) occurs to create an undershoot (or overshoot) within the allowable maximum output voltage deviation. The transient cancellation control scheme requires creating a short control pulse ( C OT ) before the load changes to initiate the opposite transient to the expected transient through a logic stage as shown in Figure (). If the uck converter(s), single-phase or multi-phase, is taken as an example, then the signal C OT should turn OFF the high-side switch(es) and ON the low-side switch(es) when overshoot is expected and vice versa when an undershoot is expected. Then, this opposite transient signal should be deactivated just before the transient (load change) occurs. Figure (): Simplified Controller lock Diagram The first question that comes to mind is how to control the timing and the duration of the opposite transient signal? The answer to such question will become clear in the next section by applying the transient cancellation technique to a single phase hysteretic controlled RM for a microprocessor. III. PPLYING TRNSIENT CNCELLTION SCHEME TO HYSTERETIC CONTROLLED RM FOR MICROPROCESSOR (a) (b) Figure (): Ideal Output-ltage Waveforms at High-to-Low Load Transient: (a) without the Transient Cancellation Controller and (b) with the Transient Cancellation Controller Figure () shows the Orcad/Pspice schematics (for the simulation purposes) for a single-phase hysteretic controlled buck RM with the new transient cancellation control scheme being applied to it. This schematic includes the following parts:. The Power Stage.. The Load.. The Main Hysteretic Comparator for the main control Signal Generation. 4. Transient Hysteresis Comparator with wider hysteresis band than the main hysteresis comparator.. Opposite Transient Circuit part. 6. Final Stage Logic Circuit. 7. The Computer Power Management Control Signal Emulation for the Sleep and ctive modes part. The operation of the RM in Figure () can be summarized as follows: The main hysteresis comparator maintains the output voltage of the power stage around the required value with small ripple during steady state. "MCS" and "MCS" in part (6) are the final control signals that control the power stage switches. "MCS" and "MCS" in part (6) are equal to the output of the main hysteresis comparator "MCS" and "MCSn" in part () as long as the signals "MS_OFF" (Main Switch(es) OFF) and "MS_ON" (Main Switch(es) ON) are low. Suppose that at certain time a request for sleep mode is generated from the power management controller [7] 7

3 in MCS S - - D Lo () Load - Microprocessor U U in.8uh I MCS MCS in - MCS S - - D m Co Ro 6m Rt. MS_OFF MCSn MS_ON U 74 U4 748 U 748 U4 74 MCS () Power Stage Load_Current - S_Sleep - - Sbreak S_ctive - - U4Sbreak (7)Power Managemet Signals for Sleep and ctive Modes (6) Control Circuit Final S Sleep ctive TOPEN = u U9 PM_Sleep TCLOSE = u U TOPEN = u U7 ( (%IN) -(%IN) )* ref ( -(%IN) (%IN) )* ref.7 - U PR 4 J E Q CLK 6 4 K CL Q R 7476 MCS MCS U MCSn TCLOSE = u U4 PM_ctive () First Stage Comparator to Generate Main Control Signal C PM_Sleep END_Sleep_OT U4 748 MS_OFF PM_ctive END_ctive_OT U 748 MS_ON U4 U4x TL.4 - ( -(%IN) (%IN) )* LTL End_Sleep_O T U8 TOPEN = u 4 Q C U46 Q 6 Q D Q D UTL End_ctive_OT U44 TOPEN = u 4 Q C U9 Q 6 Q D Q D LTL U6 U6x TH. - ( (%IN) -(%IN) )* UTL Sleep U TOPEN = u 4 Q C U47 Q 6 Q D Q D LTL ctive U4 TOPEN = u 4 Q C U4 Q 6 Q D Q D UTL (4) Transient Hyteresis C Sleep Mode Opposite Transient () Opposite Transient ctive Mode Opposite Transient Figure (): Transient Cancellation Scheme being applied to a single phase hysteretic controlled RM to the microprocessor (This signal is emulated by part (7) for the simulation purposes). efore the sleep mode signal (denoted by the "PM_Sleep") is sent to the microprocessor (the load), an opposite transient action will take a place first. The "PM_Sleep" signal activates the sleep mode opposite transient circuit in part () through an ND gate by switching from low to high. The other input for this ND gate, denoted by "END_Sleep_OT", is high at that time (this signal indicates the time that the opposite transient should end). "END_Sleep_OT" is generated by a bistable latch ( here) [8], This function can also be implemented by a DSP. The state of this latch ("Q" or "END_Sleep_OT") is equal to the signal at terminal "D" when terminal "C" is high. If terminal "C" is low, terminal "Q" will keep the same state. s long as the output voltage did not hit the upper limit of the transient hysteresis comparator (part (4)), the signal "UTL" will be low and hence "END_Sleep_OT" will be high (or it is better to end the opposite transient signal when the output voltage hits the upper limit of the steady-state hysteresis window and generate the signal UL to guarantee that this will occur). From the above, it is clear that the signal "MS_OFF" (Main Switch(es) OFF) will go high when "PM_Sleep" goes high. When "MS_OFF" in part () goes high, MCS in part (6) goes low and MCS high. This will turn OFF the high side switch(es) and turn ON the low side switch(es) which creates an undershoot in the output voltage. The output voltage keeps decreasing until it hits the lower limit of the transient hysteresis comparator in part (4) because of the undershoot causing the signal "LTL" to go high. The 8

4 second bistable latch in the Sleep Mode Opposite Transient Logic receives this signal which cause the signal "Sleep" to go low. The "Sleep" signal causes the load (the microprocessor) in part () to switch to the sleep mode (high load to low load) which creates an overshoot after the undershoot. The output voltage keeps increasing until it hits the upper limit of the transient hysteresis comparator (or the upper limit of the steady-state hysteresis window to guarantee that this will occur) because of the overshoot causing the signal "UTL" to go high which causes the signal END_Sleep_OT to go low ending the effect of the signal MS_OFF when it goes low. t this time, the main hysteresis comparator picks up to resume regulating the output voltage in the new low load state until an ctive Mode request initiated to activate the ctive Mode Opposite Transient Circuit which has an operation similar to the Sleep Mode Opposite Transient Circuit. Figure (4) shows the basic transient cancellation control scheme timing signals in the case of the sleep mode request. o =., I =, L = L = 8. µ H, and C = mf, o phase phase with steady-state hysteretic band of ±m and transient hysteretic band of ±4m with load transient from to and vice versa. Figure () shows the simulation results without the transient cancellation part while Figure (6) shows the simulation results with the transient cancellation part for the same design. y comparing Figures () and (6), the overshoot was m and the undershoot was m without the Transient Cancellation part compared to 8m overshoot and m undershoot with the OTSC part. This means that the maximum voltage deviation reduced from m without the transient cancellation scheme to 8m with the transient cancellation scheme, which is a reduction of more than %. Even though in the actual experimental setup the reduction is expected to be less than % because of the controller delay time, it is expected that a reduction of at least 4% is expected by selecting fast components or integrating the transient cancellation control scheme function in a single chip. Moreover, the transient time in both cases was almost the same, i.e., the transient cancellation scheme did not increase the RM transient response time as can be noted from Figures () and (6). These results are obtained from simple design with a singlephase RM. etter results are expected when multiphase is used. o. EXPERIMENTL WORK Figure (4): asic Sleep Mode Transient Cancellation Controller Timing Waveforms I. SIMULTION RESULTS The RM in Figure () was simulated in Orcad/Pspice for verification with the following design parameters: =, in The transient cancellation scheme functionality was experimented by using a programmable DSP chip (real-time DSP processor). Figure (7) shows the DSP input/output signal flow block diagram while Figure (8) shows the simplified DSP program flowchart. Let us define the following: PM_Sleep/ctive signal is the Sleep/ctive Mode request signal. Logic indicates ctive Mode Request and logic indicates Sleep Mode Request from the Power Management Controller [7]. Sleep/ctive signal is the load Sleep/ctive status signal. Logic tells the load to go to the ctive Mode while logic tells the load to go to the Sleep Mode. o is the power stage (RM) output voltage. S and S are the high side and low side power stage (RM buck converter) switches control signals, respectively. L and H are the lower and upper steady state output voltage hysteresis limits, respectively. LT and HT are the lower and upper transient output voltage hysteresis limits, respectively. Where LT < L and >. HT H 9

5 Figure (): Simulation Results without the Transient Cancellation Controller Figure (6): Simulation Results with the Transient Cancellation Controller Figure (7): The DSP input/output Signal Flow lock Diagram Istatus and Ostatus are the current status for the PM_Sleep/ctive and Sleep/ctive signals, respectively. The DSP algorithm is divided into three modes and can be briefly explained as follows (Figure (8)): (Set Initially PM_Sleep/ctive= and Sleep/ctive= to indicate ctive Mode status or set PM_Sleep/ctive= and Sleep/ctive= to indicate Sleep Mode status) Figure (8): DSP Program Flowchart. Steady-State Mode: Set Istatus=PM_Sleep/ctive, and Ostatus= Sleep/ctive. When < L, set S ON and S OFF. Sleep/ctive=No Change. When > H, set S OFF and S ON. Sleep/ctive=No Change. Check PM_Sleep/ctive. If PM_Sleep/ctive= Istatus, stay in the Steady-State Mode, otherwise, if PM_Sleep/ctive=, go to the ctive Transient Mode (Mode ) or if PM_Sleep/ctive=, go to the Sleep Transient Mode (Mode ).

6 . Sleep Transient Mode: Set S OFF and S ON. When < OL, set Sleep/ctive= (pass Sleep Mode signal to the load). When > H, go back to the Steady-Sate Mode (Mode ). deviation to decrease compared to Figure 9(a). ll with the slow MHz TMSF47 DSP board, which limits the switching frequency, the minimum output voltage ripple, and the minimum overshoot/undershoot. s mentioned previously in this section, much faster DSP must be used in the future.. ctive Transient Mode: Set S ON and S OFF. When, > OH, set Sleep/ctive= (pass ctive Mode signal to the load). When < L, go to the Steady-Sate Mode (Mode ). In addition to the importance of careful design of the multiphase power stage, the selection of the DSP chip and the nalog to Digital Converter (DC) is very important. Some of the most important parameters in the selection of the DSP and DC are their speed and noise sensitivity and the DC resolution. The laboratory availability was for the TI DSP Chip and Evaluation Module of TMSLF47 [9] which has ns Instruction Cycle Time ( MHz), which is relatively slow for this application (Refer to [9] for more information on TMSLF47). This chip is geared toward control applications. However, it lacks the processing speed (MHz). In addition, increase in processing power is necessary for advance control methods in the future. Hence, even though this DSP chip is used here for initial experimental verification, the experimental work has to be and will be implemented in a faster DSP to achieve faster response, lower output voltage ripple, better current sharing accuracy, higher switching frequency, and better stability. good candidate is the C64x DSP family has a speed range of 4-6MHz [], i.e., instruction cycles in the range of.ns to.67ns. This DSP will be used in the future to repeat the experimental work. Moreover, future DSP chips speed will break the GHz speed limit []. The DC used here is the TI -bit MHz DS87 []. The RM power stage includes single-phase buck converter with the following main components: MOSFETs: SI44DY. Output Capacitors: SNYO OSCON of 8uF, 4. Output Inductors: 8, uh, T68-8/9 Core, 7-turns, 6WG Wire. MOSFETs Driver: TPS86. in=- input voltage source. Figure (9) shows some experimental results when the load switch from high current to low current as in the sleep mode. In this case, output voltage overshoot is expected. Thus, the controller creates a deliberate undershoot before the load transient. In Figure 9(b), the deliberate undershoot was slightly increased which caused the natural overshoot peak (a) (b) Figure (9): Experimental Results I. FUTURE LOOK FOR SMRT CONTROL METHODS The current drawn from the RM by a microprocessor is continuously changing depending on the activity. On the other hand, high frequency RMs as any power electronics system, is a complex combination of linear, nonlinear, and switching elements that is required to have fast dynamics. Moreover, this complex combination is a also real-time system that needs to continuously and instantly monitor and respond to the load changes. high performance control loop is essential to follow up with such transients. Such controller design is complicated especially since it requires extensive knowledge of the converter and its behavior and accurate converter modeling

7 that includes nonlinearities, parameters, and components variations. In the future, RMs may have to be proactive instead of reactive, i.e, to be able to take a response action before the load transients occur instead of after, in able to satisfy the ever increasing stringent powering requirements. Future RM controllers may need to be able to learn the load behavior and/or apply advanced response techniques to reduce the RM output voltage overshoots/undershoots and to have fast transient response. Methods such as fuzzy logic and neural networks may be applied to make the RM controller smart. We envision advanced control methods and system monitoring integrated into a single smart controller, with programmed algorithms, using programmable real-time DSP. Circuits," IEEE Transaction on Power Electronics, l., Issue, pp.8-7, March 996. [7]. Intel Corporation, "88 ICH and 88M ICH-M Datasheet". [8]. Texas Instruments, "Data Sheet of SN Chip". [9]. Texas Instruments, "Data Sheet of TMSLF47 DSP Chip ". []. Texas Instruments, "Data Sheets of TMSC644, TMSC64, and TMSC646 DSP Chips ". []. Texas Instruments, " TMSC6 DSP RODMP". []. Texas Instruments, " Datasheet of DS87 DC. II. CONCLUSION new control method that reduces the overshoot and undershoot voltage deviations under large load transients for new generation of microprocessors was proposed. simulated scheme showed how to apply this method to microprocessor RMs. oth simulation results and experimental results agreed with the expected waveforms. It was shown how this scheme could effectively cut the output voltage deviation for an existing controlled RM during load transients by about %. REFERENCES []. P. Wong, F. Lee, X. Zhou and J. Chen, ltage Regulator Module (RM) Transient Modeling and nalysis, IEEE 4 th nnual Industry pplications Conference Record, IS 99, l., pp , 999. []. Intel pplication Note P-9, Pentium III Xeon TM Processor Power Distribution Guidelines, March 999. [].. rbetter and D. Maksimocic, DC-DC Converter with Fast Transient Response and High Efficiency for Low-ltage Microprocessor Loads, IEEE Thirteenth nnual pplied Power Electronics Conference and Exposition, PEC 98, l., pp. 6-6, 998. [4]. Intel Documents, "RM 8., 8.4, and 9. DC-DC Converter Design Guidelines." []. Y. Panov and M. Jovanovic, Design Considerations for -/.-, - ltage Regulator Modules, IEEE Fifteenth nnual pplied Power Electronics Conference and Exposition, PEC, l., pp. 9-46,. [6]. M. Zhang, M. Jovanovic and F. Lee, "Design Considerations for Low-ltage On-oard DC/DC Modules for Next Generations of Data Processing