NuMicro Family NUC029 Series Datasheet

Transcription

1 SERIES DATASHEET ARM Cortex -M0 32-bit Microcontroller NuMicro Family Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. Dec. 11, 2017 Page 1 of 102 Rev 1.04

2 SERIES DATASHEET Table of Contents LIST OF FIGURES... 6 LIST OF TABLES GENERAL DESCRIPTION FEATURES ABBREVIATIONS PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro Series Selection Guide Pin Configuration NuMicro Pin Diagram Pin Description NuMicro Pin Description FUNCTIONAL DESCRIPTION ARM Cortex -M0 Core System Manager Overview System Reset System Power Distribution System Memory Map Whole System Memory Mapping System Timer (SysTick) Nested Vectored Interrupt Controller (NVIC) Clock Controller of NuMicro xan Overview System Clock and SysTick Clock Power-down Mode Clock Frequency Divider Output Clock Controller of NuMicro FAE Overview System Clock and SysTick Clock ISP Clock Source Selection Module Clock Source Selection Power-down Mode Clock Flash Memory Controller (FMC) Overview Dec. 11, 2017 Page 2 of 102 Rev 1.04

3 SERIES DATASHEET Features External Bus Interface (EBI) (LAN/NAN Only) Overview Features General Purpose I/O (GPIO) Overview Features Timer Controller (TIMER) Overview Features PWM Generator and Capture Timer (PWM) (xan Only) Overview Features Enhanced PWM Generator (FAE Only) Overview Features Watchdog Timer (WDT) Overview Features Window Watchdog Timer (WWDT) (xan Only) Overview Features UART Interface Controller (UART) Overview Features I 2 C Serial Interface Controller (I 2 C) Overview Features Serial Peripheral Interface (SPI) Overview Features Analog-to-Digital Converter (ADC) Overview Features Analog Comparator (ACMP) Dec. 11, 2017 Page 3 of 102 Rev 1.04

4 SERIES DATASHEET Overview Features Hardware Divider (HDIV) (xan Only) Overview Features APPLICATION CIRCUIT XAN ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings DC Electrical Characteristics AC Electrical Characteristics External Input Clock External 4~24 MHz High Speed Crystal (HXT) Internal MHz High Speed RC Oscillator (HIRC) Internal 10 khz Low Speed RC Oscillator (LIRC) Analog Characteristics bit SAR ADC Specification LDO and Power Management Specification Low Voltage Reset Specification Brown-out Detector Specification Power-on Reset Specification Temperature Sensor Specification Comparator Specification Flash DC Electrical Characteristics FAE ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings DC Electrical Characteristics AC Electrical Characteristics External Input Clock External 4~24 MHz High Speed Crystal (HXT) Internal MHz High Speed RC Oscillator (HIRC) Internal 10 khz Low Speed RC Oscillator (LIRC) Analog Characteristics bit SAR ADC Specification LDO and Power Management Specification Low Voltage Reset Specification Dec. 11, 2017 Page 4 of 102 Rev 1.04

5 SERIES DATASHEET Brown-out Detector Specification Power-on Reset Specification Comparator Specification Flash DC Electrical Characteristics PACKAGE DIMENSIONS pin LQFP (7x7x1.4 mm) pin QFN (7x7x0.8 mm) pin QFN (5x5x0.75 mm) pin QFN (4x4x0.75 mm) pin TSSOP (6.5x4.4x1.2 mm) REVISION HISTORY Dec. 11, 2017 Page 5 of 102 Rev 1.04

6 SERIES DATASHEET LIST OF FIGURES Figure 4-1 NuMicro Series Selection Code Figure 4-2 NuMicro LAN LQFP 48-pin Diagram Figure 4-3 NuMicro NAN QFN 48-pin Diagram Figure 4-4 NuMicro ZAN/TAN QFN 33-pin Diagram Figure 4-5 NuMicro FAE TSSOP 20-pin Diagram Figure 5-1 Functional Controller Diagram Figure 5-2 NuMicro xan Power Distribution Diagram Figure 5-3 NuMicro FAE Power Distribution Diagram Figure 5-4 NuMicro xan Whole System Memory Mapping Figure 5-5 NuMicro FAE Whole System Memory Mapping Figure 5-6 NuMicro xan Clock Generator Block Diagram Figure 5-7 NuMicro xan Clock Source Controller Overview (1/2) Figure 5-8 NuMicro xan Clock Source Controller Overview (2/2) Figure 5-9 NuMicro xan System Clock Block Diagram Figure 5-10 NuMicro xan SysTick Clock Control Block Diagram Figure 5-11 NuMicro xan Clock Source of Frequency Divider Figure 5-12 NuMicro xan Frequency Divider Block Diagram Figure 5-13 NuMicro FAE Clock Generator Block Diagram Figure 5-14 NuMicro FAE System Clock Block Diagram Figure 5-15 NuMicro FAE SysTick Clock Control Block Diagram Figure 5-16 NuMicro FAE AHB Clock Source for HCLK Figure 5-17 NuMicro FAE Peripherals Clock Source Selection for PCLK Figure 7-1 xan Typical Crystal Application Circuit Figure 7-2 xan Power-up Ramp Condition Figure 8-1 FAE Typical Crystal Application Circuit Figure 8-2 xan Power-up Ramp Condition Dec. 11, 2017 Page 6 of 102 Rev 1.04

7 SERIES DATASHEET LIST OF TABLES Table 1-1 NuMicro Series Difference List... 8 Table 3-1 List of Abbreviations Table 4-1 NuMicro Series Selection Guide Table 5-1 NuMicro xan Address Space Assignments for On-Chip Controllers Table 5-2 NuMicro FAE Address Space Assignments for On-Chip Controllers Table 5-3 Exception Model Table 5-4 NuMicro xan System Interrupt Map Table 5-5 NuMicro FAE System Interrupt Map Table 5-6 Vector Table Format Table 5-7 NuMicro FAE Peripheral Clock Source Selection Table Dec. 11, 2017 Page 7 of 102 Rev 1.04

8 SERIES DATASHEET 1 GENERAL DESCRIPTION The NuMicro series 32-bit microcontroller is embedded with ARM Cortex -M0 core for industrial control and applications which need rich communication interfaces or require high performance, high integration, and low cost. The Cortex -M0 is the newest ARM embedded processor with 32-bit performance at a cost equivalent to the traditional 8-bit microcontroller. The NuMicro series includes four part numbers: LAN, NAN, ZAN, TAN and FAE. The LAN/NAN/ZAN/TAN can run up to 50 MHz and operate at 2.5V ~ 5.5V, -40 ~ 85, and the FAE can run up to 24 MHz and operate at 2.5V ~ 5.5V, -40 ~ 105. Therefore, the series can afford to support a variety of industrial control and applications which need high CPU performance. The LAN/NAN/ZAN/TAN offers 64K/64K/32K bytes flash, 4 Kbytes Data Flash, 4 Kbytes flash for the ISP, and 4 Kbytes SRAM. The FAE offers 16 Kbytes flash, size configurable Data Flash (shared with program flash), 2 Kbytes flash for the ISP, and 2K-bytes SRAM. Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer, UART, SPI, I 2 C, PWM, ADC, WDT (Watchdog Timer), WWDT (Window Watchdog Timer), Analog Comparator and Brown-out Detector, have been incorporated into the series in order to reduce component count, board space and system cost. These useful functions make the series powerful for a wide range of applications. Additionally, the NuMicro series is equipped with ISP (In-System Programming) and ICP (In-Circuit Programming) functions, and IAP (In-Application Programming), which allow the user to update the program memory without removing the chip from the actual end product. Item LAN/NAN/ ZAN/TAN FAE Core Up to 50 MHz Up to 24 MHz Operating Temp. -40 ~ ~ +105 Hardware Divider - Clock Control Supports PLL as clock source - - Supports external khz crystal oscillator as clock source Window WDT - PWM PWM Generator and Capture Timer Enhanced PWM Generator ADC 12-bit SAR ADC with 760 ksps (Supports Single, Burst, Single-Cycle, and Continuous Scan mode) 10-bit SAR ADC with 300 ksps (Only supports Single mode) EBI - Built-in Temp.Sensor - Table 1-1 NuMicro Series Difference List Dec. 11, 2017 Page 8 of 102 Rev 1.04

9 SERIES DATASHEET 2 FEATURES ARM Cortex -M0 core Runs up to 50 MHz One 24-bit system timer Supports Low Power Sleep mode A single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints Provides hardware divider and supports signed 32-bit dividend, 16-bit divisor operation(xan only) Operating voltage ranges from 2.5 V to 5.5 V Memory 16/32/64 KB Flash for program memory (APROM) Up to 4 KB Flash for loader (LDROM) Up to 4 KB SRAM for internal scratch-pad RAM (SRAM) 4 KB Flash for data memory (Data Flash) (xan only) Configurable Data Flash (FAE only) Clock Control Programmable system clock source MHz internal oscillator Dynamically calibrating the HIRC OSC to MHz ±3% from -40 to 105 by external khz crystal oscillator (LXT) (FAE only) 4~24 MHz external crystal input 10 khz low-power oscillator for Watchdog Timer and wake-up in Sleep mode PLL allows CPU operation up to the maximum 50 MHz (xan only) khz external crystal input (LXT) for Power-down wake-up and system operation clock (FAE only) GPIO Up to 40 general-purpose I/O (GPIO) pins for LQFP/QFN 48-pin package Four I/O modes: Quasi-bidirectional Push-pull output Open-drain output Input only with high impendence TTL/Schmitt trigger input selectable I/O pin can be configured as interrupt source with edge/level setting Supports high driver and high sink I/O mode Configurable I/O mode after POR Timer Up to four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter Independent clock source for each timer Provides up to four timer counting modes: one-shot, periodic, toggle and continuous counting 24-bit up counter value is readable through TDR (Timer Data Register) Supports event counting function to count the input event from external counter pin 24-bit capture value is readable through TCAP (Timer Capture Data Register) Supports external capture pin for interval measurement Supports external capture pin to reset 24-bit up counter Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated Supports internal capture triggered while internal ACMP output signal transition Dec. 11, 2017 Page 9 of 102 Rev 1.04

10 SERIES DATASHEET (xan only) Supports Inter-Timer trigger mode (xan only) Supports internal signal (CPO0, CPO1) for interval measurement (FAE only) WDT (Watchdog Timer) Multiple clock sources Supports wake-up from Power-down or Sleep mode Interrupt or reset selectable on watchdog time-out Time-out reset delay period can be selected to 3/18/130/1026 * WDT_CLK (xan only) WWDT (Window Watchdog Timer) (xan only) 6-bit down counter with 11-bit pre-scale for wide range window selected PWM Generator and Capture Timer (xan only) Up to four built-in 16-bit PWM generators, providing eight PWM outputs or four complementary paired PWM outputs Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for each PWM generator PWM interrupt synchronized to PWM period 16-bit digital Capture timers with rising/falling capture inputs Supports capture interrupt Internal 10 khz to PWM clock source Polar inverse function Center-aligned type function Timer duty interrupt enable function Two kinds of PWM interrupt period type selection Two kinds of PWM interrupt duty type selection Period/duty trigger ADC function PWM Timer synchronous start function Enhanced PWM Generator (FAE only) Independent 16-bit PWM duty control units with maximum three outputs Supports group/synchronous/independent/ complementary modes Supports One-shot or Auto-reload mode Supports Edge-aligned and Center-aligned type Programmable dead-zone insertion between complementary channels Each output has independent polarity setting control Hardware fault brake protections Supports duty, period, and fault break interrupts Supports duty/period trigger ADC conversion Timer comparing matching event trigger PWM to do phase change Supports comparator event trigger PWM to force PWM output low for current period Provides interrupt accumulation function UART Up to two sets of UART devices Programmable baud-rate generator Buffered receiver and transmitter, each with 16 bytes FIFO Optional flow control function (CTS and RTS) Supports IrDA(SIR) function Supports RS-485 function Supports LIN function (xan only) SPI Up to two sets of SPI devices Supports Master/Slave mode Dec. 11, 2017 Page 10 of 102 Rev 1.04

11 SERIES DATASHEET Full-duplex synchronous serial data transfer Provides 3 wire function Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Rx latching data can be either at rising edge or at falling edge of serial clock Tx sending data can be either at rising edge or at falling edge of serial clock Supports Byte Suspend mode in 32-bit transmission 4-level depth FIFO buffer PLL clock source (xan only) I 2 C Up to two sets of I 2 C modules Supports Master/Slave mode Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allow versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) Supports Power-down wake-up function Supports FIFO function (FAE only) ADC 12-bit SAR ADC with 760 ksps for xan, and 10-bit SAR ADC with 300 ksps for FAE Up to eight single-end analog input channels Or four differential analog input channels (xan only) Four operation modes (FAE only support Single mode) Single mode: A/D conversion is performed one time on a specified channel Burst mode: A/D converter samples and converts the specified single channel and sequentially stores the result in FIFO Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode until software stops A/D conversion An A/D conversion can be started by: Software Write 1 to ADST bit External pin (STADC) PWM trigger with optional start delay period Each conversion result is held in data register with valid and overrun indicators Each channel has individual data register (xan only) Conversion result can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting Internal temperature sensor output (xan only) Analog Comparator Up to four sets of Comparator analog modules External input or internal band-gap voltage selectable at negative node Interrupt when compared results change Power-down wake-up Dec. 11, 2017 Page 11 of 102 Rev 1.04

12 SERIES DATASHEET EBI (External Bus Interface) for external memory-mapped device access (LAN/ NAN only) Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode Supports 8-bit or 16-bit data width Supports byte-write in 16-bit data width ISP (In-System Programming) and ICP (In-Circuit Programming) IAP (In-Application Programming) One built-in temperature sensor with 1 resolution (xan only) BOD (Brown-out Detector) With 4 levels: 4.4V/3.7V/2.7V/2.2V Supports Brown-out interrupt and reset option 96-bit unique ID (UID) LVR (Low Voltage Reset) Threshold voltage level: 2.0V Operating Temperature: LAN/NAN/ZAN/TAN: -40 ~85 FAE:-40 ~105 Reliability: EFT > ± 4 KV, ESD HBM pass 4 KV Packages: All Green package (RoHS) 48-pin LQFP, 48-pin QFN, 33-pin QFN, 20-pin TSSOP Dec. 11, 2017 Page 12 of 102 Rev 1.04

13 SERIES DATASHEET 3 ABBREVIATIONS Acronym ACMP ADC APB AHB BOD EBI FIFO FMC GPIO HCLK HIRC HXT IAP ICP ISP LDO LIN LIRC LXT NVIC PCLK PLL PWM SPI SPS TMR UART UCID USB WDT WWDT Description Analog Comparator Controller Analog-to-Digital Converter Advanced Peripheral Bus Advanced High-Performance Bus Brown-out Detection External Bus Interface First In, First Out Flash Memory Controller General-Purpose Input/Output The Clock of Advanced High-Performance Bus MHz Internal High Speed RC Oscillator 4~24 MHz External High Speed Crystal Oscillator In Application Programming In Circuit Programming In System Programming Low Dropout Regulator Local Interconnect Network 10 khz internal low speed RC oscillator (LIRC) khz External Low Speed Crystal Oscillator Nested Vectored Interrupt Controller The Clock of Advanced Peripheral Bus Phase-Locked Loop Pulse Width Modulation Serial Peripheral Interface Samples per Second Timer Controller Universal Asynchronous Receiver/Transmitter Unique Customer ID Universal Serial Bus Watchdog Timer Window Watchdog Timer Table 3-1 List of Abbreviations Dec. 11, 2017 Page 13 of 102 Rev 1.04

14 SERIES DATASHEET Part Number APROM (KB) RAM (KB) Data Flash (KB) ISP ROM (KB) I/O Timer (32-Bit) UART SPI I 2 C PWM (16-bit) ADC (12-bit) ADC (10-bit) Comparator WDT WWDT EBI PLL khz Crystal Oscillator ISP/ICP/IAP Package Operating Temperature Range( ) 4 PARTS INFORMATION LIST AND PIN CONFIGURATION 4.1 NuMicro Series Selection Guide Connectivity LAN LQFP48-40 to +85 NAN QFN48-40 to +85 ZAN * - - TAN * - - QFN33 (5x5) QFN33 (4x4) -40 to to +85 FAE 16 2 Config ** TSSOP20-40 to +105 Note: *: ACMP3 only has positive and negative input. Table 4-1 NuMicro Series Selection Guide **: ACMP0 only has positive and negative input, and ACMP1 only has positive input. Dec. 11, 2017 Page 14 of 102 Rev 1.04

15 SERIES DATASHEET X X X CPU core ARM Cortex M0 Part Number Temperature N: - 40 ~ + 85 E: -40 ~ +105 Package L: LQFP 48 N: QFN 48 Z: QFN 33 (5x5) T: QFN 33 (4x4) F: TSSOP 20 Reserved Figure 4-1 NuMicro Series Selection Code Dec. 11, 2017 Page 15 of 102 Rev 1.04

16 SERIES DATASHEET 4.2 Pin Configuration NuMicro Pin Diagram NuMicro LAN LQFP 48 pin RXD, RTS0, AD3, P0.3 TXD, CTS0, AD2, P0.2 ACMP3_N, RXD1, RTS1, AD1, P0.1 ACMP3_P, TXD1, CTS1, AD0, P0.0 VDD AVDD nwrl, T2,AIN0,P1.0 nwrh, T3,AIN1,P1.1 RXD1,AIN2, P1.2 TXD1,AIN3,P1.3 ACMP0_N, SPISS0,AIN4,P1.4 PWM2, P ACMP0_P, MOSI_0, AIN5, P P4.1, PWM1, T3EX ACMP2_N, MISO_0, AIN6, P P0.4, AD4, SPISS1 ACMP2_P, SPICLK0, AIN7, P P0.5, AD5, MOSI_1 nrst 4 33 P0.6, AD6, MISO_1 ACMP1_N, RXD, P P0.7, AD7, SPICLK1 AV SS ACMP1_P, TXD, P LQFP-48 pin P4.7, ICE_DAT P4.6, ICE_CLK T0EX, STADC, nint0, P P4.5, ALE, SDA1 T1EX, MCLK, nint1, P P4.4, ncs, SCL1 SDA0, T0, P P2.7, AD15, PWM7 CKO, SCL0, T1, P P2.6, AD14, PWM6, ACMP1_O PWM3, P P2.5, AD13, PWM5, SDA P4.0, PWM0, T2EX P2.4, AD12, PWM4, SCL1 P2.3, AD11, PWM3 P2.2, AD10, PWM2 P2.1, AD9, PWM1 P2.0, AD8, PWM0 LDO_CAP VSS XTAL1 XTAL2 P3.7, nrd P3.6, nwr, CKO, ACMP0_O Figure 4-2 NuMicro LAN LQFP 48-pin Diagram Dec. 11, 2017 Page 16 of 102 Rev 1.04

17 SERIES DATASHEET NuMicro NAN QFN 48 pin QFN P4.1, PWM1, T3EX 2 P0.4, AD4, SPISS1 3 P0.6, AD6, MISO_1 4 P0.7, AD7, SPICLK P4.7, ICE_DAT P4.6, ICE_CLK LDO_CAP 8 P4.5, ALE, SDA1 9 P4.4, ncs, SCL1 10 P2.7, AD15, PWM P2.6, AD14, PWM6, ACMP1_O P2.5, AD13, PWM5, SDA1 ACMP0_O, CKO, nwr, P3.6 nrd, P3.7 XTAL2 XTAL1 VSS LDO_CAP PWM0, AD8, P2.0 PWM1, AD9, P2.1 PWM2, AD10, P2.2 PWM3, AD11, P2.3 SCL1, PWM4, AD12, P2.4 T2EX, PWM0, P4.0 P4.2, PWM2 P1.4, AIN4, SPISS0, ACMP0_N P1.3, AIN3, TXD1 P1.2, AIN2, RXD1 P1.1, AIN1, T3, nwrh P1.0, AIN0, T2, nwrl AVDD VDD P0.0, AD0, CTS1, TXD1, ACMP3_P P0.1, AD1, RTS1, RXD1, ACMP3_N P0.2, AD2, CTS0, TXD P0.3, AD3, RTS0, RXD ACMP0_P, MOSI_0, AIN5, P1.5 ACMP2_N, MISO_0, AIN6, P1.6 ACMP2_P, SPICLK0, AIN7, P1.7 nrst ACMP1_N, RXD, P3.0 AVSS ACMP1_P, TXD, P3.1 T0EX, STADC, nint0, P3.2 T1EX, MCLK, nint1, P3.3 SDA0, T0, P3.4 CKO, SCL0, T1, P3.5 PWM3, P VSS Figure 4-3 NuMicro NAN QFN 48-pin Diagram Dec. 11, 2017 Page 17 of 102 Rev 1.04

18 SERIES DATASHEET NuMicro ZAN/TAN QFN 33 pin ACMP3_N, RXD1, RTS1, P0.1 ACMP3_P, TXD1, CTS1, P0.0 VDD AVDD AIN0, T2, P1.0 RXD1, AIN2, P1.2 TXD1, AIN3, P1.3 ACMP0_N, AIN4, P ACMP0_P, AIN5, P1.5 nrst P0.4, SPISS1 P0.5, MOSI_1 ACMP1_N, RXD, P P0.6, MISO_1 AV SS ACMP1_P, TXD, P QFN-33 Pin P0.7, SPICLK1 P4.7, ICE_DAT T0EX, STADC, nint0, P P4.6, ICE_CLK SDA0, T0, P3.4 CKO, SCL0, T1, P VSS P2.6, PWM6, ACMP1_O P2.5, PWM5, SDA P2.4, PWM4, SCL1 P2.3, PWM3 P2.2, PWM2 LDO_CAP VSS XTAL1 XTAL2 P3.6, CKO, ACMP0_O Figure 4-4 NuMicro ZAN/TAN QFN 33-pin Diagram Dec. 11, 2017 Page 18 of 102 Rev 1.04

19 SERIES DATASHEET NuMicro FAE TSSOP 20 pin ACMP0_P,RXD,AIN2,P V DD ACMP0_P,TXD,AIN3,P P0.4,SPISS0,PWM5 ACMP0_N,AIN4,P P0.5,MOSI_0 ACMP0_P,AIN5,P1.5 nrst ACMP1_P,T0EX,STADC,nINT0,P TSSOP-20 Pin P0.6,MISO_0 P0.7,SPICLK0 P4.7,ICE_DAT ACMP1_P,SDA0,T0,P P4.6,ICE_CLK ACMP1_P,SCL0,T1,P P2.5,PWM3 XTAL2,P P2.4,PWM2 XTAL1,P V ss Figure 4-5 NuMicro FAE TSSOP 20-pin Diagram Dec. 11, 2017 Page 19 of 102 Rev 1.04

20 SERIES DATASHEET 4.3 Pin Description NuMicro Pin Description LQFP/QFN 48-pin Pin No. QFN 33-pin Pin Name Pin Type Description 1 1 P1.5 I/O General purpose digital I/O pin. AIN5 AI ADC5 analog input. ACMP0_P AI Comparator0 positive input pin. - MOSI_0 I/O SPI0 MISO (Master Out, Slave In) pin. P1.6 I/O General purpose digital I/O pin. 2 - AIN6 AI ADC6 analog input. MISO_0 I/O SPI0 MISO (Master In, Slave Out) pin. ACMP2_N AI Comparator2 negative input pin. P1.7 I/O General purpose digital I/O pin. 3 - AIN7 AI ADC7 analog input. SPICLK0 I/O SPI0 serial clock pin. ACMP2_P AI Comparator2 positive input pin. 4 2 nrst I (ST) External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. 5 3 P3.0 I/O General purpose digital I/O pin. RXD [2] I Data receiver input pin for UART0. ACMP1_N AI Comparator1 negative input pin. 6 4 AV SS AP Ground pin for analog circuit. P3.1 I/O General purpose digital I/O pin. 7 5 TXD [2] O Data transmitter output pin for UART0. ACMP1_P AI Comparator1 positive input pin P3.2 I/O General purpose digital I/O pin. 8 6 nint0 I External interrupt0 input pin. STADC I ADC external trigger input. T0EX I Timer0 external capture/reset trigger input pin. P3.3 I/O General purpose digital I/O pin. 9 - nint1 I External interrupt1 input pin. MCLK O EBI external clock output pin. TIEX I Timer1 external capture/reset trigger input pin P3.4 I/O General purpose digital I/O pin. Dec. 11, 2017 Page 20 of 102 Rev 1.04

21 SERIES DATASHEET LQFP/QFN 48-pin Pin No. QFN 33-pin Pin Name Pin Type Description T0 I/O Timer0 external event counter input pin SDA0 i/o I2C0 data input/output pin. P3.5 I/O General purpose digital I/O pin T1 I/O Timer1 external event counter input pin. SCL0 I/O I 2 C0 clock I/O pin. CKO [2] O Frequency divider output pin P4.3 I/O General purpose digital I/O pin. PWM3 [2] I/O PWM3 output/capture input P3.6 I/O General purpose digital I/O pin. CKO [2] O Frequency divider output pin. ACMP0_O O Analog comparator0 output pin. nwr O EBI write enable output pin P3.7 I/O General purpose digital I/O pin. nrd O EBI read enable output pin XTAL2 O External 4~24 MHz (high speed) crystal output pin XTAL1 I (ST) External 4~24 MHz (high speed) crystal input pin V SS P Ground pin for digital circuit LDO_CAP P LDO output pin. P2.0 I/O General purpose digital I/O pin AD8 I/O EBI Address/Data bus bit8 PWM0 [2] I/O PWM0 output/capture input. P2.1 I/O General purpose digital I/O pin AD9 I/O EBI Address/Data bus bit PWM1 [2] I/O PWM1 output/capture input. P2.2 I/O General purpose digital I/O pin. PWM2 [2] I/O PWM2 output/capture input. - AD10 I/O EBI Address/Data bus bit P2.3 I/O General purpose digital I/O pin. PWM3 [2] I/O PWM3 output/capture input. - AD11 I/O EBI Address/Data bus bit P2.4 I/O General purpose digital I/O pin. Dec. 11, 2017 Page 21 of 102 Rev 1.04

22 SERIES DATASHEET LQFP/QFN 48-pin Pin No. QFN 33-pin Pin Name Pin Type Description PWM4 I/O PWM4 output/capture input. SCL1 [2] I/O I 2 C1 clock I/O pin. - AD12 I/O EBI Address/Data bus bit12. P4.0 I/O General purpose digital I/O pin PWM0 [2] I/O PWM0 output/capture input T2EX I Timer2 external capture/reset trigger input pin. P2.5 I/O General purpose digital I/O pin. PWM5 I/O PWM5 output/capture input. SDA1 [2] i/o I2C1 data input/output pin. - AD13 I/O EBI Address/Data bus bit13. P2.6 I/O General purpose digital I/O pin PWM6 I/O PWM6 output/capture input. ACMP1_O O Analog comparator1 output pin. - AD14 I/O EBI Address/Data bus bit14. P2.7 I/O General purpose digital I/O pin AD15 I/O EBI Address/Data bus bit15. PWM7 I/O PWM7 output/capture input. P4.4 I/O General purpose digital I/O pin ncs O EBI chip select enable output pin. SCL1 [2] I/O I 2 C1 clock I/O pin. P4.5 I/O General purpose digital I/O pin ALE O EBI address latch enable output pin. SDA1 [2] i/o I2C1 data input/output pin P4.6 I/O General purpose digital I/O pin. ICE_CLK I Serial Wired Debugger Clock pin. P4.7 I/O General purpose digital I/O pin. ICE_DAT I/O Serial Wired Debugger Data pin P0.7 I/O General purpose digital I/O pin. SPICLK1 I/O SPI1 serial clock pin. - AD7 I/O EBI Address/Data bus bit P0.6 I/O General purpose digital I/O pin. MISO_1 I/O SPI1 MISO (Master In, Slave Out) pin. Dec. 11, 2017 Page 22 of 102 Rev 1.04

23 SERIES DATASHEET LQFP/QFN 48-pin Pin No. QFN 33-pin Pin Name Pin Type Description - AD6 I/O EBI Address/Data bus bit P0.5 I/O General purpose digital I/O pin. MOSI_1 I/O SPI1 MISO (Master Out, Slave In) pin. - AD5 I/O EBI Address/Data bus bit P0.4 I/O General purpose digital I/O pin. SPISS1 I/O SPI1 slave select pin. - AD4 I/O EBI Address/Data bus bit4. P4.1 I/O General purpose digital I/O pin PWM1 [2] I/O PWM1 output/capture input. T3EX I Timer3 external capture/reset trigger input pin. P0.3 I/O General purpose digital I/O pin AD3 I/O EBI Address/Data bus bit3. RTS0 O Request to Send output pin for UART0. RXD [2] I Data receiver input pin for UART0. P0.2 I/O General purpose digital I/O pin AD2 I/O EBI Address/Data bus bit2. CTS0 I Clear to Send input pin for UART TXD [2] O Data transmitter output pin for UART0. P0.1 I/O General purpose digital I/O pin. RTS1 O Request to Send output pin for UART1. RXD1 [2] I Data receiver input pin for UART1. ACMP3_N AI Comparator3 negative input pin. - AD1 I/O EBI Address/Data bus bit1. P0.0 I/O General purpose digital I/O pin CTS1 I Clear to Send input pin for UART1. TXD1 [2] O Data transmitter output pin for UART1. ACMP3_P AI Comparator3 positive input pin. - AD0 I/O EBI Address/Data bus bit V DD P Power supply for I/O ports and LDO source for internal PLL and digital circuit AV DD AP Power supply for internal analog circuit P1.0 I/O General purpose digital I/O pin. Dec. 11, 2017 Page 23 of 102 Rev 1.04

24 SERIES DATASHEET LQFP/QFN 48-pin Pin No. QFN 33-pin Pin Name Pin Type Description AIN0 AI ADC0 analog input. T2 I/O Timer2 external event counter input pin. - nwrl O EBI low byte write enable output pin. - P1.1 I/O General purpose digital I/O pin. 44 AIN1 AI ADC1 analog input. T3 I/O Timer3 external event counter input pin. nwrh O EBI high byte write enable output pin. P1.2 I/O General purpose digital I/O pin AIN2 AI ADC2 analog input. RXD1 [2] I Data receiver input pin for UART1. P1.3 I/O General purpose digital I/O pin AIN3 AI ADC3 analog input TXD1 [2] O Data transmitter output pin for UART1. P1.4 I/O General purpose digital I/O pin. AIN4 AI ADC4 analog input. ACMP0_N AI Comparator0 negative input pin. - SPISS0 I/O SPI0 slave select pin P4.2 I/O General purpose digital I/O pin. PWM2 [2] I/O PWM2 output/capture input. Note1: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power; ST = Schmitt trigger Note2: The PWM0 ~ PWM3, RXD, TXD, RXD1, TXD1, SCL1, SDA1 and CKO can be assigned to different pins. However, a pin function can only be assigned to a pin at the same time, i.e. software cannot assign RXD to P0.3 and P3.0 at the same time. Dec. 11, 2017 Page 24 of 102 Rev 1.04

25 SERIES DATASHEET Pin No. TSSOP 20-pin Pin Name Pin Type Description P1.2 I/O General purpose digital I/O pin. 1 AIN2 AI ADC2 analog input. RXD I Data receiver input pin for UART0. ACMP0_P AI Comparator0 positive input pin. P1.3 I/O General purpose digital I/O pin. 2 AIN3 AI ADC3 analog input. TXD O Data transmitter output pin for UART0. ACMP0_P AI Comparator0 positive input pin. P1.4 I/O General purpose digital I/O pin. 3 AIN4 AI ADC4 analog input. ACMP0_N AI Comparator0 negative input pin. P1.5 I/O General purpose digital I/O pin. 4 AIN5 AI ADC5 analog input. ACMP0_P AI Comparator0 positive input pin. AV SS AP Ground pin for analog circuit. 5 nrst I (ST) External reset input: active LOW, with an internal pull-up. Set this pin low reset chip to initial state. P3.2 I/O General purpose digital I/O pin. nint0 I External interrupt0 input pin. 6 STADC I ADC external trigger input. T0EX I Timer0 external capture/reset trigger input pin. ACMP1_P AI Comparator1 positive input pin P3.4 I/O General purpose digital I/O pin. 7 T0 I/O Timer0 external event counter input pin SDA0 i/o I2C0 data input/output pin. ACMP1_P AI Comparator1 positive input pin P3.5 I/O General purpose digital I/O pin. 8 T1 I/O Timer1 external event counter input pin. SCL0 I/O I 2 C0 clock I/O pin. ACMP1_P AI Comparator1 positive input pin 9 P5.1 I/O General purpose digital I/O pin. XTAL2 O External 4~24 MHz (high speed) crystal output pin. 10 P5.0 I/O General purpose digital I/O pin. Dec. 11, 2017 Page 25 of 102 Rev 1.04

26 SERIES DATASHEET Pin No. TSSOP 20-pin Pin Name Pin Type Description XTAL1 I (ST) External 4~24 MHz (high speed) crystal input pin. 11 V SS P Ground pin for digital circuit P2.4 I/O General purpose digital I/O pin. PWM2 I/O PWM0 output. P2.5 I/O General purpose digital I/O pin. PWM3 I/O PWM3 output. P4.6 I/O General purpose digital I/O pin. ICE_CLK I Serial Wired Debugger Clock pin. P4.7 I/O General purpose digital I/O pin. ICE_DAT I/O Serial Wired Debugger Data pin. P0.7 I/O General purpose digital I/O pin. SPICLK0 I/O SPI0 serial clock pin. P0.6 I/O General purpose digital I/O pin. MISO_0 I/O SPI0 MISO (Master In, Slave Out) pin. P0.5 I/O General purpose digital I/O pin. MOSI_0 I/O SPI0 MISO (Master Out, Slave In) pin. 19 P0.4 I/O General purpose digital I/O pin. SPISS0 I/O SPI1 slave select pin. PWM5 I/O PWM5 output. 20 V DD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. Note1: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power; ST = Schmitt trigger Dec. 11, 2017 Page 26 of 102 Rev 1.04

27 SERIES DATASHEET 5 FUNCTIONAL DESCRIPTION 5.1 ARM Cortex -M0 Core The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entere d on Reset, and can be entered as a result of an exception return. Figure 5-1 shows the functional controller of processor. Interrupts Cortex -M0 Components Cortex -M0 processor Nested Vectored Interrupt Controller (NVIC) Cortex -M0 Processor Core Debug Breakpoint and Watchpoint Unit Wakeup Interrupt Controller (WIC) Bus Matrix Debugger Interface Debug Access Port (DAP) AHB-Lite Interface Serial Wire or JTAG Debug Port Figure 5-1 Functional Controller Diagram The implemented device provides the following components and features: A low gate count processor: - ARMv6-M Thumb instruction set - Thumb-2 technology - ARMv6-M compliant 24-bit SysTick timer - A 32-bit hardware multiplier - System interface supported with little-endian data accesses - Ability to have deterministic, fixed-latency, interrupt handling - Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling - C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers - Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature NVIC: Dec. 11, 2017 Page 27 of 102 Rev 1.04

28 SERIES DATASHEET - 32 external interrupt inputs, each with four levels of priority - Dedicated Non-maskable Interrupt (NMI) input - Supports for both level-sensitive and pulse-sensitive interrupt lines - Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Debug support - Four hardware breakpoints - Two watchpoints - Program Counter Sampling Register (PCSR) for non-intrusive code profiling - Single step and vector catch capabilities Bus interfaces: - Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory - Single 32-bit slave port that supports the DAP (Debug Access Port) Dec. 11, 2017 Page 28 of 102 Rev 1.04

29 SERIES DATASHEET 5.2 System Manager Overview System management includes the following sections: System Resets System Power Architecture System Memory Map System management registers for Part Number ID, chip reset and on-chip controllers reset, multi-functional pin control System Timer (SysTick) Nested Vectored Interrupt Controller (NVIC) System Control registers System Reset The system reset can be issued by one of the following listed events. For these reset event flags can be read by RSTSRC register. Hardware Reset Power-on Reset (POR) Low level on the RESET pin (nrst) Watchdog Time-out Reset (WDT) Low Voltage Reset (LVR) Brown-out Detector Reset (BOD) Software Reset MCU Reset - SYSRESETREQ(AIRCR[2]) Cortex -M0 Core One-shot Reset - CPU_RST(IPRSTC1[1]) Chip One-shot Reset - Chip_RST(IPRSTC1[0]) Note: ISPCON.BS keeps the original value after MCUReset and CPU Reset. Dec. 11, 2017 Page 29 of 102 Rev 1.04

30 SERIES DATASHEET System Power Distribution In this chip, the power distribution is divided into three segments. Analog power from AV DD and AV SS provides the power for analog components operation. AV DD must be equal to V DD to avoid leakage current. Digital power from V DD and V SS supplies the power to the I/O pins and internal regulator which provides a fixed 1.8 V power for digital operation. Build-in a capacitor for internal voltage regulator. (FAE only) The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should be located close to the corresponding pin. Analog power (AV DD ) should be the same voltage level with the digital power (V DD ). Figure 5-2 shows the NuMicro xan power distribution and Figure 5-3 shows the NuMicro FAE power distribution. AV DD AV SS 12-bit SAR-ADC Analog Comparator Low Voltage Reset Brown Out Detector Temperature Sensor FLASH Digital Logic Internal MHz and 10 khz Oscillator LDO_CAP 1.8V 1uF PLL POR18 POR50 5V to 1.8V LDO IO cell GPIO Pins NuMicro xan Power Distribution V DD V SS Figure 5-2 NuMicro xan Power Distribution Diagram Dec. 11, 2017 Page 30 of 102 Rev 1.04

31 SERIES DATASHEET 10-bit SAR-ADC Analog Comparator Low Voltage Reset Brown Out Detector FLASH Digital Logic Internal MHz and 10 khz Oscillator 1.8V 500pF POR18 5V to 1.8V LDO IO cell GPIO Pins NuMicro FAE Power Distribution V DD V SS Figure 5-3 NuMicro FAE Power Distribution Diagram System Memory Map The NuMicro series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, addressing space, and programming detailed will be described in the following sections for each on-chip peripheral. The NuMicro series only supports little-endian data format. Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 0x0000_FFFF FLASH_BA FLASH Memory Space (64 KB) 0x2000_0000 0x2000_0FFF SRAM_BA SRAM Memory Space (4 KB) EBI Space (0x6000_0000 ~ 0x6001_FFFF) (LAN/NAN Only) 0x6000_0000 0x6001_FFFF EBI_BA External Memory Space (128 KB ) AHB Controllers Space (0x5000_0000 ~ 0x501F_FFFF) 0x5000_0000 0x5000_01FF GCR_BA System Global Control Registers Dec. 11, 2017 Page 31 of 102 Rev 1.04

32 SERIES DATASHEET 0x5000_0200 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 0x5000_7FFF GPIO_BA GPIO (P0 ~ P4) Control Registers 0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_0000 0x5001_03FF EBI_CTL_BA EBI Control Registers (LAN/NAN only) 0x5001_4000 0x5001_7FFF HDIV_BA Hardware Divider Register (xan only) APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4000_4000 0x4000_40FF WDT_BA Watchdog Timer Control Registers 0x4000_4100 0x4000_7FFF WWDT_BA Window Watchdog Timer Control Registers (xan only) 0x4001_0000 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers 0x4002_0000 0x4002_3FFF I2C0_BA I 2 C0 Interface Control Registers 0x4003_0000 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers 0x4003_4000 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 0x4004_0000 0x4004_3FFF PWMA_BA PWM0/1/2/3 Control Registers 0x4005_0000 0x4005_3FFF UART0_BA UART0 Control Registers 0x400D_0000 0x400D_3FFF ACMP01_BA Analog Comparator0/ Analog Comparator1 Control Registers 0x400E_0000 0x400E_FFFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 0x4011_0000 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4012_0000 0x4012_3FFF I2C1_BA I 2 C1 Interface Control Registers (Nuc029xAN only) 0x4014_0000 0x4014_3FFF PWMB_BA PWM4/5/6/7 Control Registers 0x4015_0000 0x4015_3FFF UART1_BA UART1 Control Registers 0x401D_0000 0x401D_3FFF ACMP23_BA Analog Comparator2/ Analog Comparator3 Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 0xE000_E0FF SYST_BA System Timer Control Registers 0xE000_E100 0xE000_ECFF NVIC_BA External Interrupt Controller Control Registers 0xE000_ED00 0xE000_ED8F SCB_BA System Control Registers Table 5-1 NuMicro xan Address Space Assignments for On-Chip Controllers Address Space Token Controllers Flash and SRAM Memory Space 0x0000_0000 0x0000_3FFF FLASH_BA FLASH Memory Space (16 KB) 0x2000_0000 0x2000_0FFF SRAM_BA SRAM Memory Space (2 KB) AHB Controllers Space (0x5000_0000 ~ 0x501F_FFFF) 0x5000_0000 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 0x5000_02FF CLK_BA Clock Control Registers Dec. 11, 2017 Page 32 of 102 Rev 1.04

33 SERIES DATASHEET 0x5000_0300 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 0x5000_7FFF GP_BA GPIO (P0 ~ P5) Control Registers 0x5000_C000 0x5000_FFFF FMC_BA Flash Memory Control Registers APB Controllers Space (0x4000_0000 ~ 0x401F_FFFF) 0x4000_4000 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4001_0000 0x4001_3FFF TMR_BA Timer0/Timer1 Control Registers 0x4002_0000 0x4002_3FFF I2C_BA I 2 C Interface Control Registers 0x4003_0000 0x4003_3FFF SPI_BA SPI with master/slave function Control Registers 0x4004_0000 0x4004_3FFF PWMA_BA PWM Control Registers 0x4005_0000 0x4005_3FFF UART_BA UART Control Registers 0x400D_0000 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 0x400E_3FFF ADC_BA Analog-Digital-Converter (ADC) Control Registers System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 0xE000_ED8F SCB_BA System Control Registers Table 5-2 NuMicro FAE Address Space Assignments for On-Chip Controllers Dec. 11, 2017 Page 33 of 102 Rev 1.04

34 SERIES DATASHEET Whole System Memory Mapping 4 GB 0xFFFF_FFFF Reserved System Control 0xE000_F000 System Control Block 0xE000_ED00 SCB_BA 0xE000_EFFF External Interrupt Controller 0xE000_E100 NVIC_BA System Control 0xE000_E000 System Timer Control 0xE000_E010 SYST_BA 0xE000_DFFF System Control Space 0xE000_E000 SCS_BA Reserved 0x6002_0000 0x6001_FFFF EBI 0x6000_0000 0x5FFF_FFFF Reserved 0x5020_0000 AHB peripherals 0x501F_FFFF Hardware Divider Control 0x5001_4000 HDIV_BA AHB 0x5000_0000 EBI Control 0x5001_0000 EBI_CTL_BA 0x4FFF_FFFF FMC 0x5000_C000 FLASH_BA Reserved GPIO Control 0x5000_4000 GPIO_BA Interrupt Multiplexer Control 0x5000_0300 INT_BA 0x4020_0000 Clock Control 0x5000_0200 CLK_BA 0x401F_FFFF System Global Control 0x5000_0000 GCR_BA APB 1 GB 0x4000_0000 Reserved 4 KB SRAM 0x3FFF_FFFF APB peripherals ACMPB Control 0x401D_0000 ACMP23_BA UART1 Control 0x4015_0000 UART1_BA 0x2000_1000 PWM4/5/6/7 Control 0x4014_0000 PWMB_BA 0x2000_0FFF I2C1 Control 0x4012_0000 I2C1_BA Timer2/Timer3 Control 0x4011_0000 TMR23_BA ADC Control 0x400E_0000 ADC_BA ACMPA Control 0x400D_0000 ACMP01_BA 0.5 GB 0x2000_0000 UART0 Control 0x4005_0000 UART0_BA Reserved 64 KB on-chip Flash (LAN/NAN) 0x1FFF_FFFF PWM0/1/2/3 Control 0x4004_0000 PWMA_BA SPI1 Control 0x4003_4000 SPI1_BA SPI0 Control 0x4003_0000 SPI0_BA 0x0001_0000 I2C Control 0x4002_0000 I2C0_BA 0x0000_FFFF Timer0/Timer1 Control 0x4001_0000 TMR01_BA 32 KB on-chip Flash 0x0000_7FFF WDT Control 0x4000_4100 WWDT_BA 0 GB (ZAN/TAN) 0x0000_0000 WWDT Control 0x4000_4000 WDT_BA Figure 5-4 NuMicro xan Whole System Memory Mapping Dec. 11, 2017 Page 34 of 102 Rev 1.04

35 SERIES DATASHEET System Control 4 GB 0xFFFF_FFFF System Control 0xE000_ED00 SCS_BA Reserved System Control Reserved Reserved Reserved AHB Reserved APB External Interrupt Control 0xE000_E100 SCS_BA 0xE000_F000 System Timer Control 0xE000_E010 SCS_BA 0xE000_EFFF 0xE000_E000 0xE000_E00F 0x6002_0000 0x6001_FFFF 0x6000_0000 0x5FFF_FFFF 0x5020_0000 AHB peripherals 0x501F_FFFF FMC 0x5000_C000 FMC_BA 0x5000_0000 GPIO Control 0x5000_4000 GP_BA 0x4FFF_FFFF Interrupt Multiplexer Control 0x5000_0300 INT_BA Clock Control 0x5000_0200 CLK_BA System Global Control 0x5000_0000 GCR_BA 0x4020_0000 0x401F_FFFF 1 GB 0x4000_0000 0x3FFF_FFFF APB peripherals ADC Control 0x400E_0000 ADC_BA Reserved ACMP Control 0x400D_0000 CMP_BA UART Control 0x4005_0000 UART_BA 0x2000_0800 PWM Control 0x4004_0000 PWM_BA 0x2000_07FF SPI Control 0x4003_0000 SPI_BA 2 KB SRAM 0.5 GB 0x2000_0000 I2C Control 0x4002_0000 I2C_BA 0x1FFF_FFFF Timer0/Timer1 Control 0x4001_0000 TMR_BA WDT Control 0x4000_4000 WDT_BA Reserved 0x0000_ KB on-chip Flash 0x0000_3FFF 0 GB (FAE) 0x0000_0000 Figure 5-5 NuMicro FAE Whole System Memory Mapping Dec. 11, 2017 Page 35 of 102 Rev 1.04

36 SERIES DATASHEET System Timer (SysTick) The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0 before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the ARM Manual and ARM v6-m Architecture Reference Manual. Cortex -M0 Technical Reference Nested Vectored Interrupt Controller (NVIC) The Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as Nested Vectored Interrupt Controller (NVIC), which is closely coupled to the processor core and provides following features: Nested and Vectored interrupt support Automatic processor state saving and restoration Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in Handler Mode. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers PC, PSR, LR, R0~R3, R12 to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports Tail Chaining which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports Late Arrival which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the ARM Manual and ARM v6-m Architecture Reference Manual. Cortex -M0 Technical Reference Dec. 11, 2017 Page 36 of 102 Rev 1.04

37 SERIES DATASHEET Exception Model and System Interrupt Map The following table lists the exception model supported by NuMicro series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of all the user-configurable interrupts is 0. Note that priority 0 is treated as the fourth priority on the system, after three system exceptions Reset, NMI and Hard Fault. Exception Name Vector Number Priority Reset 1-3 NMI 2-2 Hard Fault 3-1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 5-3 Exception Model Dec. 11, 2017 Page 37 of 102 Rev 1.04

38 SERIES DATASHEET Vector Number Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module Interrupt Description Power-Down Wake-Up 1 ~ System exceptions BOD_INT Brown-out Brown-out low voltage detected interrupt Yes 17 1 WDT_INT WDT Watchdog Timer interrupt Yes 18 2 EINT0 GPIO External signal interrupt from P3.2 pin Yes 19 3 EINT1 GPIO External signal interrupt from P3.3 pin Yes 20 4 P0/1_INT GPIO External signal interrupt from P0[7:0]/P1[7:0] Yes 21 5 P2/3/4_INT GPIO External signal interrupt from P2[7:0]/P3[7:0]/P4[7:0], except P3.2 and P3.3 Yes 22 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt No 23 7 PWMB_INT PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt No 24 8 TMR0_INT TMR0 Timer0 interrupt Yes 25 9 TMR1_INT TMR1 Timer1 interrupt Yes TMR2_INT TMR2 Timer2interrupt Yes TMR3_INT TMR3 Timer3 interrupt Yes UART0_INT UART0 UART0 interrupt Yes UART1_INT UART1 UART1 interrupt Yes SPI0_INT SPI0 SPI0 interrupt No SPI1_INT SPI1 SPI1 interrupt No 32 ~ ~ Reserved I2C0_INT I 2 C0 I 2 C0 interrupt Yes I2C1_INT I 2 C1 I 2 C1 interrupt Yes 36 ~ ~ Reserved ACMP01_INT ACMP0/1 Analog Comparator0 or Comparator1 interrupt Yes ACMP23_INT ACMP2/3 Analog Comparator2 or Comparator3 interrupt Yes Reserved PWRWU_INT CLKC Clock controller interrupt for chip wake-up from Power-down state Yes ADC_INT ADC ADC interrupt No 46 ~ ~ Reserved - Table 5-4 NuMicro xan System Interrupt Map Dec. 11, 2017 Page 38 of 102 Rev 1.04