ZNEO Z16F Series. High Performance Microcontrollers. Product Specification PS PRELIMINARY

Transcription

1 High Performance Microcontrollers ZNEO Z16F Series PS PRELIMINARY Copyright 2013 Zilog, Inc. All rights reserved.

2 ZNEO Z16F Series ZNEO ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer 2013 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, ZNEO and Z16F are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS P R E L I M I N A R Y Disclaimer

3 ZNEO Z16F Series iii Revision History Each instance in this document s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Nov 2013 Jul 2013 Aug 2011 Jun 2011 Aug 2010 Jan 2009 Revision Level Section Description 12 Signal Descriptions Corrected active status of RD, WR and CS signals. 11 Analog Functions Updated the Analog Functions Block Diagram. 10 Multi-Channel PWM Timer Per CR#13095, corrected PWMEN description in PWM Control 0 Register (PWMCTL0) table; corrected description in PWM Deadband Register (PWMDB) table and added footnote; added same footnote to PWM Minimum Pulse Width Filter (PWMMPF), PWM Fault Mask Register (PWMFM), and PWM Fault Control Register (PWMFCTL) tables. 09 Electrical Characteristics Corrected V COFF input offset value in Comparator Electrical Characteristics table Page No , , N/A Removed ISO information. ii All Updated logos. All Table 191 Changed the Minimum, Typical and Maximum values for V REF (Externally supplied Voltage Reference only) Timer 0 2 Control 0 Register Table 62: added Only Counter Mode should 109 be used with this feature to Bit 4 description. Analog Functions ADC Overview, updated fast conversion time 243 to 2.5 µs. Electrical Characteristics Updated Table Internal Precision Oscillator Removed reference to 32 khz PS P R E L I M I N A R Y Revision History

4 ZNEO Z16F Series iv Feb 2007 Jul 2006 Jan Independent and Complementary PWM Outputs Corrected PWM Registers. Updated Edge- Aligned PWM Output figure. Electrical Characteristics Replaced 105 C with 125 C in Tables through 192. Added Figures 73 through 75. I2C Master/Slave Controller Changes to Software Control of I2C Transactions 209 section. Packaging Updated Part Number Suffix Designations 359 section. Enhanced Serial Peripheral Interface Throughput section modified External Interface, General- Purpose Input/Output, DMA Controller, Option Bits, On-Chip Debugger and Electrical Characteristics Modifications done in the following chapters: External Interface, GPIO, DMA Controller, Option bits, on-chip debugger and Electrical characteristics , 66, 267, 292, 298, 337 Ordering Information Ordering Information modified All Changed zneo to ZNEO in the entire document. All All Added TM symbol to ZNEO. All Signal and Pin Descriptions, Interrupt Controller and Analog Functions Modifications done to following chapters: Pin description, Interrupt controller and Analog functions. 7, 80, 242 Ordering Information Ordering Information modified. 356 PS P R E L I M I N A R Y Revision History

5 v Table of Contents Revision History iii List of Figures xvi List of Tables xix Document Objectives xxv About This Manual xxv Intended Audience xxv Manual Conventions xxv Safeguards xxvii Introduction Features Block Diagram ZNEO CPU Features External Interface Flash Controller Random Access Memory ZNEO Peripheral Overview Bit Analog-to-Digital Converter with Programmable Gain Amplifier Analog Comparator Operational Amplifier General-Purpose Input/Output Universal Asynchronous Receiver/Transmitter Infrared Encoder/Decoders Inter-Integrated Circuit Master/Slave Controller Enhanced Serial Peripheral Interface DMA Controller Pulse Width Modulator Standard Timers Interrupt Controller Crystal Oscillator Reset Controller On-Chip Debugger Signal and Pin Descriptions Available Packages Pin Configurations Signal Descriptions Pin Characteristics PS P R E L I M I N A R Y Table of Contents

6 vi Address Space Memory Map Internal Nonvolatile Memory Internal RAM Input/Output Memory Input/Output Memory Precautions CPU Control Registers External Memory Endianness Bus Widths Peripheral Address Map External Interface External Interface Signals Chip Selects Tools Compatibility Guidelines External WAIT Pin Operation Operation Wait State Generator ISA-Compatible Mode External Interface Control Register Definitions External Interface Control Register Chip Select Control Registers External Interface Timing External Interface Write Timing, Normal Mode External Interface Write Timing, ISA Mode External Interface Read Timing, Normal Mode External Interface Read Timing, ISA Mode Reset and Stop Mode Recovery Reset Types System Reset Power-On Reset Voltage Brown-Out Reset Watchdog Timer Reset External Pin Reset External Reset Indicator User Reset Fault Detect Logic Reset Stop Mode Recovery Stop Mode Recovery Using WDT Time-Out Stop Mode Recovery Using a GPIO Port Pin Transition PS P R E L I M I N A R Y Table of Contents

7 vii Reset Status and Control Register Low-Power Modes Stop Mode Halt Mode Peripheral-Level Power Control Power Control Option Bits General-Purpose Input/Output GPIO Port Availability by Device Architecture GPIO Alternate Functions GPIO Interrupts GPIO Control Register Definitions Port A-K Input Data Registers Port A-K Output Data Registers Port A-K Data Direction Registers Port A-K High Drive Enable Registers Port A-K Alternate Function High and Low Registers Port A-K Output Control Registers Port A-K Pull-Up Enable Registers Port A-K Stop Mode Recovery Source Enable Registers Port A IRQ MUX1 Register Port A IRQ MUX Register Port A IRQ Edge Register Port C IRQ MUX Register Interrupt Controller Interrupt Vector Listing Architecture Operation Master Interrupt Enable Interrupt Vectors and Priority System Exceptions Interrupt Assertion System Exception Status Registers Last IRQ Register Interrupt Request 0 Register Interrupt Request 1 Register Interrupt Request 2 Register IRQ0 Enable High and Low Bit Registers IRQ1 Enable High and Low Bit Registers IRQ2 Enable High and Low Bit Registers PS P R E L I M I N A R Y Table of Contents

8 viii Timers Architecture Operation Timer Operating Modes Reading Timer Count Values Timer Control Register Definitions Timer 0 2 High and Low Byte Registers Timer X Reload High and Low Byte Registers Timer 0 2 PWM High and Low Byte Registers Timer 0 2 Control Registers Multi-Channel PWM Timer Architecture Operation PWM Option Bits PWM Reload Event PWM Prescaler PWM Period and Count Resolution PWM Duty Cycle Registers Independent and Complementary PWM Outputs Manual Off-State Control of PWM Output Channels Deadband Insertion Minimum PWM Pulse Width Filter Synchronization of PWM and ADC Synchronized Current-Sense Sample and Hold PWM Timer and Fault Interrupts Fault Detection and Protection PWM Operation in CPU Halt Mode PWM Operation in CPU Stop Mode Observing the State of PWM Output Channels PWM Control Register Definitions PWM High and Low Byte Registers PWM Reload High and Low Byte Registers PWM 0 2 Duty Cycle High and Low Byte Registers PWM Control 0 Register PWM Control 1 Register PWM Deadband Register PWM Minimum Pulse Width Filter PWM Fault Mask Register PWM Fault Status Register PWM Fault Control Register PWM Input Sample Register PS P R E L I M I N A R Y Table of Contents

9 ix PWM Output Control Register Current-Sense Sample and Hold Control Registers LIN-UART Architecture Operation Data Format for Standard UART Modes Transmitting Data using the Polled Method Transmitting Data Using Interrupt-Driven Method Receiving Data Using the Polled Method Receiving Data Using the Interrupt-Driven Method Clear To Send Operation External Driver Enable LIN-UART Special Modes Multiprocessor (9-Bit) Mode LIN Protocol Mode LIN-UART Interrupts LIN-UART DMA Interface LIN-UART Baud Rate Generator Noise Filter Architecture Operation LIN-UART Control Register Definitions LIN-UART Transmit Data Register LIN-UART Receive Data Register LIN-UART Status 0 Register LIN-UART Mode Select and Status Register LIN-UART Control 0 Register LIN-UART Control 1 Registers LIN-UART Address Compare Register LIN-UART Baud Rate High and Low Byte Registers Infrared Encoder/Decoder Architecture Operation Transmitting IrDA Data Receiving IrDA Data Infrared Encoder/Decoder Control Register Definitions Enhanced Serial Peripheral Interface Architecture ESPI Signals Master-In/Slave-Out PS P R E L I M I N A R Y Table of Contents

10 x Master-Out/Slave-In Serial Clock Slave Select ESPI Register Overview Comparison with Basic SPI Block Operation Throughput ESPI Clock Phase and Polarity Control Modes of Operation SPI Protocol Configuration Error Detection ESPI Interrupts DMA Interface ESPI Baud Rate Generator ESPI Control Register Definitions ESPI Data Register ESPI Transmit Data Command Register ESPI Control Register ESPI Mode Register ESPI Status Register ESPI State Register ESPI Baud Rate High and Low Byte Registers I 2 C Master/Slave Controller Architecture I 2 C Master/Slave Controller Registers Comparison with Master Mode only I 2 C Controller Operation SDA and SCL Signals I 2 C Interrupts Start and Stop Conditions Software Control of I 2 C Transactions Master Transactions Slave Transactions DMA Control of I 2 C Transactions I 2 C Control Register Definitions I 2 C Data Register I 2 C Interrupt Status Register I 2 C Control Register I 2 C Baud Rate High and Low Byte Registers I 2 C State Register I 2 C Mode Register PS P R E L I M I N A R Y Table of Contents

11 xi I 2 C Slave Address Register Watchdog Timer Operation Watchdog Timer Refresh Watchdog Timer Time-Out Response Watchdog Timer Reload Unlock Sequence Watchdog Timer Register Definitions Watchdog Timer Reload High and Low Byte Registers Analog Functions ADC Overview Architecture Operation ADC Timing ADC Interrupts ADC0 Timer 0 Capture ADC Convert on Read Reference Buffer, RBUF Internal Voltage Reference Generator ADC Control Register Definitions ADC0 Control Register ADC0 Data High Byte Register ADC0 Data Low Bits Register Sample Settling Time Register Sample Time Register ADC Clock Prescale Register ADC0 Max Register ADC Timer 0 Capture Register Comparator and Operational Amplifier Overview Comparator Operation Operational Amplifier Operation Interrupts Comparator Control Register Definitions Comparator and Operational Amplifier Control Register Flash Memory Information Area Operation Timing Using the Flash Frequency Register Flash Read Protection Flash Write/Erase Protection Programming PS P R E L I M I N A R Y Table of Contents

12 xii Page Erase Mass Erase Flash Controller Bypass Flash Controller Behavior using the On-Chip Debugger Flash Control Register Definitions Flash Command Register Flash Status Register Flash Control Register Flash Sector Protect Register Flash Page Select Register Flash Frequency Register DMA Controller DMA Features DMA Block Diagram DMA Description DMA Register Description DMA Control Bit Definitions DMA Watermark DMA Peripheral Interface signals Buffer Closure DMA Modes Linked List Mode DMA Priority DMA Interrupts DMA Request Select Register DMA Control Registers DMA Control Register DMA X Transfer Length Register DMA Destination Address DMA Source Address Registers DMA List Address Register External DMA Signals DMA Timing Option Bits Operation Option Bit Address Space Program Memory Address 0001h Program Memory Address 0002h Program Memory Address 0003h Information Area PS P R E L I M I N A R Y Table of Contents

13 xiii IPO Trim Registers (Information Area Address 0021h and 0022h) ADC Reference Voltage Trim (Information Area Address 0023h) On-Chip Debugger Architecture Operation On-Chip Debug Enable Serial Interface Serial Data Format Baud Rate Generator Auto-Baud Detector Line Control Bit Mode Start Bit Flow Control Initialization Initialization during Reset Debug Lock Error Reset DEBUG Halt Mode Reading and Writing Memory Reading Memory CRC Breakpoints Instruction Trace On-Chip Debugger Commands Cyclic Redundancy Check Memory Cyclic Redundancy Check UART Mode Serial Errors Interrupts DBG Pin as a GPIO Pin Control Register Definitions Receive Data Register Transmit Data Register Baud Rate Reload Register Line Control Register Status Register Control Register OCD Control Register OCD Status Register Hardware Breakpoint Registers Trace Control Register Trace Address Register PS P R E L I M I N A R Y Table of Contents

14 xiv On-Chip Oscillator Operating Modes Crystal Oscillator Operation Oscillator Operation with an External RC Network Oscillator Control Operation System Clock Selection Clock Selection Following System Reset Clock Failure Detection and Recovery Oscillator Control Register Definitions Oscillator Control Register Oscillator Divide Register Internal Precision Oscillator Operation Electrical Characteristics Absolute Maximum Ratings DC Characteristics On-Chip Peripheral AC and DC Electrical Characteristics AC Characteristics General Purpose I/O Port Input Data Sample Timing On-Chip Debugger Timing SPI Master Mode Timing SPI Slave Mode Timing I 2 C Timing UART Timing Packaging Ordering Information Part Number Suffix Designations Precharacterization Product Index Customer Support PS P R E L I M I N A R Y Table of Contents

15 xvi List of Figures Figure 1. Motor Control MCUs Z16F Series Block Diagram Figure 2. Z16F2810 MCU, 64-Pin Low-Profile Quad Flat Package (LQFP) Figure 3. Z16F2810 MCU, 68-Pin Plastic Leaded Chip Carrier (PLCC) Figure 4. ZNEO Z16F Series, 80-Pin Quad Flat Package (QFP) Figure 5. ZNEO Z16F Series, 100-Pin Low-Profile Quad Flat Package (LQFP) Figure 6. Physical Memory Map Figure 7. Endianness of Words and Quads Figure 8. Alignment of Word and Quad Operations on 16-bit Memories Figure 9. Chip Select Boundary Addressing with 128 KB Internal Flash Figure 10. External Interface Wait State Operation Example (Write Operation) Figure 11. External Interface Timing for a Write Operation, Normal Mode Figure 12. External Interface Timing for a Write Operation, ISA Mode Figure 13. External Interface Timing for a Read Operation, Normal Mode Figure 14. External Interface Timing for a Read Operation, 2 Wait States and 1 Post Read Wait State Figure 15. External Interface Timing for a Read Operation, ISA Mode Figure 16. Power-On Reset Operation Figure 17. Voltage Brown-Out Reset Operation Figure 18. GPIO Port Pin Block Diagram Figure 19. Interrupt Controller Block Diagram Figure 20. Timer Block Diagram Figure 21. PWM Block Diagram Figure 22. Edge-Aligned PWM Output Figure 23. Center-Aligned PWM Output Figure 24. LIN-UART Block Diagram Figure 25. LIN-UART Asynchronous Data Format without Parity Figure 26. LIN-UART Asynchronous Data Format with Parity Figure 27. LIN-UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) Figure 28. LIN-UART Asynchronous Multiprocessor Mode Data Format Figure 29. LIN-UART Receiver Interrupt Service Routine Flow Figure 30. Noise Filter System Block Diagram Figure 31. Noise Filter Operation PS P R E L I M I N A R Y List of Figures

16 xvii Figure 32. Infrared Data Communication System Block Diagram Figure 33. Infrared Data Transmission Figure 34. Infrared Data Reception Figure 35. ESPI Block Diagram Figure 36. ESPI Timing when PHASE = Figure 37. ESPI Timing when PHASE = Figure 38. SPI Mode (SSMD = 000) Figure 39. I2S Mode (SSMD = 010) Figure 40. ESPI Configured as an SPI Master in a Single Master, Single Slave System Figure 41. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System Figure 42. ESPI Configured as an SPI Slave Figure 43. I2C Controller Block Diagram Figure 44. Data Transfer Format, Master Write Transaction with 7-Bit Addressing. 211 Figure 45. Data Transfer Format, Master Write Transaction with 10-Bit Addressing 212 Figure 46. Data Transfer Format, Master Read Transaction with 7-Bit Addressing. 214 Figure 47. Data Transfer Format, Master Read Transaction with 10-Bit Addressing 215 Figure 48. Data Transfer Format, Slave Receive Transaction with 7-Bit Addressing 218 Figure 49. Data Transfer Format, Slave Receive Transaction with 10-Bit Addressing Figure 50. Data Transfer Format, Slave Transmit Transaction with 7-Bit Addressing 221 Figure 51. Data Transfer Format, Slave Transmit Transaction with 10-Bit Addressing Figure 52. Analog Functions Block Diagram Figure 53. ADC Timing Diagram Figure 54. ADC Convert Timing Figure 55. Flash Memory Arrangement Figure 56. DMA Block Diagram Figure 57. DMA Channel Registers Figure 58. Direct DMA Diagram Figure 59. Linked List Diagram Figure 60. External DMA Transfer Figure 61. External ISA DMA transfer Figure 62. On-Chip Debugger Block Diagram Figure 63. Interfacing a Serial Pin with an RS-232 Interface, #1 of Figure 64. Interfacing a Serial Pin with an RS-232 Interface, #2 of PS P R E L I M I N A R Y List of Figures

17 xviii Figure 65. OCD Serial Data Format Figure 66. Output Driver when Drive High and Open Drain Enabled Figure Bit Mode Figure 68. Start Bit Flow Control Figure 69. Initialization During Reset Figure 70. Recommended 20 MHz Crystal Oscillator Configuration Figure 71. Connecting the On-Chip Oscillator to an External RC Network Figure 72. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 15 kω Resistor Figure 73. Typical I DD Versus System Clock Frequency Figure 74. Typical Halt Mode IDD Versus System Clock Frequency Figure 75. Stop Mode Current Versus V DD Figure 76. Port Input Sample Timing Figure 77. SPI Master Mode Timing Figure 78. SPI Slave Mode Timing Figure 79. I 2 C Timing Figure 80. UART Timing with CTS Figure 81. UART Timing without CTS PS P R E L I M I N A R Y List of Figures

18 xix List of Tables Table 1. ZNEO Z16F Series Package Options Table 2. Signal Descriptions Table 3. Pin Characteristics of the ZNEO CPU Table 4. Reserved Memory Map Example Table 5. ZNEO CPU Control Registers Table 6. Register File Address Map Table 7. External Interface Signals Description Table 8. Example Usage of Chip Selects Table 9. External Interface Control Register (EXTCT) Table 10. External Chip Select Control Registers High (EXTCSxH) Table 11. External Chip Select Control Registers Low for CS0 (EXTCS0L) Table 12. External Chip Select Control Registers Low for CS1 (EXTCS1L) Table 13. External Chip Select Control Registers Low for CS2 to CS5 (EXTCSxL). 46 Table 14. External Interface Timing for a Write Operation, Normal Mode Table 15. External Interface Timing for a Write Operation, ISA Mode Table 16. External Interface Timing for a Read Operation, Normal Mode Table 17. External Interface Timing for a Read Operation, ISA Mode Table 18. Reset and Stop Mode Recovery Characteristics and Latency Table 19. System Reset Sources and Resulting Reset Action Table 20. Stop Mode Recovery Sources and Resulting Action Table 21. Reset Status and Control Register (RSTSCR) Table 22. Reset Status Register Values Following Reset Table 23. GPIO Port Availability by Device Table 24. Port Alternate Function Mapping Table 25. Port A-K Input Data Registers (PxIN) Table 26. Port A-K Output Data Registers (PxOUT) Table 27. Port A-K Data Direction Registers (PxDD) Table 28. Port A-K High Drive Enable Registers (PxHDE) Table 29. Port A-K Alternate Function Low Registers (PxAFL) Table 30. Alternate Function Enabling Table 31. Port A-K Alternate Function High Registers (PxAFH) Table 32. Port A-K Output Control Registers (PxOC) Table 33. Port A-K Pull-Up Enable Registers (PxPUE) PS P R E L I M I N A R Y List of Tables

19 xx Table 34. Port A-K Stop Mode Recovery Source Enable Registers (PxSMRE) Table 35. Port A IRQ MUX1 Register (PAIMUX1) Table 36. Port A IRQ MUX Register (PAIMUX) Table 37. Port A IRQ Edge Register (PAIEDGE) Table 38. Port C IRQ MUX Register (PCIMUX) Table 39. Interrupt Vectors in Order of Priority Table 40. Interrupt Vector Placement Table 41. System Exception Register High (SYSEXCPH) Table 42. System Exception Register Low (SYSEXCPL) Table 43. Last IRQ Register (LASTIRQ) Table 44. Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register (IRQ0SET) Table 45. Interrupt Request1 Register (IRQ1) and Interrupt Request1 Set Register (IRQ1SET) Table 46. Interrupt Request 2 Register (IRQ2) and Interrupt Request 2 Set Register (IRQ2SET) Table 47. IRQ0 Enable and Priority Encoding Table 48. IRQ0 Enable High Bit Register (IRQ0ENH) Table 49. IRQ0 Enable Low Bit Register (IRQ0ENL) Table 50. IRQ1 Enable and Priority Encoding Table 51. IRQ1 Enable High Bit Register (IRQ1ENH) Table 52. IRQ1 Enable Low Bit Register (IRQ1ENL) Table 53. IRQ2 Enable and Priority Encoding Table 54. IRQ2 Enable Low Bit Register (IRQ2ENL) Table 55. IRQ2 Enable High Bit Register (IRQ2ENH) Table 56. Timer 0 2 High Byte Register (TxH) Table 57. Timer 0 2 Low Byte Register (TXL) Table 58. Timer 0 2 Reload High Byte Register (TxRH) Table 59. Timer 0 2 Reload Low Byte Register (TxRL) Table 60. Timer 0 2 PWM High Byte Register (TxPWMH) Table 61. Timer 0 2 PWM Low Byte Register (TxPWML) Table 62. Timer 0 2 Control 0 Register (TxCTL0) Table 63. Timer 0 2 Control 1 Register (TxCTL1) Table 64. PWM High Byte Register (PWMH) Table 65. PWM Low Byte Register (PWML) Table 66. PWM Reload High Byte Register (PWMRH) PS P R E L I M I N A R Y List of Tables

20 xxi Table 67. PWM Reload Low Byte Register (PWMRL) Table 68. PWM 0 2 H/L Duty Cycle High Byte Register (PWMHxDH, PWMLxDH) Table 69. PWM Control 0 Register (PWMCTL0) Table 70. PWM 0 2 H/L Duty Cycle Low Byte Register (PWMHxDL, PWMLxDL) Table 71. PWM Control 1 Register (PWMCTL1) Table 72. PWM Deadband Register (PWMDB) Table 73. PWM Minimum Pulse Width Filter (PWMMPF) Table 74. PWM Fault Mask Register (PWMFM) Table 75. PWM Fault Status Register (PWMFSTAT) Table 76. PWM Fault Control Register (PWMFCTL) Table 77. PWM Input Sample Register (PWMIN) Table 78. PWM Output Control Register (PWMOUT) Table 79. Current-Sense Sample and Hold Control Register (CSSHR0 and CSSHR1) Table 80. LIN-UART Transmit Data Register (UxTXD) Table 81. LIN-UART Receive Data Register (UxRXD) Table 82. LIN-UART Status 0 Register, Standard UART Mode (UxSTAT0) Table 83. LIN-UART Status 0 Register, LIN Mode (UxSTAT0) Table 84. LIN-UART Mode Select and Status Register (UxMDSTAT) Table 85. Multiprocessor Mode Status Field (MSEL = 000b) Table 86. Digital Noise Filter Mode Status Field (MSEL = 001b) Table 87. LIN Mode Status Field (MSEL = 010b) Table 88. Hardware Revision Mode Status Field (MSEL = 111b) Table 89. LIN-UART Control 0 Register (UxCTL0) Table 90. MultiProcessor Control Register (UxCTL1 with MSEL = 000b) Table 91. Noise Filter Control Register (UxCTL1 with MSEL = 001b) Table 92. LIN Control Register (UxCTL1 with MSEL = 010b) Table 93. LIN-UART Address Compare Register (UxADDR) Table 94. LIN-UART Baud Rate High Byte Register (UxBRH) Table 95. LIN-UART Baud Rate Low Byte Register (UxBRL) Table 96. LIN-UART Baud Rates Table 97. ESPI Registers Table 98. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation Table 99. ESPI Tx DMA Descriptor Command Field PS P R E L I M I N A R Y List of Tables

21 xxii Table 100. ESPI Tx DMA Descriptor Status Field Table 101. ESPI Rx DMA Descriptor Status Field Table 102. ESPI Data Register (ESPIDATA) Table 103. ESPI Transmit Data Command Register (ESPITDCR) Table 104. ESPI Control Register (ESPICTL) Table 105. ESPI Mode Register (ESPIMODE) Table 106. ESPI Status Register (ESPISTAT) Table 107. ESPI State Register (ESPISTATE) Table 108. ESPISTATE Values and Description Table 109. ESPI Baud Rate High Byte Register (ESPIBRH) Table 110. ESPI Baud Rate Low Byte Register (ESPIBRL) Table 111. I 2 C Master/Slave Controller Registers Table 112. I 2 C Data Register (I2CDATA) Table 113. I 2 C Interrupt Status Register (I2CISTAT) Table 114. I 2 C Control Register (I2CCTL) Table 115. I 2 C Baud Rate High Byte Register (I2CBRH) Table 116. I 2 C Baud Rate Low Byte Register (I2CBRL) Table 117. I 2 C State Register (I2CSTATE), Description when DIAG = Table 118. I 2 C State Register (I2CSTATE), Description when DIAG = Table 119. I2CSTATE_H Table 120. I2CSTATE_L Table 121. I 2 C Mode Register (I2CMODE) Table 122. I 2 C Slave Address Register (I2CSLVAD) Table 123. Watchdog Timer Approximate Time-Out Delays Table 124. Watchdog Timer Reload High Byte Register (WDTH) Table 125. Watchdog Timer Reload Low Byte Register (WDTL) Table 126. ADC0 Control Register 0 (ADC0CTL) Table 127. ADC0 Data High Byte Register (ADC0D_H) Table 128. ADC0 Data Low Bits Register (ADC0D_L) Table 129. Sample and Settling Time (ADCSST) Table 130. Sample Time (ADCST) Table 131. ADC Clock Prescale Register (ADCCP) Table 132. ADC0 MAX Register (ADC0MAX) Table 133. ADC Timer 0 Capture Register, High Byte (ADCTCAP_H) Table 134. ADC Timer 0 Capture Register, Low Byte (ADCTCAP_L) Table 135. Comparator and Op Amp Control Register (CMPOPC) PS P R E L I M I N A R Y List of Tables