Datasheet RL78/I1D 1. OUTLINE. 1.1 Features RENESAS MCU. R01DS0244EJ0220 Rev Page 1 of 99. Feb 20, R01DS0244EJ0220 Rev

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1 Datasheet RL78/I1D RENESAS MCU R01DS0244EJ0220 Rev OUTLINE 1.1 Features Ultra-low power consumption technology VDD = 1.6 V to 3.6 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed ( MHz operation with high-speed on-chip oscillator) to ultra-low speed ( khz operation with low-speed on-chip oscillator clock) Multiply/divide/multiply & accumulate instructions are supported. Address space: 1 MB General-purpose registers: (8-bit register 8) 4 banks On-chip RAM: 0.7 to 3 KB Code flash memory Code flash memory: 8 to 32 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Self-programming (with boot swap function/flash shield window function) Data flash memory Data flash memory: 2 KB Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. Number of rewrites: 1,000,000 times (TYP.) Voltage of rewrites: VDD = 1.8 to 3.6 V High-speed on-chip oscillator Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85 C) Middle-speed on-chip oscillator Selectable from 4 MHz, 2 MHz, and 1 MHz. Operating ambient temperature TA = -40 to +105 C (G: Industrial applications) Power management and reset function On-chip power-on-reset (POR) circuit On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels) Data transfer controller (DTC) Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode Activation sources: Activated by interrupt sources. Chain transfer function Event link controller (ELC) Event signals of 20 types can be linked to the specified peripheral function. Serial interfaces CSI: 2 channels UART: 1 channel I 2 C/simplified I 2 C: 2 channels Timers 16-bit timer: 4 channels 12-bit interval timer: 1 channel 8-bit interval timer: 4 channels Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function) Watchdog timer: 1 channel A/D converter 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V) Analog input: 6 to 17 channels Internal reference voltage (1.45 V) and temperature sensor Comparator 2 channels Operating modes: Comparator high-speed mode, comparator low-speed mode, window mode Operational amplifier 4 channels I/O ports I/O port: 14 to 42 (N-ch open drain I/O [withstand voltage of 6 V]: 4, N-ch open drain I/O [VDD withstand voltage]: 3 to 7) Can be set to N-ch open drain, TTL input buffer, and onchip pull-up resistor Different potential interface: Can connect to a 1.8/2.5 V device On-chip key interrupt function On-chip clock output/buzzer output controller Others On-chip BCD (binary-coded decimal) correction circuit On-chip data operation circuit Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01DS0244EJ0220 Rev Page 1 of 99

2 1. OUTLINE ROM, RAM capacities Flash ROM Data flash RAM RL78/I1D 20 pins 24 pins 30 pins 32 pins 48 pins 32 KB 2 KB 3 KB Note R5F117AC R5F117BC R5F117GC 16 KB 2 KB 2 KB R5F1176A R5F1177A R5F117AA R5F117BA R5F117GA 8 KB 2 KB 0.7 KB R5F11768 R5F11778 R5F117A8 Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F117xC (x = A, B, G): Start address FF300H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0244EJ0220 Rev Page 2 of 99

3 1. OUTLINE 1.2 Ordering Information Figure 1-1 Part Number, Memory Size, and Package of RL78/I1D Part No. R 5 F G C G x x x F B#U 0 Packaging specification #20: Tray (HVQFN) #30: Tray (LFQFP, LQFP, LSSOP) #U0: Tray (HWQFN) #40: Embossed Tape (HVQFN) #50: Embossed Tape (LFQFP, LQFP, LSSOP) #W0: Embossed Tape (HWQFN) Package type: SP: LSSOP, 0.65 mm pitch FP: LQFP, 0.80 mm pitch FB: LFQFP, 0.50 mm pitch NA: HWQFN, 0.50 mm pitch Note 1 NA: HVQFN, 0.50 mm pitch Note 2 ROM number (Omitted for blank products) Fields of application: G: Industrial applications, TA = -40 to +105 C ROM capacity: 8: 8 KB A: 16 KB C: 32 KB Pin count: 6: 20-pin 7: 24-pin A: 30-pin B: 32-pin G: 48-pin RL78/I1D Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Note 1. Note pin products 32-pin products R01DS0244EJ0220 Rev Page 3 of 99

4 1. OUTLINE Pin count Package Ordering Part Number 20 pins 20-pin plastic LSSOP ( mm, 0.65 mm pitch) 24 pins 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch) 30 pins 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) 32 pins 32-pin plastic HVQFN (5 5 mm, 0.5 mm pitch) 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch) 48 pins 48-pin plastic LFQFP (7 7 mm, 0.5 mm pitch) R5F11768GSP#30, R5F1176AGSP#30, R5F11768GSP#50, R5F1176AGSP#50 R5F11778GNA#U0, R5F1177AGNA#U0, R5F11778GNA#W0, R5F1177AGNA#W0 R5F117A8GSP#30, R5F117AAGSP#30, R5F117ACGSP#30, R5F117A8GSP#50, R5F117AAGSP#50, R5F117ACGSP#50 R5F117BAGNA#20, R5F117BCGNA#20, R5F117BAGNA#40, R5F117BCGNA#40 R5F117BAGFP#30, R5F117BCGFP#30, R5F117BAGFP#50, R5F117BCGFP#50 R5F117GAGFB#30, R5F117GCGFB#30, R5F117GAGFB#50, R5F117GCGFB#50 Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0244EJ0220 Rev Page 4 of 99

5 1. OUTLINE 1.3 Pin Configuration (Top View) pin products <R> 20-pin plastic LSSOP ( mm, 0.65 mm pitch) P12/ANI2/AMP0+ P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD RL78/I1D (Top View) P13/ANI3/AMP0- P14/ANI4/IVCMP0/AMP0O AVSS AVDD P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P31/TI01/TO00/PCLBUZ0/IVREF1 P30/SCK00/SCL00/TI00/TO01/IVREF0 P54/SO00/TxD0/INTP1/TOOLTXD Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark For pin identification, see 1.4 Pin Identification. R01DS0244EJ0220 Rev Page 5 of 99

6 1. OUTLINE pin products <R> 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch) AVDD P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 AVSS P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET INDEX MARK RL78/I1D (Top View) exposed die pad P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. It is recommended to connect an exposed die pad to VSS. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). R01DS0244EJ0220 Rev Page 6 of 99

7 1. OUTLINE pin products <R> 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P56/SCK00/SCL00/INTP3 P55/SI00/RxD0/SDA00/INTP2/TOOLRXD RL78/I1D (Top View) P15/ANI5/AMP1+ P16/ANI6/AMP1- P17/ANI7/AMP1O AVSS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P33/TI02/TO02/INTP5 P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P54/SO00/TxD0/INTP1/TOOLTXD Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). R01DS0244EJ0220 Rev Page 7 of 99

8 1. OUTLINE pin products <R> 32-pin plastic HVQFN (5 5 mm, 0.5 mm pitch) exposed die pad P17/ANI7/AMP1O P16/ANI6/AMP1- P15/ANI5/AMP1+ P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD AVSS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O RL78/I1D (Top View) INDEX MARK Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). Remark 3. It is recommended to connect an exposed die pad to VSS. R01DS0244EJ0220 Rev Page 8 of 99

9 1. OUTLINE <R> 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch) P17/ANI7/AMP1O P16/ANI6/AMP1- P15/ANI5/AMP1+ P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD AVSS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O RL78/I1D (Top View) Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). R01DS0244EJ0220 Rev Page 9 of 99

10 1. OUTLINE pin products <R> 48-pin plastic LFQFP (7 7 mm, 0.5 mm pitch) P16/ANI6/AMP1- P15/ANI5/AMP1+ P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P11/ANI1/AVREFM P10/ANI0/AVREFP P130 P40/TOOL0 P04/ANI18 P03/ANI17 P02/ANI16 P01/PCLBUZ1 P17/ANI7/AMP1O AVSS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P33/(TI02/TO02)/INTP RL78/I1D (Top View) P00 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS P32/KR3/(TI01/TO00)/INTP6 P31/TI01/TO00/PCLBUZ0/IVREF1 VDD P P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P50/(TI00/TO01)/RTC1HZ P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P57/(TI03/TO03)/INTP4/VCOUT1 P63/SSI00 P62 P61 Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 μf). Caution 2. Make AVSS pin the same potential as VSS pin. Caution 3. Make AVDD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). R01DS0244EJ0220 Rev Page 10 of 99

11 1. OUTLINE 1.4 Pin Identification ANI0 to ANI13, : Analog input PCLBUZ0, PCLBUZ1 : Programmable clock output/buzzer ANI16 to ANI18 output AVDD : Analog power supply REGC : Regulator capacitance AVREFM : A/D converter reference RESET : Reset potential (- side) input RTC1HZ : Real-time clock correction clock (1 Hz) AVREFP : A/D converter reference output potential (+ side) input RxD0 : Receive data AVSS : Analog ground SCK00, SCK01 : Serial clock input/output EXCLK : External clock input SCL00, SCL01 : Serial clock input/output (main system clock) SDA00, SDA01 : Serial data input/output EXCLKS : External clock input SI00, SI01 : Serial data input (subsystem clock) SO00, SO01 : Serial data output INTP0 to INTP6 : External interrupt input SSI00 : Serial interface chip select input IVCMP0, IVCMP1 : Comparator input TI00 to TI03 : Timer input IVREF0, IVREF1 : Comparator reference input TO00 to TO03 : Timer output KR0 to KR3 : Key return TOOL0 : Data input/output for tool P00 to P04 : Port 0 TOOLRXD, TOOLTXD : Data input/output for external device P10 to P17 : Port 1 TxD0 : Transmit data P20 to P25 : Port 2 VCOUT0, VCOUT1 : Comparator output P30 to P33 : Port 3 AMP0+, AMP1+, : Operational amplifier (+side) input P40 : Port 4 AMP2+, AMP3+ P50 to P57 : Port 5 AMP0-, AMP1-, : Operational amplifier (-side) input P60 to P63 : Port 6 AMP2-, AMP3- P121 to P124 : Port 12 AMP0O, AMP1O, : Operational amplifier output P130, P137 : Port 13 AMP2O, AMP3O VDD VSS : Power supply : Ground X1, X2 : Crystal oscillator (main system clock) XT1, XT2 : Crystal oscillator (subsystem clock) R01DS0244EJ0220 Rev Page 11 of 99

12 1. OUTLINE 1.5 Block Diagram pin products TI00 TO00 TIMER ARRAY UNIT 0 (4ch) ch00 EVENT LINK CONTROLLER (ELC) Port 0 5 Port 1 8 P00 to P04 P10 to P17 TI01 TO01 ch01 Port 2 6 P20 to P25 TI02 TO02 ch02 Port 3 4 P30 to P33 TI03 TO03 ch03 Port 4 P40 8-BIT INTERVAL TIMER 0 Port 5 8 P50 to P57 ch00 Port 6 4 P60 to P63 ch01 8-BIT INTERVAL TIMER 1 CODE FLASH: 32 KB DATA FLASH: 2 KB BCD CORRECTION CIRCUIT DATA OPERATION CIRCUIT (DOC) Port 12 Port 13 4 P121 to P124 P130 P137 ch10 ch11 INT ON-CHIP DEBUG TOOL0/P40 RL78 CPU CORE DATA TRANSFER CONTROLLER (DTC) MULDIV RAM 3 KB CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 PCLBUZ1 KEY INTERRUPT 4ch 4 KR0 to KR3 RxD0 TxD0 SCK00 SI00 SO00 SSI00 SCK01 SI01 SO01 SCL00 SDA00 SCL01 SDA01 SERIAL ARRAY UNIT0 (2ch) UART0 CSI00 CSI01 IIC00 IIC01 POR/ LVD CLOCK GENERATOR + RESET CIRCUIT HIGH-SPEED ON-CHIP OSCILLATOR 24 MHz MIDDLE-SPEED ON-CHIP OSCILLATOR 4 MHz LOW-SPEED ON-CHIP OSCILLATOR 15 khz RESET MAIN SYSTEM CLOCK GENERATOR 1to 20 MHz X1 SUBSYSTEM CLOCK GENERATOR khz XT1 REGULATOR X2/EXCLK XT2/EXCLK EXTERNAL INTERRUPT 7ch REAL TIME CLOCK 2 12-BIT INTERVAL TIMER A/D CONVERTER (16ch) COMPARATOR (2ch) COMPARATOR 0 COMPARATOR INTP0 to INTP6 RTC1HZ ANI2 to ANI13, ANI16 to ANI18 ANI0/AVREFP ANI1/AVREFM VCOUT0 IVCMP0 IVREF0 VCOUT1 IVCMP1 IVREF1 REGC OPERATIONAL AMPLIFIER (4ch) VDD VSS TOOLRXD/P55, TOOLTXD/P54 WATCHDOG TIMER (WDT) OPERATIONAL AMPLIFIER 0 OPERATIONAL AMPLIFIER 1 AMP0+ AMP0- AMP0O AMP1+ AMP1- AMP1O CRC OPERATIONAL AMPLIFIER 2 AMP2+ AMP2- AMP2O FREQUENCY MEASUREMENT CIRCUIT OPERATIONAL AMPLIFIER 3 AMP3+ AMP3- AMP3O R01DS0244EJ0220 Rev Page 12 of 99

13 1. OUTLINE 1.6 Outline of Functions <R> Remark This outline describes the functions at the time when Peripheral I/O redirection register 0 (PIOR0) are set to 00H. Item (1/2) 20-pin 24-pin 30-pin 32-pin 48-pin R5F1176x (x = 8, A) R5F1177x (x = 8, A) R5F117Ax (x = 8, A, C) R5F117Bx (x = A, C) R5F117Gx (x = A, C) Code flash memory (KB) 8 to 16 KB 8 to 16 KB 8 to 32 KB 16 to 32 KB 16 to 32 KB Data flash memory (KB) 2 KB 2 KB 2 KB 2 KB 2 KB RAM 0.7 to 2.0 KB 0.7 to 2.0 KB 0.7 to 3.0 KB Note 2.0 to 3.0 KB Note 2.0 to 3.0 KB Note Address space 1 MB Main system clock Subsystem clock General-purpose register High-speed system clock (fmx) High-speed on-chip oscillator clock (fih) Max: 24 MHz Middle-speed on-chip oscillator clock (fim) Max: 4 MHz Subsystem clock oscillator (fsx, fsxr) Low-speed on-chip oscillator clock (fil) Minimum instruction execution time Instruction set X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode:1 to 20 MHz (VDD = 2.7 to 3.6 V), HS (High-speed main) mode:1 to 16 MHz (VDD = 2.4 to 3.6 V), LS (Low-speed main) mode:1 to 8 MHz (VDD = 1.8 to 3.6 V), LV (Low-voltage main) mode:1 to 4 MHz (VDD = 1.6 to 3.6 V), LP (Low-power main) mode:1 MHz (VDD = 1.8 to 3.6 V) HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V), LP (Low-power main) mode: 1 MHz (VDD = 1.8 to 3.6 V) 15 khz (TYP.): VDD = 1.6 to 3.6 V XT1 (crystal) oscillation khz (TYP.): VDD = 1.6 to 3.6 V 8 bits 32 registers (8 bits 8 registers 4 banks) μs (High-speed on-chip oscillator clock: fih = 24 MHz operation) 0.05 μs (High-speed system clock: fmx = 20 MHz operation) 30.5 μs (Subsystem clock oscillator clock: fsx = khz operation) Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits 16 bits, 32 bits 32 bits) Multiplication and Accumulation (16 bits 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total CMOS I/O CMOS input N-ch open-drain I/O (6 V tolerance) Timer 16-bit timer 4 channels Watchdog timer 1 channel 4 Real-time clock 12-bit interval timer 8/16-bit interval timer 1 channel 1 channel 4 channels (8 bit) / 2 channels (16 bit) Timer output RTC output 1 channel 1 Hz (subsystem clock generator and RTC/other clock: fsx = khz) Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F117xC (x = A, B, G): Start address FF300H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0244EJ0220 Rev Page 13 of 99

14 1. OUTLINE Item 20-pin 24-pin 30-pin 32-pin 48-pin R5F1176x (x = 8, A) R5F1177x (x = 8, A) R5F117Ax (x = 8, A, C) R5F117Bx (x = A, C) Clock output/buzzer output [20-pin, 24-pin products] 2.44 khz, 4.88 khz, 9.76 khz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fmain = 20 MHz operation) [30-pin, 32-pin, 48-pin products] 2.44 khz, 4.88 khz, 9.76 khz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fmain = 20 MHz operation) 256 Hz, 512 Hz, khz, khz, khz, khz, khz, khz (subsystem clock generator and RTC/other clock: fsxr = khz operation) R5F117Gx (x = A, C) 12-bit resolution A/D converter 6 channels 6 channels 12 channels 12 channels 17 channels (2/2) Comparator (Window Comparator) 2 channels Operational amplifier 2 channels 4 channels <R> <R> Data Operation Circuit (DOC) Serial interface Comparison, addition, and subtraction of 16-bit data [20-pin, 30-pin products] CSI: 1 channel/uart: 1 channel/simplified I 2 C: 1 channel [24-pin, 32-pin, 48-pin products] CSI: 2 channels/uart: 1 channel/simplified I 2 C: 2 channels Data transfer controller (DTC) 16 sources 20 sources 19 sources 20 sources 22 sources Event link controller (ELC) Event input: 15 Event trigger output: 5 Event input: 17 Event trigger output: 5 Event input: 17 Event trigger output: 7 Event input: 17 Event trigger output: 7 Event input: 20 Event trigger output: 7 Vectored interrupt Internal sources External Key interrupt Reset Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector Internal reset by illegal instruction execution Note Internal reset by RAM parity error Internal reset by illegal-memory access Power-on-reset circuit Power-on-reset: 1.51 ± 0.04V (TA = -40 to +85 C) Power-down-reset: 1.50 ± 0.04 V (TA = -40 to +85 C) Voltage detector Power on 1.67 V to 3.13 V (12 stages) On-chip debug function Power supply voltage Power down Operating ambient temperature 1.63 V to 3.06 V (12 stages) Provided (Enable to tracing) VDD = 1.6 to 3.6 V TA = -40 to +105 C The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0244EJ0220 Rev Page 14 of 99

15 Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to Functions for each product in the RL78/I1D User s Manual. Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105 C. Derating is the systematic reduction of load for the sake of improved reliability. Caution 4. When operating temperature exceeds 85 C, only HS (high-speed main) mode can be used as the flash operation mode. Regulator mode should be used with the normal setting (MCSEL = 0). R01DS0244EJ0220 Rev Page 15 of 99

16 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD, AVDD VDD = AVDD -0.3 to V AVREFP 0.3 to AVDD Note 2 V AVSS -0.5 to V AVREFM -0.3 to AVDD Note 2 V and AVREFM AVREFP REGC pin input voltage VIREGC REGC -0.3 to and -0.3 to VDD Note 1 V Input voltage VI1 P00 to P04, P30 to P33, P40, P50 to P57, P121 to P124, P130, P137, EXCLK, EXCLKS, RESET -0.3 to VDD Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to V VI3 P10 to P17, P20 to P to AVDD Note 2 V Output voltage VO1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P to VDD Note 2 V VO2 P10 to P17, P20 to P to AVDD Note 2 V <R> <R> V Analog input voltage VAI1 ANI16 to ANI to VDD and -0.3 to AVREF(+) Notes 2, 3 V VAI2 ANI0 to ANI to AVDD and -0.3 to AVREF(+) Notes 2, 3 VAI3 Operational amplifier input pin -0.3 to AVDD Note 2 V Note 1. Note 2. Note 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μf). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Must be 4.6 V or lower. Do not exceed AVREF (+) V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0244EJ0220 Rev Page 16 of 99

17 Absolute Maximum Ratings (2/2) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P00 to P04, P30 to P33, P40, P50 to P57, P ma Total of all pins -170 ma P00 to P04, P40, P ma P30 to P33, P50 to P ma IOH2 Per pin P10 to P17, P20 to P ma Total of all pins -1.4 ma Output current, low IOL1 Per pin P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P ma Total of all pins 170 ma P00 to P04, P40, P ma P30 to P33, P50 to P57, P60 to P ma IOL2 Per pin P10 to P17, P20 to P ma Total of all pins 5.6 ma Operating ambient temperature TA In normal operation mode -40 to +105 C In flash memory programming mode Storage temperature Tstg -65 to +150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 17 of 99

18 2.2 Oscillator Characteristics X1, XT1 characteristics (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) Resonator Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fx) Note Ceramic resonator/ crystal resonator 2.7 V VDD 3.6 V MHz 2.4 V VDD < 2.7 V V VDD < 2.4 V V VDD < 1.8 V XT1 clock oscillation frequency (fxt) Note Crystal resonator khz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/I1D User s Manual On-chip oscillator characteristics (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fih 1 24 MHz High-speed on-chip oscillator clock frequency accuracy -20 to +85 C 1.8 V VDD 3.6 V % 1.6 V VDD < 1.8 V to -20 C 1.8 V VDD 3.6 V % 1.6 V VDD < 1.8 V to +105 C 2.4 V VDD 3.6 V % Middle-speed on-chip oscillator oscillation frequency Note 2 fim 1 4 MHz Middle-speed on-chip oscillator oscillation frequency accuracy 1.8V VDD 3.6V % Low-speed on-chip oscillator clock frequency Note 2 fil 15 khz Low-speed on-chip oscillator clock frequency accuracy % Note 1. Note 2. High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01DS0244EJ0220 Rev Page 18 of 99

19 2.3 DC Characteristics Pin characteristics (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 IOH1 Per pin for P00 to P04, P30 to P33, P40, P50 to P57, P130 TA = -40 to +85 C Note 2 ma TA = +85 to +105 C -3.0 ma Note 2 Total of P00 to P04, P40, P130 (When duty 70% Note 3 ) 2.7 V VDD 3.6 V ma 1.8 V VDD < 2.7 V -5.0 ma 1.6 V VDD < 1.8 V -2.5 ma Total of P30 to P33, P50 to P57 (When duty 70% Note 3 ) 2.7 V VDD 3.6 V ma 1.8 V VDD < 2.7 V ma 1.6 V VDD < 1.8 V -5.0 ma Total of all pins (When duty 70% Note 3 ) ma IOH2 Per pin for P10 to P17, P20 to P Note 2 ma Total of all pins (When duty 70% Note 3 ) 1.6 V VDD 3.6 V -1.4 ma Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). Total output current of pins = (IOH 0.7)/(n 0.01) <Example> Where n = 80% and IOH = ma Total output current of pins = ( )/( ) -8.7 ma However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P30 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 19 of 99

20 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 IOL1 Per pin for P00 to P04, P30 to P33, P40, P50 to P57, P130 TA = -40 to +85 C 20.0 Note 2 ma TA = +85 to +105 C 8.5 ma Note 2 Per pin for P60 to P Note 2 ma Total of P00 to P04, P40, P130 (When duty 70% Note 3 ) 2.7 V VDD 3.6 V 15.0 ma 1.8 V VDD < 2.7 V 9.0 ma 1.6 V VDD < 1.8 V 4.5 ma Total of P30 to P33, P50 to P57, P60 to P63 (When duty 70% Note 3 ) 2.7 V VDD 3.6 V 35.0 ma 1.8 V VDD < 2.7 V 20.0 ma 1.6 V VDD < 1.8 V 10.0 ma Total of all pins (When duty 70% Note 3 ) 50.0 ma IOL2 Per pin for P10 to P17, P20 to P Note 2 ma Total of all pins (When duty 70% Note 3 ) 1.6 V VDD 3.6 V 5.6 ma Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). Total output current of pins = (IOL 0.7)/(n 0.01) <Example> Where n = 80% and IOL = 10.0 ma Total output current of pins = ( )/( ) 8.7 ma However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 20 of 99

21 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high VIH1 P00 to P04, P30 to P33, P40, P50 to P57, P130 Normal input buffer 0.8 VDD VDD V VIH2 P30, P32, P33, P51, P52, P54 to P57 TTL input buffer 3.3 V VDD 3.6 V TTL input buffer 1.6 V VDD < 3.3 V 2.0 VDD V 1.5 VDD V VIH3 P10 to P17, P20 to P AVDD AVDD V VIH4 P60 to P VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low VIL1 P00 to P04, P30 to P33, P40, P50 to P57, P130 Normal input buffer VDD V VIL2 P30, P32, P33, P51, P52, P54 to P57 TTL input buffer 3.3 V VDD 3.6 V TTL input buffer 1.6 V VDD < 3.3 V V V VIL3 P10 to P17, P20 to P AVDD V VIL4 P60 to P VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET VDD V Caution The maximum value of VIH of pins P30 and P51 to P56 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 21 of 99

22 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high VOH1 P00 to P04, P30 to P33, P40, P50 to P57, P V VDD 3.6 V, IOH = -2.0 ma VDD V <R> 1.8 V VDD 3.6 V Note 3, VDD V IOH = -1.5 ma 1.6 V VDD 3.6 V Note 1, VDD V IOH = -1.0 ma VOH2 P10 to P17, P20 to P V AVDD 3.6 V Note 2, AVDD V IOH = -100 μa Output voltage, low VOL1 P00 to P04, P30 to P33, P40, P50 to P57, P V VDD 3.6 V, IOL = 3.0 ma 2.7 V VDD 3.6 V, IOL = 1.5 ma 1.8 V VDD 3.6 V Note 3, IOL = 0.6 ma 1.6 V AVDD 3.6 V Note 1, IOL = 0.3 ma 0.6 V 0.4 V 0.4 V 0.4 V VOL2 P10 to P17, P20 to P V AVDD 3.6 V Note 2, IOL = 400 μa VOL3 P60 to P V VDD 3.6 V, IOL = 3.0 ma 1.8 V VDD 3.6 V Note 3, IOL = 2.0 ma 1.6 V AVDD 3.6 V Note 1, IOL = 1.0 ma 0.4 V 0.4 V 0.4 V 0.4 V Note 1. Only TA = -40 to +85 C is guaranteed. Note 2. The condition that 2.4 V AVDD 3.6 V is guaranteed when +85 C < TA +105 C. Note 3. The condition that 2.4 V VDD 3.6 V is guaranteed when +85 C < TA +105 C. Caution P30 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 22 of 99

23 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130, P137 VI = VDD 1 μa ILIH2 RESET VI = VDD 1 μa ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VDD In input port or external clock input 1 μa In resonator connection 10 μa ILIH4 P10 to P17, P20 to P25 VI = AVDD 1 μa Input leakage current, low ILIL1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130, P137 VI = VSS -1 μa ILIL2 RESET VI = VSS -1 μa ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) VI = VSS In input port or external clock input -1 μa In resonator connection -10 μa ILIL4 P10 to P17, P20 to P25 VI = AVSS -1 μa On-chip pull-up resistance RU P00 to P04, P30 to P33, P40, P50 to P57, P130 VI = VSS, In input port kω Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0244EJ0220 Rev Page 23 of 99

24 2.3.2 Supply current characteristics (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (1/4) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode fih = 24 MHz Note 3, TA = -40 to +105 C Basic operation VDD = 3.0 V 1.4 ma HS (high-speed main) mode fih = 24 MHz Note 3, TA = -40 to +85 C Normal operation VDD = 3.0 V ma fih = 24 MHz Note 3, Normal VDD = 3.0 V 6.7 TA = +85 to +105 C operation fih = 16 MHz Note 3, Normal VDD = 3.0 V TA = -40 to +85 C operation fih = 16 MHz Note 3, Normal VDD = 3.0 V 4.9 TA = +85 to +105 C operation LS (low-speed main) mode (MCSEL = 0) fih = 8 MHz Note 3, TA = -40 to +85 C Normal operation VDD = 3.0 V ma VDD = 2.0 V <R> <R> LS (low-speed main) mode (MCSEL = 1) fih = 4 MHz Note 3, TA = -40 to +85 C fim = 4 MHz Note 7, TA = -40 to +85 C Normal operation Normal operation VDD = 3.0 V ma VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V <R> LV (low-voltage main) mode fih = 3 MHz Note 3, TA = -40 to +85 C Normal operation VDD = 3.0 V ma VDD = 2.0 V LP (low-power main) mode Note 5 (MCSEL = 1) fih = 1 MHz Note 3, TA = -40 to +85 C fim = 1 MHz Note 5, TA = -40 to +85 C Normal operation Normal operation VDD = 3.0 V μa VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V HS (high-speed main) mode fmx = 20 MHz Note 2, TA = -40 to +85 C Normal operation VDD = 3.0 V Square wave input ma Resonator connection fmx = 20 MHz Note 2, Normal VDD = 3.0 V Square wave input 5.7 TA = +85 to +105 C operation Resonator connection 5.8 fmx = 10 MHz Note 2, Normal VDD = 3.0 V Square wave input TA = -40 to +85 C operation Resonator connection fmx = 10 MHz Note 2, Normal VDD = 3.0 V Square wave input 3.4 TA = +85 to +105 C operation Resonator connection 3.5 LS (low-speed main) mode (MCSEL = 0) fmx = 8 MHz Note 2, TA = -40 to +85 C fmx = 8 MHz Note 2, TA = -40 to +85 C Normal operation Normal operation VDD = 3.0 V Square wave input ma Resonator connection VDD = 2.0 V Square wave input Resonator connection <R> <R> LS (low-speed main) mode (MCSEL = 1) fmx = 4 MHz Note 2, TA = -40 to +85 C fmx = 4 MHz Note 2, TA = -40 to +85 C Normal operation Normal operation VDD = 3.0 V Square wave input ma Resonator connection VDD = 2.0 V Square wave input Resonator connection LP (low-power main) mode (MCSEL = 1) fmx = 1 MHz Note 2, TA = -40 to +85 C fmx = 1 MHz Note 2, TA = -40 to +85 C Normal operation Normal operation VDD = 3.0 V Square wave input μa Resonator connection VDD = 2.0 V Square wave input Resonator connection (Notes and Remarks are listed on the next page.) R01DS0244EJ0220 Rev Page 24 of 99

25 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (2/4) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation fsx = khz, Normal operation Square wave input μa TA = -40 C Note 4 Resonator connection fsx = khz, Normal operation Square wave input TA = +25 C Note 4 Resonator connection fsx = khz, Normal operation Square wave input TA = +50 C Note 4 Resonator connection fsx = khz, Normal operation Square wave input TA = +70 C Note 4 Resonator connection fsx = khz, Normal operation Square wave input TA = +85 C Note 4 Resonator connection fsx = khz, Normal operation Square wave input TA = +105 C Note 4 Resonator connection fil = 15 khz, TA = -40 C Note 6 Normal operation fil = 15 khz, TA = +25 C Note 6 Normal operation fil = 15 khz, TA = +85 C Note 6 Normal operation fil = 15 khz, TA = +105 C Note 6 Normal operation <R> Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When ultra-low-power consumption oscillation is set (AMPHS1, AMPHS0) = (1, 0). The values do not include the current flowing into the real-time clock, 12-bit interval timer, and watchdog timer. When the high-speed system clock, high-speed on-chip oscillator clock, sub clock, and low-speed on-chip oscillator clock are stopped. The MAX values include the current of peripheral operation except BGO operation, and the STOP leakage current. However, the real time clock, watchdog timer, LVD circuit, and A/D converter are stopped. When the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and sub clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. Remark 1. fmx: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fih: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 3. fim: Middle-speed on-chip oscillator clock frequency (4 MHz max.) Remark 4. fil: Low-speed on-chip oscillator clock frequency Remark 5. fsx: Sub clock frequency (XT1 clock oscillation frequency) Remark 6. fsub: Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency) Remark 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 C R01DS0244EJ0220 Rev Page 25 of 99

26 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (3/4) <R> <R> Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current IDD2 HALT HS (high-speed main) mode fih = 24 MHz Note 4, VDD = 3.0 V ma Note 1 Note 2 mode TA = -40 to +85 C fih = 24 MHz Note 4, VDD = 3.0 V 2.85 TA = +85 to +105 C fih = 16 MHz Note 4, VDD = 3.0 V TA = -40 to +85 C fih = 16 MHz Note 4, VDD = 3.0 V 2.08 TA = +85 to +105 C LS (low-speed main) mode fih = 8 MHz Note 4, VDD = 3.0 V μa (MCSEL = 0) TA = -40 to +85 C VDD = 2.0 V LS (low-speed main) mode fih = 4 MHz Note 4, VDD = 3.0 V μa (MCSEL = 1) TA = -40 to +85 C VDD = 2.0 V fim = 4 MHz Note 7, VDD = 3.0 V TA = -40 to +85 C VDD = 2.0 V LV (low-voltage main) mode fih = 3 MHz Note 4, VDD = 3.0 V μa TA = -40 to +85 C VDD = 2.0 V LP (low-power main) mode fih = 1 MHz Note 4, VDD = 3.0 V μa (MCSEL = 1) TA = -40 to +85 C VDD = 2.0 V fim = 1 MHz Note 7, VDD = 3.0 V TA = -40 to +85 C VDD = 2.0 V HS (high-speed main) mode fmx = 20 MHz Note 3, VDD = 3.0 V Square wave input ma TA = -40 to +85 C Resonator connection fmx = 20 MHz Note 3, VDD = 3.0 V Square wave input 2.45 TA = +85 to +105 C Resonator connection 2.57 fmx = 10 MHz Note 3, VDD = 3.0 V Square wave input TA = -40 to +85 C Resonator connection fmx = 10 MHz Note 3, VDD = 3.0 V Square wave input 1.28 TA = +85 to +105 C Resonator connection 1.36 LS (low-speed main) mode fmx = 8 MHz Note 3, VDD = 3.0 V Square wave input μa (MCSEL = 0) TA = -40 to +85 C Resonator connection fmx = 8 MHz Note 3, VDD = 2.0 V Square wave input TA = -40 to +85 C Resonator connection LS (low-speed main) mode fmx = 4 MHz Note 3, VDD = 3.0 V Square wave input μa (MCSEL = 1) TA = -40 to +85 C Resonator connection fmx = 1 MHz Note 3, VDD = 2.0 V Square wave input TA = -40 to +85 C Resonator connection LP (low-power main) mode fmx = 4 MHz Note 3, VDD = 3.0 V Square wave input μa (MCSEL = 1) TA = -40 to +85 C Resonator connection fmx = 1 MHz Note 3, VDD = 2.0 V Square wave input TA = -40 to +85 C Resonator connection Subsystem clock operation fsx = khz, Square wave input μa TA = -40 C Note 5 Resonator connection fsx = khz, Square wave input TA = +25 C Note 5 Resonator connection fsx = khz, Square wave input TA = +50 C Note 5 Resonator connection fsx = khz, Square wave input TA = +70 C Note 5 Resonator connection fsx = khz, Square wave input TA = +85 C Note 5 Resonator connection fsx = khz, Square wave input TA = +105 C Note 5 Resonator connection fil = 15 khz, TA = -40 C Note μa fil = 15 khz, TA = +25 C Note fil = 15 khz, TA = +85 C Note fil = 15 khz, TA = +105 C Note (Notes and Remarks are listed on the next page.) R01DS0244EJ0220 Rev Page 26 of 99

27 <R> Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. When the HALT instruction is executed in the flash memory. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and highspeed on-chip oscillator clock are stopped. When RTCLPC = 1 and ultra-low-power consumption oscillation is set (AMPHS1, AMPHS0) = (1, 0). The values include the current flowing into the real-time clock. However, the values do not include the current flowing into the 12-bit interval timer and watchdog timer. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, high-speed system clock, and sub clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. Remark 1. fmx: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fih: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 3. fim: Middle-speed on-chip oscillator clock frequency (4 MHz max.) Remark 4. fil: Low-speed on-chip oscillator clock frequency Remark 5. fsx: Sub clock frequency (XT1 clock oscillation frequency) Remark 6. fsub: Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency) Remark 7. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 C R01DS0244EJ0220 Rev Page 27 of 99

28 (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (4/4) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current IDD3 STOP mode TA = -40 C μa Note 1 Note 2 Note 3 TA = +25 C TA = +50 C TA = +70 C TA = +85 C TA = +105 C <R> Note 1. Note 2. Note 3. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, operational amplifier, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. The values do not include the current flowing into the real-time clock, 12-bit interval timer, and watchdog timer. For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when operating the subsystem clock in HALT mode. R01DS0244EJ0220 Rev Page 28 of 99

29 Peripheral Functions (Common to all products) (TA = -40 to +85 C, 1.6 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105 C, 2.4 V AVDD = VDD 3.6 V, VSS = AVSS = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note μa RTC operating current IRTC Notes 1, 2, 3 fsx = khz 0.02 μa 12-bit interval timer operating current ITMKA Notes 1, 2, 4 fsx = khz 0.04 μa 8-bit interval timer operating current ITMT Notes 1, 9 fsx = khz fmain stopped (per unit) 8-bit counter mode 2-channel operation 0.12 μa 16-bit counter mode operation 0.10 μa Watchdog timer operating current IWDT Notes 1, 2, 5 fil = 15 khz 0.22 μa A/D converter operating current IADC Notes 6, 10 During maximum-speed conversion AVDD = 3.0 V μa AVREF(+) current IAVREF Note 11 AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = μa Internal reference voltage (1.45 V) current IADREF Notes 1, μa Temperature sensor operating current ITMPS Note μa Comparator operating current ICMP Notes 8, 10 AVDD = 3.6 V, Regulator output voltage = 2.1 V AVDD = 3.6 V, Regulator output voltage = 1.8 V Comparator high-speed mode Window mode Comparator low-speed mode Window mode Comparator high-speed mode Standard mode Comparator low-speed mode Standard mode Comparator high-speed mode Window mode Comparator low-speed mode Window mode Comparator high-speed mode Standard mode Comparator low-speed mode Standard mode 12.5 μa Operational amplifier operating current IAMP Notes 10, 13 Low-power consumption mode One operational amplifier unit operates Note μa Two operational amplifier units operate Note Three operational amplifier units operate Note Four operational amplifier units operate Note High-speed mode One operational amplifier unit operates Note Two operational amplifier units operate Note Three operational amplifier units operate Note Four operational amplifier units operate Note LVD operating current ILVD Notes 1, μa (Notes and Remarks are listed on the next page.) R01DS0244EJ0220 Rev Page 29 of 99

30 <R> Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Current flowing to VDD. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are stopped. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and ICMP when the comparator circuit is in operation. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current flowing to AVDD. Current flowing into AVREFP. Current consumed by generating the internal reference voltage (1.45 V). Current flowing only to the operational amplifier. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and IAMP when the operational amplifier is operating in operating mode, HALT mode, or STOP mode. The values include the operating current of the operational amplifier reference current circuit. Remark 1. fil: Low-speed on-chip oscillator clock frequency Remark 2. fsub: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fclk: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP. value is TA = 25 C R01DS0244EJ0220 Rev Page 30 of 99