Design of an Op-Amp Gain Compensator for Switched-Capacitor Integrators

Transcription

1 國立交通大學 電機與控制工程學系 碩士論文 交換電容式積分器 之運算放大器增益補償的設計 Design of an Op-mp Gain Compensator for Switched-Capacitor Integrators 研究生 : 許皓淵指導教授 : 鄭木火博士 中華民國九十七年七月

2 交換電容式積分器 之運算放大器增益補償的設計 Design of an Op-mp Gain Compensator for Switched-Capacitor Integrators 研究生 : 許皓淵指導教授 : 鄭木火博士 Student : Hao-Yuan Hsu dvisor : Dr. Mu-Huo Cheng 國立交通大學 電機與控制工程學系 碩士論文 Thesis Submitted to Department of Electrical and Control Engineering College of Electrical Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electrical and Control Engineering July 008 Hsinchu, Taiwan, Republic of China 中華民國九十七年七月

3 交換電容式積分器 之運算放大器增益補償的設計 研究生 : 許皓淵 指導教授 : 鄭木火博士 國立交通大學電機與控制工程學系 摘要 在類比系統中, 切換電容積分器為具有重要功能的電路 切換電容積分器包含一運算放大器 運算放大器的非理想特性, 例如有限增益, 有限頻寬以及輸入偏移將會降低積分器的效能 舉例來說, 運算放大器之有限增益將會使離散時間積分器的極點偏離理想位置 z=, 造成有限的直流增益及相位誤差 這個影響顯著地降低了三角積分調變器之 MSH 架構的性能, 因為對雜訊修整濾波器而言直流值上不再有一零點 一直接的方法為設計運算放大器有非常大的增益, 但是以現在的技術要達到高增益是非常複雜以及幾乎不可能 在本論文中我們專注於有限增益運算放大器對切換電容積分器的影響, 並且設計一可以降低因運算放大器有限增益所造成在積分器之轉移函數上誤差的新型切換電容積分器 因此, 這經過設計的積分器可以等效增加運算放大器的增益, 以及改善其在應用上的效能 此新架構是以相關雙取樣的方法及利用回授運算放大器被提出 我們首先推導其轉移函數並使用 MTLB 計算因運算放大器有限增益造成的誤差 其性能將與現有的電路做比較 接著, 我們使用 TSMC 0.35 微米互補式金氧半的製程來設計, 以及 HSPICE 來模擬電路在數個頻率之頻率響應 預先模擬與佈局後模擬的結果接近相同, 並且與原始設計規格相符 最後畫出電路佈局, 晶片大小大約是 40 35µm 關鍵詞 : 相關雙取樣, 交換電容式積分器, 有限增益 i

4 Design of an Op-mp Gain Compensator for Switched-Capacitor Integrators Student: Hao-Yuan Hsu dvisor: Dr. Mu-Huo Cheng Institute of Electrical and Control Engineering National Chiao-Tung University bstract The Switched Capacitor(SC) integrator is an important functional circuit block in the analog systems. SC integrator contains an operational amplifier. The non-idealities of the operational amplifier, such as the finite gain, the finite bandwidth, and the input offset will degrade the performance of the integrator. For example, the finite-gain of the operational amplifier will make the pole of discrete-time integrator deviate from the ideal position z = yielding a DC finite gain and phase error in the SC integrator. This effect degrades significantly the performance of delta sigma modulators via the MSH structure, because the noise-shaping filter has no longer a zero at DC. One direct approach is to design an op-amp with extremely high gain, but it is complicated and nearly impossible via the present technology. In this thesis, we focus on the effect of finite-gain op-amp in SC integrators, and design a new SC integrator circuit which can reduce the error in the integrator transfer characteristic due to the finite-gain of the op-amp. Hence, the designed integrator enhances equivalently the op-amp finite gain, and improves the performance in applications. The new topology is proposed using the feedback op-amp and the correlated double sampling (CDS) technique. We first derive the transfer function and use MTLB to evaluate the errors arisen from the effect of finite-gain in op-amp. The performances of proposed circuit and other existing circuits are compared. Then, we design the circuit using TSMC 0.35µm CMOS technology, and simulate the circuit frequency responses at several frequencies via HSPICE. The pre-sim or post-sim simulation results are approximately identical, and conform to the original design specifications. Finally, the layout is drawn and the chip size is about 40 35µm. Keywords: CDS, SC Integrator, Finite-Gain ii

5 誌謝 在這短暫的兩年研究所生活, 我要特別感謝鄭木火教授, 由於老師的指導, 使得此論文能順利完成 老師在治學態度上的嚴謹細心, 使我在學識上獲益良多 因此, 在本論文付梓之際, 對於辛勤傳道並耐心授業的老師致上最誠摯的謝意 在口試期間, 承蒙口試委員蘇朝琴教授 莊正教授以及方維倫教授撥冗指導並提供許多寶貴意見, 使此論文能更臻於完善, 在此也誠摯地感謝你們的辛勞 同時, 我要感謝 Lab94 同仁們 感謝已畢業的學長衍禎與嘉華的提攜與照顧 實驗室一起學習的夥伴宏楊 嘉明 志全 立中與英哲, 在課業上的砥礪互勉以及生活中的鼓勵和幫忙, 都成為我求學生涯中最好的助力 也感謝學弟啟仁 明華與建男, 因為你們的幫忙, 讓我能更專心於研究上 最後, 我要特別感謝我的家人, 尤其是我的父母親, 因為你們長久以來的支持和包容體諒, 使我能順利完成學業 僅以此小小的成果, 呈現給我的親朋好友, 並感謝所有曾幫助過我的人 iii

6 Contents BSTRCT IN CHINESE BSTRCT IN ENGLISH 誌謝 Contents List of Figures List of Tables i ii iii iv vi x Introduction. Background Motivation n Overview of Integrator 5. Introduction Switch Capacitor Integrator Continuous time Integrator Switched Capacitor Integrator Non-ideal Effects of Switched Capacitor Integrator Double-Sampled Technique Summary The Gain-Compensated SC Integrators 0 3. SC Integrator With No Compensation Introduction Conventional SC Integrator Existed Gain-Compensated Integrators Introduction Single-Sampled Gain-Compensated Integrator iv

7 3..3 Double-Sampled Gain-Compensated Integrator The Modification of Double-Sampled Gain-Compensated SC Integrators New Single-Sampled Gain-Compensated SC Integrator Simulation nd Results Operational mplifier nd Common Mode Feedback Switch Simulations Of New Single-End Gain-Compensated Integrator Conclusion 67 bibliography 68 v

8 List of Figures. Block diagram of delta-sigma modulator with a - MSH structure SNR variations with amplitude for a - MSH structure SNR variations with amplitude for a - MSH structure and a comparison between conventional and gain-compensated integrator CT non-inverting integrator CT inverting integrator Magnitude and phase response for CT integrator Magnitude and phase response for inverting CT integrator when (0) and UGB are finite (a) Switched capacitor resistor (b) and the equivalent circuit (c) and the clock signal with the equivalent circuit (a) Negative and (b) positive switched capacitor circuit (a) Inverting and (b) non-inverting SC integrator that are insensitive to parasitic capacitors Magnitude response of CT and DT non-inverting integrator Phase response of CT and DT non-inverting integrator Small-signal models of (a) sampling (b) integrating non-inverting SC integrator [] SC integrator during integration phase Feedback model consisting of a feedforward term d(s), a feedback term β(s), an amplifier OL (s), and an input scaler γ(s) [8] Equivalent circuits for (a) γ(s) (b) β(s) for an ideal SC integrator [8] Op-amp with offset voltage Inverting SC integrator with offset error SC integrator with offset error at (a) sampling phase (b) integration phase Simple configuration using an NMOS switch to show charge injection []... 6 vi

9 .8 Double-sampled SC integrator first-order double-sampled delta sigma modulator [7] first-order double-sampled modulator using additive-error switching [7] (a) Non-inverting and (b) Inverting SC integrator Non-inverting SC integrator during (a) φ and (b) φ Inverting SC integrator during (a) φ and (b) φ Non-inverting double-sampled SC integrator Non-inverting double-sampled SC integrator during (a) φ and (b) φ Non-inverting double-sampled SC integrator with two integration capacitors Non-inverting double-sampled SC integrator with two integration capacitors during (a) φ and (b) φ Gain-compensated SC integrator with limit in input [] The SC integrator during (a) phase and (b) phase Gain-compensated SC integrator with no limitation for input signal [3] The SC integrator during phase (a) φ and (b) φ The frequency response of the macro model op-amp with 40dB magnitude The output voltage of the SC integrator with no gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The output voltage of the SC integrator with gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The output voltage of the SC integrator with no gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =80dB Double-sampled and gain-compensated SC integrator with no limit to input [4] Double-sampled and gain-compensated SC integrator with no limit to input during phase (a) φ and (b) φ Magnitude errors of the integrator for =, f in = 0kHz, and f s = 0MHz The vary double-sampled and gain-compensated SC with no limit to input The vary double-sampled and gain-compensated SC with no limit to input during (a) φ and φ The comparison of gain errors between paper proposed and we proposed for κc a = C b = = κc s = C s = = C f, f in = 0kHz, and f s = 0MHz.. 38 vii

10 3. The output voltage for a non-inverting SC integrator with no compensation shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The transferred charge on the integration capacitor, shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The output voltage for a SC integrator that paper proposed shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The transferred charge on the integration capacitor, shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The output voltage for a SC integrator shown in Fig. 3.9, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The transferred charge on the integration capacitor, shown in Fig. 3.9, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB The transferred charge on the integration capacitor, shown in Fig. 3.9, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =0dB The transferred charge on the integration capacitor, shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =0dB new single-sampled gain-compensated SC integrator single-sampled gain-compensated SC integrator during (a) phase (b) phase simple feedback system The output voltage for a SC integrator shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =40dB, and f = 80dB Magnitude errors of the integrator for = = C c = C c, f in = 0kHz, and f s = 0MHz Magnitude of pole errors for conventional circuit and new gain-compensated topology fully differential folded-cascode operational amplifier with common-mode feedback wide-swing constant transconductance bias circuit The frequency response of the fully differential folded-cascode amplifier (a) 50dB magnitude (b) 88 phase margin Simulation of bias output voltage Single-end folded-cascode op-amp with output buffer viii

11 3.4 The frequency response of a single-end folded-cascode op-amp (a) 60dB magnitude (b) 84 phase margin Definition of speed in a sampling circuit for NMOS switch Definition of speed in a sampling circuit for Transmission gate Comparison of on-resistance of switch The output voltage for a SC integrator with no compensation shown in Fig. 3.(a), f in = 0kHz with amplitude mv, f s = 0MHz, and =50dB The FFT of the output voltage for a SC integrator with no compensation shown in Fig. 3.(a), f in = 0kHz with amplitude mv, f s = 0MHz, and =50dB The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 30kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 30kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The post simulation for a SC integrator that we proposed, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The magnification for a SC integrator that we proposed by varying the input frequency shown in Fig. 3.30, with amplitude mv, f s = 0MHz, =50dB, and f = 60dB Layout photo of the new gain-compensated switched capacitor integrator ix

12 List of Tables 3. Simulated summary of the fully differential folded-cascode amplifier x

13 Chapter Introduction. Background Integrators are used in many analog systems, such as over-sampled analog-to-digital converters, filters, and so on []. Perhaps the most popular approach for realizing analog signal processing in MOS integrated circuits is through the use of Switched-Capacitor (SC) circuits, because they can get accurate frequency response. The filter coefficients are determined by capacitance ratio which can be set quite precisely in an integrated circuit. SC circuit is realized with the use of some basic building blocks, such as op-amp, capacitors, switches, and non-overlapping clock. The basic principles of a SC integrator can be well understood with an ideal op-amp. However, some important non-idealities of the op-amp in practical SC circuits are DC gain, unit-gain frequency, phase margin, slew rate, and dc offset [3]. The DC gain of amplifiers in a MOS technology intended for SC circuits is typically on the order of 40dB to 80dB. Low gain affects the coefficient of the discrete time transfer function of the Silters. The unit-gain frequency and phase margin of an op-amp gives an indication of the small signal settling behavior of an op-amp. general rule of the thumb is the clock frequency should be at least five times lower than the unit-frequency assuming phase margin is greater than 70 degrees [4]. The trade off between gain and bandwidth makes high speed and high accuracy circuits not easy be designed. Chapter reviews an overview and modeling of the integrators for both discrete time and continuous time. The non-idealities of the SC integrators, and a double sampling technique that used to improve the sampling rate are also introduced. Chapter 3 demonstrates the design, theory, implementations and simulations of the gain-compensated SC integrators. way called CDS technique can significantly enhance the op-amp finite gain and reduce the input offset

14 voltage. It is very attractive when used for the delta sigma modulators with MSH structure to reduce the pole error. Finally, we proposed a new topology that have effectively high op-amp finite gain.. Motivation Q ( z) X(z) ( ) z ( ) z Y (z) z Y(z) Q ( z) ( ) z ( ) z Y (z) z Figure.: Block diagram of delta-sigma modulator with a - MSH structure The cascaded (MSH) structure provides the high order noise shaping combined with the robust stability of the first order system. The overall performance, in general, is largely determined by the characteristics of the analog components, specially the integrator. The actual integrator transfer function differs from the ideal case due to the nonzero switch resistance, finite DC gain, finite bandwidth of op-amp, and so on. In general, the integrator transfer function can be written as [4] H(z) = V out(z) V in (z) = ( ζ)z (.) ( δ)z Where ζ and δ are the gain error and pole error, respectively. The effects of the gain error and the pole error can be derived by the analysis of typical delta-sigma modulators with a - MSH structure shown in Fig... nalysis of Fig.., assume the errors ζ i and δ i (i= and ) are small. The z-domain output of first, second, and the overall of the modulator is given by Y (z) ( ζ )z X(z) + [ ( δ )z ]Q (z) (.) Y (z) ( ζ )z Q (z) + [ ( δ )z ]Q (z) (.3)

15 Y (z) = Y (z) z + Y (z) ( z ) = ( ζ )z X(z) + [δ z + ζ z ( z )]Q (z) + [( z ) + δ z ( z )]Q (z) (.4) The second and the third term of Eq.(.4) are quantization noise due to the pole error and gain error. In the second term, the noise of first integrator due to the pole error δ is unshaped. However, the pole error of second modulator and both of the gain error was shaped to high frequency, because a zero at DC. It makes the first integrator be a dominant factor that influence the performance of MSH structure. ssuming a conventional SC integrator, the capacitor mismatch of the sampling capacitor and integration capacitor cause the gain error was 0.0. The finite gain of op-amp is 40dB, then the transfer function can described as V out (z) V in (z) = The ideal transfer function, can be described as z ( + ) ( + )z =.0z.0.0z (.5) V out (z) V in (z) = z z (.6) The entire analog, clock and digital control circuits for the modulators has been implemented in software by Matlab and Simulink. Taking the transfer function of Eq.(.5) and substitute it into the block diagram shown in Fig... The SNR obtained by varying the signal amplitude shown in Fig.., and depict the quantization noise cannot be shaped when the non-ideal integrator at first stage. However, if the non-ideal integrator at second stage, it will not decrease the performance of the whole system. From Fig.. and the derivation of Eq.(.4), we can find that non-ideality due to op-amp finite gain for the SC integrator at first stage in MSH structure dominate the performance. One direct approach to reduce the error is to design a high gain op-amp. Taking the transfer function of Eq. (.5), and assume is 60dB. From the simulation result shown in Fig..3, we can find that the SC integrator with high gain at first stage really reduce the errors. In order to solve the pole error that caused by op-amp finite gain, we try to find some way that can enhance the op-amp gain, and don t need to change the op-amp itself. way called Correlated Double Sampling (CDS) technique can used for the SC integrator. It sampled the error at one half phase, then compensated it at next half phase, and makes the op-amp finite gain effectively enhanced. In this thesis, we will show how the compensated SC integrator work. Finally, a new topology is proposed. 3

16 90 80 Nnoideal first stage Nonideal second stage Ideal integrator SNR (db) Signal mplitude (db) Figure.: SNR variations with amplitude for a - MSH structure Integrator with no first stage Integrator with gain first stage SNR (db) Signal mplitude (db) Figure.3: SNR variations with amplitude for a - MSH structure and a comparison between conventional and gain-compensated integrator 4

17 Chapter n Overview of Integrator. Introduction This chapter discuss the difference between Discrete Time(DT) and Continuous Time(CT) integrators, and the non-idealities of the real integrators, then a double sampling technique that used to increase the sampling rate also introduced. There are several non-idealities of a op-amp, such as finite gain, finite bandwidth, settling time, offset voltage, and so on, which all need to be concerned when design a SC integrator. The transfer function of the integrators used in the systems must be closed to an ideal function, /( z ). The chapter will debate the trade off between both the specifications, and review some basic concepts of the SC integrators.. Switch Capacitor Integrator.. Continuous time Integrator CT integrator as shown in Fig.. and Fig.. are non-inverting and inverting topology. The ideal transfer function of the two topology can given by [3] where ω I = integrator frequency V out (jω) V in (jω) = = jω I jωr C ω V out (jω) V in (jω) = τ I = integrator time constant = j ωτ I (.) jωr C = jω I ω = j ωτ I (.) Both of the two ideal integrator have magnitude and phase response shown in Fig..3. The magnitude response is the same but phase response is different by 80. From Eq. (.) and Eq. (.) can find it has a pole at zero in frequency domain. 5

18 Vin R C R R Vout Figure.: CT non-inverting integrator Vin R C Vout Figure.: CT inverting integrator Here we add the influence of finite gain and finite unit-gain-bandwidth (UGB) to CT inverting op-amp show in Fig.., and the closed-loop transfer function can be described as V out (s) V in (s) = ( sr C ) (s)sr C +sr C + (s)sr C +sr C ssume that (s) of op-amp can be described as (s) = = ( ω I s ) (s)(s/ω I ) (s/ω I )+ + (s)(s/ω I) (s/ω I )+ (.3) (0) + s ω 3dB (.4) t low frequencies (s 0), (s) is approximately (0) and (.3) becomes V out V in = (0) (.5) t high frequencies (s ), (s) is approximately UGB, and (.3) becomes s V out = ( UGB )( ω I V in s s ) (.6) Eq. (.) (.5) and (.6) describe the different frequency transfer function of Eq. (.3). In order to discriminate the frequency region of the non-ideal integrator due to op-amp finite gain and bandwidth. We can simply assume Eq. (.) equal to Eq. (.5) and Eq. (.6), and can get ω x = ω I (0) (.7) ω x = UGB (.8) 6

19 00 Vout(s)/Vin(s) 50 db rg[vout(s)/vin(s)] rad/s 0 Noninverting Inverting log Figure.3: Magnitude and phase response for CT integrator 50 Vout(s)/Vin(s) Magnitude 0 db X X3 X rg[vout(s)/vin(s)] Phase rad/s 3 X4 X log Figure.4: Magnitude and phase response for inverting CT integrator when (0) and UGB are finite Here we assume the integrator frequency ω I is 0kHz, unit-gain-bandwidth UGB is 0MHz, and op-amp gain is 40dB. The resulting magnitude and phase response of inverting integrator show how the gain and pole effect the ideal integrator. From the simulation result shown in Fig..4, where X = ω x is due to op-amp finite gain, X = ω x is due to op-amp finite bandwidth, and X 3 = ω I is the integrator frequency. The idealness of the integrator is determine whether the phase is nearly ±90. From the phase response of Fig..4 can get the operational frequency range of CT integrator at the interval between X 4 and X 5, the CT integrator will approximate ideal behavior, where X 4 = 0ω I (0) and X 5 = UGB 0 [3]. s we can see, a real integrator was limited by the two parameters, gain and bandwidth of op-amp. 7

20 .. Switched Capacitor Integrator Consider the circuit shown in Fig..5. The dynamic circuit is useful in simulating a large value of resistor, generally > MΩ which not occupy much area in layout []. The clock signals φ and φ form two phase of non-overlapping clock signal. v S S v C v R sc v (a) (b) v C T (c) v C Figure.5: (a) Switched capacitor resistor (b) and the equivalent circuit (c) and the clock signal with the equivalent circuit When φ is high, the S is on and the capacitor C is charged to V The charge q stored on the capacitor during this interval is q = CV (.9) When S is on, the charge stored on the capacitor is q = CV (.0) If V and V are not equal, then a charge equal to the difference between q and q is transferred during the interval of clock. The average current is given by I avg = C(V V ) T = V V R sc (.) The resistance of the switched capacitor circuit is given by R sc = T C = Cf clk (.) 8

21 C C V V V V (a) (b) Figure.6: (a) Negative and (b) positive switched capacitor circuit Vin Cs Vout Vin Cs Vout (a) (b) Figure.7: (a) Inverting and (b) non-inverting SC integrator that are insensitive to parasitic capacitors Where f clk is the clock frequency and R sc is the equivalent resistance. Because the SC resistor of Fig..5 is sensitive to parasitic capacitors, it finds little use. Consider the circuit of Fig..6 (a) negative and (b) positive switched capacitor resistor that are insensitive to the capacitor parasitics [6], and using the switched capacitor resistor to replace the R of Fig... The non-inverting and inverting SC integrator are shown in Fig..7. The ideal transfer function of non-inverting integrator can be described as H(z) = V out(z) V in (z) = ( z ) z = ( ) z (.3) To get the frequency response, replace z by e jωt and get H(e jωt ) = V out(e jωt ) V in (e jωt ) = ( ) e jωt = ( e jωt/ ) (.4) e jωt/ e jωt/ Replacing e jωt/ e jωt/, Eq.(.4) becomes H(e jωt ) = ( e jωt/ ) j sin(ωt/) = ( ωt/ )( jωt sin(ωt/) )(e jωt/ ) (.5) Where the integrator frequency can be expressed as ω I = T (.6) 9

22 0 Vout(w)/Vin(w) SC integrator CT integrator 8 Magnitude (db) 6 4 Wi W/W s Figure.8: Magnitude response of CT and DT non-inverting integrator 4 3 rg[vout(w)/vin(w)] SC integrator CT integrator Phase (rad/s) 0 Wi W/W s Figure.9: Phase response of CT and DT non-inverting integrator The integrator frequency, ω I, of the SC integrator can be well defined, because it is proportional to the ratio of capacitors. The second and third terms in Eq. (.5) represent the magnitude and phase error respectively. Here, we assume the CT integrator frequency ω I is equal to 0. ω s, where ω s is five times the sampling frequency ω s of a SC integrator, and ω is the input frequency. The comparison between ideal CT and DT integrators shown in Fig..8 and Fig..9 are magnitude and phase frequency response. The magnitudes of the CT and DT integrators are closed to each other when input frequency is smaller than ω I, but the phase is equal only when ω = 0. We can find when the input signal compare to the sampling frequency is low, like delta sigma modulator. The DT integrator would work like a CT integrator. In many applications, a non-inverting and an inverting SC integrators are in series in a feedback loop [3]. Then, the phase errors of each integrator will be canceled. 0

23 ..3 Non-ideal Effects of Switched Capacitor Integrator The non-ideal behavior of the SC integrators include charge injection, finite gain, settling time, slew rate of amplifier and so on. In this section, we will consider some primary nonidealities of the SC integrators. Finite Gain of mplifier V in C p V x -V x C l V out V in V x C p -V x C l Vout (a) (b) Figure.0: Small-signal models of (a) sampling (b) integrating non-inverting SC integrator [] Fig..0 shows the small-signal linear model of Fig..7 (b). The transfer function of the integrator can be calculated and expressed as [] H(z) = ( r z ) r (.7) r z Where r and r are the closed-loop static errors. They can be expressed r = r = f + f f + f (.8) (.9) Where f and f are the Deedback factors during both sampling and integration phase. They can be expressed f = f = + C p (.0) + + C p (.) Where is the sampling capacitor, is the integration capacitor, and C p is the parasitic capacitor of op-amp. s can be seen from Eq.(.7), the gain and pole errors of the integrator transfer function depend on the gain of the amplifier and the dc feedback factors.

24 Slew Rate of mplifier The SC integrators like Fig..7 are less sensitive to slew-rate limits than amplifiers. This is because the feedback capacitor,, holds the output voltage of the op-amp constant when no capacitors are being connected to the inverting inputs of the op-amp. Slew-rate limitations occur only when the output of op-amp is changing due to the change of charge on during the interval of integration phase. To avoid this limitation, it is necessary that the following inequality be satisfied[3] v out (max) SR Where v out (max) is the maximum output swing of the integrator, T is the integration time. Setting time of amplifier < T (.) -V in V out C p Figure.: SC integrator during integration phase The realization of high-speed and high-accuracy SC integrators are critical for analog signal processing applications, such as data converters. key component is the settling time of op-amp. The non-inverting integrator of Fig..7(b) sampled the input voltage by during φ, and then transferred to during φ. During the integration phase φ, the op-amp output must settle to desire level of accuracy within the allotted time. Fig.. shows the configuration of SC integrator during the integration phase, assuming ideal switches. To develop a generalized analysis for SC integrator during the integration phase, the circuit in Fig.. is mapped into the general model [8] shown in Fig... The closed loop is given by CL (s) = γ(s) OL(s) + d(s) (.3) + OL (s)β(s)

25 d(s) -Vin out γ(s) -(s) V Figure.: Feedback model consisting of a feedforward term d(s), a feedback term β(s), an amplifier OL (s), and an input scaler γ(s) [8] β(s) -V in - V V out Cp Cs - Cp V (a) (b) Figure.3: Equivalent circuits for (a) γ(s) (b) β(s) for an ideal SC integrator [8] The amplifier transfer function (s) can be expressed as OL (s) = (0) + s ω 3dB (.4) Where γ(s) is the transfer function from the integrator input to the input terminals of the op-amp is simply a capacitive network. It is determine by the equivalent circuit shown in Fig..3(a), and can be expressed γ = + + C p (.5) Where β(s) is the feedback transfer function. It is computed from the equivalent circuit shown in Fig..3(b), and can be expressed β = + + C p (.6) The contribution of V in to V out is determined by the feedforward transfer function, d(s). The SC integrator, d(s) contributes an RHP zero at ω z = g m / [8], where g m is the transconductance of op-amp. The effect of the RHP zero is to cause a small initial step in the output that is opposite in direction to the response to the input step. 3

26 For the SC integrator, the feedforward term, d(s), is much smaller than the first term in Eq.(.3) and can be neglected. During the integration phase, the closed-loop gain of the inverting SC integrator can be described as CL (s) OLγ + OL β (.7) Combine Eq.(.4) and Eq.(.7), and assuming /[β OL (0)], we can get CL (s) + j γ β f f UGB β (.8) Where f 3dB OL (0) = f UGB is the unit-gain frequency, the step response of a single-pole system with time constant, τ, can be expressed as τ = πf UGB β (.9) For a step input to the op-amp, the output voltage is given by V out = V outfinal ( e t/τ ) (.30) For the output voltage of the op-amp to settle less than % of its final value, V outfinal, requires 5τ []. rule-of-thumb estimate for the settling time is simply /(f UGB β). Offset of mplifier Op-amp with offset - V + V V os V out Offset free op-amp Figure.4: Op-amp with offset voltage The source of offset may arise from the physical design of the differential amplifier or process variations. Circuit thresholds, mismatch of device sizes, are all source of offset error. Many different techniques for calibrating differential amplifier offset error have been proposed. 4

27 V in - V V out V os Figure.5: Inverting SC integrator with offset error - V V os V out V in - V V os V out (a) (b) Figure.6: SC integrator with offset error at (a) sampling phase (b) integration phase One analog technique involves careful physical layout to minimize the basic offset error, or the use of a switch capacitor circuit to correct offset error shown in Fig..4. nother digital technique is to cancel the offset at the output of amplifier [5]. Here we discuss a topical way that used to cancel the offset voltage with switched capacitor topology. n inverting SC integrator shown in Fig..5 is used to discuss. When Φ on, the integrator start to sample the offset voltage with the capacitor shows in Fig..6 (a). Then, next phase Φ on, it integrate the input voltage shown in Fig..6 (b). t the same time the voltage that storage on during previous phase Φ, will cancel the offset voltage. The offset voltage will not be integrated to the output for one cycle clock period. Charge Injection Charge injection can be simple displayed in Fig..7. When the MOSFET switch is on, and V ds is small, the charge under the gate oxide resulting from the inverted channel is Q ch. When the MOSFET turn off, this charge is injected to the capacitor and V in. However the charge is less effect when the switch turn on, because the input voltage is connected to C through the 5

28 v in Charge Injection C Figure.7: Simple configuration using an NMOS switch to show charge injection [] channel resistance makes the error unimportant. Charge injection is itself a complex one. It has been shown that if the clock signal turns off fast, the channel charge is distributes fairly equally between the adjacent nodes. Thus, half of the channel charge is distributed onto C [], and if it is assumed that clock swings between VDD and ground, the charge that appear at the output of C can be approximated as Where V c = C oxwl(v DD V in [V THN0 + γ( V fp + V in V fp )]) C C ox = Oxide capacitance per area V fp = Electrostatic potential of p-type substrate V THN = NMOS threshold voltage (.3) Eq.(.3) shows the problem associate with charge injection. The change in voltage across C is nonlinear where respect to V in due to the threshold voltage. Thus, it can be said that if the charge injection is signal-dependent, harmonic distortion appear, such as sampled-data systems. In this section we have discussed some non-ideal effects that primary occur at switched capacitor topology. There are still many other effects, such as clock jitter, capacitive feedthrough, thermal noise, and so on, still need to be concerned. One of the important non-ideal effects is op-amp finite gain and will still be discussed in next chapter..3 Double-Sampled Technique conventional single-sampled SC integrator is shown in Fig..7. It consists of op-amp, one sampling capacitor, one integrating capacitor, and several switches that are controlled by a two-phase nonoverlapping clock. With this approach, the output is updated only during φ, and the maximum sampling rate is limited to /(τ), where τ is the op-amp settling time. From Eq.(.9) can find the minimum settling time. 6

29 V in C s V out Figure.8: Double-sampled SC integrator To increase the sampling rate without reducing the op-amp settling time, a double sampling technique can be used [7, 9] shown in Fig..8. During φ, sampled the input voltage and transferred the charge that have been stored at previous half phase to. During φ, both two capacitors also do the same thing. Therefore, the output is updated during both two half phase. The maximum sampling rate is limited to /τ, where τ is the settling time of op-amp. The sampling rate is twice of the single-sampled SC integrators. The double sampling SC integrator uses two capacitors and to sample the input voltage. Each sampling capacitor samples the input by multiplying its capacitor by V in. If, the charge that transferred to will be different. But the errors due to the mismatch of capacitors and will be modulated to half of the sampling frequency, which can be filtered easily. Here we will show how it work. When φ on, was integrated by, and it can be expressed as V out (n ) = V out (n ) + V i (n 3 ) (.3) When φ on, was integrated by, and can be expressed V out (n) = V out (n ) + V i (n ) (.33) ssume that = + / and = /, then the input-output relationship can be written as [7] V out (n) = V out (n ) + V i (n ) + ( )n V i (n ) (.34) The last term of Eq.(.34) is the product of the input and ( ) n, which is the modulation of the input by a sampled cosine at frequency f s /, because ( ) n = cos(π((f s /)nt)).therefore, the errors can filtered to high frequency. 7

30 V in Cs C s D Q V out out V r out -V r Figure.9: first-order double-sampled delta sigma modulator [7] V in V r Y Cs C r Z Y Z C r D Q FSM V out Y Z Y Y Z Z Figure.0: first-order double-sampled modulator using additive-error switching [7] lthough a double sampling SC integrator is very attractive to have twice sampling rate, and have no problem on sampling capacitors mismatch for input voltage. However, when consider the application for delta sigma modulator shown in Fig..9, the errors that from the output quantizer will mixe to the baseband. Because the modulator works like a filter, and will shape the noise from baseband to high frequency. When there is a mismatch between and. From Eq.(.34), the noise that have already shaped to high frequency now will be mixed to baseband. There are many way [7, 9, 0] have been proposed to solve this problem. Fig..0 shows a first order double-sampled delta sigma modulator with a finite state machine(fsm) [7]. Compare to the conventional modulator show in Fig..9, the different of them are quantizer and FSM. The key point here is that the quantizer voltage V r shows in Fig..0 not switching. There is a constant voltage V r at the op-amp input, it means that quantization noise will not mixed to the baseband. The FSM used here is to control phase Z and Y, which not only provide positive or negative feedback voltage V r, but also make the function of Eq.(.34) work. The algorithm that form by FSM is not complex and can be constructed by digital circuit. The double sampling way that used to improve the sampling rate is very attractive. 8

31 .4 Summary In this chapter we have discussed the difference between CT and DT integrators. Both of them will be similar when the input frequency of the DT integrators relative to the sampling frequency is low. The phenomenon makes the topology that operate at high frequency very attractive, such as delta sigma modulators. The non-idealities of the SC integrators and the trade off between both of them are also discussed. One of the non-idealities is the op-amp finite gain, if it has infinite value, the SC integrator will work like an ideal integrator /( z ). The op-amp finite gain makes the pole of discrete-time integrator deviate from the ideal position z = yielding a Dinite gain in the SC integrator. There are some trade off between those non-ideal parameters when design a circuit, how to choose the specification depends on the applications. double-sampled technique that used to increase the sampling rate makes it easier to design the bandwidth of op-amp, because there is a trade off between high gain and high bandwidth of op-amp. However, the offset voltage may not canceled during one of half phase. In next chapter, a SC integrator that has effective high gain will be introduced, It uses a CDS technique to sample the errors due to op-amp finite gain, then compensates it at next half phase. 9

32 Chapter 3 The Gain-Compensated SC Integrators 3. SC Integrator With No Compensation 3.. Introduction This chapter discuss the SC integrators with no compensation first, then a CDS technique that used to compensate the errors due to op-amp finite gain will be introduced. The sampling frequency of the SC integrators is limited by the op-amp settling time. circuit combine the CDS technique with double sampling frequency is very attractive. However, there is a trade off between op-amp offset voltage and sampling frequency. The comparison between doublesampled and single-sampled technique can makes it more clear. Finally, we proposed a new single-sampled gain-compensated SC integrator, the simulation results and math derivation are all conform to the original design specifications. 3.. Conventional SC Integrator Vin Φ C s Φ Φ Φ Φ Φ V - Vout Vin Φ Φ Φ Φ Φ Φ - V Vout Φ Φ Φ Φ (a) (b) Figure 3.: (a) Non-inverting and (b) Inverting SC integrator 0

33 V in Vout - V Vout (a) (b) Figure 3.: Non-inverting SC integrator during (a) φ and (b) φ Cs - V Cf V out V in - V V out (a) (b) Figure 3.3: Inverting SC integrator during (a) φ and (b) φ The topology shown in Fig. 3. (a) is a non-inverting SC integrators, and it can be analyzed with two consecutive half phase shown in Fig. 3.. When φ on, the charge conservation at node V can be expressed as [V i (n )] [ V out(n 3 ) + V out(n 3 )] = [ V out(n )] [ V out(n ) + V out(n )] (3.) Taking the z-transform, and assume the capacitors =, the overall transfer function can be expressed V out (z) V i (z) = z ( + ) ( + (3.) )z The inverting SC integrator shown in Fig.3. (b), also can be analyzed with two consecutive half phase shown in Fig When φ on, the charge conservation at node V can be expressed as [ V out(n 3 ) + V out(n 3 )] = [ V out(n ) + V i(n )] [ V out(n ) + V out(n )] (3.3)

34 Taking the z-transform, and assume the capacitors =, the overall transfer function can be expressed as V out (z) V i (z) = ( + ) ( + )z (3.4) From Eq.(3.) and Eq.(3.4), can find that the non-inverting and inverting SC integrator have the same pole error, which is proportional to /. The difference of them only a half of delay and phase shift by The transfer function also can derive from Eq.(.7), which combine the parasitical capacitor for more detail. Cs V in V - Vout Cs Figure 3.4: Non-inverting double-sampled SC integrator The SC integrator with double-sampled technique, which used to double the sampling rate is shown in Fig The non-inverting SC integrator can be analyzed with two consecutive half phase shown in Fig When φ on, the charge conservation at node V can be expressed as [V i(n )] [ V out(n ) + V out (n )] = [ V out(n )] [ V out(n ) + V out(n (3.5) )] Taking the z-transform, and assume the capacitors = =, the overall transfer function can be expressed V out (z) V i (z) = z ( + ) ( + )z (3.6)

35 Cs Cs Cf V in V - V out V in Cs V - V out Cs Cs (a) (b) Figure 3.5: Non-inverting double-sampled SC integrator during (a) φ and (b) φ Cs Cf V in V - Vout Cs Cf Figure 3.6: Non-inverting double-sampled SC integrator with two integration capacitors Cs Cf V in V - C f Vout V in Cs V - Vout Cf Cs Cs Cf (a) (b) Figure 3.7: Non-inverting double-sampled SC integrator with two integration capacitors during (a) φ and (b) φ 3

36 nother double-sampled SC integrator used two integration capacitors shown in Fig. 3.6 also can be analyzed with two consecutive half phase shown in Fig When φ on, the charge conservation at node V can be expressed as C s[v i (n )] C f[ V out(n 3 ) + V out(n 3 )] = C s [ V out(n )] C f [ V out(n ) + V out(n )] (3.7) Taking the z-transform, and assume the capacitors = = =, the overall transfer function can be expressed H(z) = V out(z) V i (z) = z ( + ) ( + (3.8) )z The DC magnitude at z = can be expressed H(z) z= = (3.9) The circuit shown in Fig.3.6 use two integration capacitors,, and two sampling capacitors, C s to integrate the input voltage. It has two paths to transfer the charge alternately, and each path works like the circuit shown in Fig.3. (a) do. From the transfer function of the SC integrator that discussed above shown in Eq.(3.) and Eq.(3.8), can find they are same. The only difference is Fig.3.6 integrated input voltage during both half phase. Compare to the another double-sampled SC integrator shown in Fig. 3.4, which use only one integration capacitor. The charge always transfer to the capacitor during both half phase, the Eq.(3.6) show a half of delay term. It is a key point when design a gain-compensated SC integrator. Because the topology of Fig.3.4 that use only one integrating capacitor will accumulate input voltage and gain error for two consecutive half phase. It will make the gain-compensated SC integrator cannot be realized, the reason will discussed more detail in next section. s we can see, the pole error of SC integrator with no compensation is proportion to /. In order to reduce the non-ideal effects, the way called gain-compensated technique will be introduced next. 3. Existed Gain-Compensated Integrators 3.. Introduction topology of SC integrator with gain compensation is proposed. It employs the same input as in the integrating phase during the calibration cycle to compensate for the integrating pole error due to the finite gain of op-amp. The SC integrator error can be classified by its 4

37 gain and pole errors. Capacitor mismatch causes the gain error while the finite op-amp gain causes the gain and pole errors. It is difficult to design an op-amp with both high gain and wide bandwidth, therefore the combination of gain-compensated and double-sampled technique will be attractive. In this section we will discuss a single-sampled gain-compensated technique first, then a double-sampled technique will be introduced. t last, a new single-sampled gaincompensated circuit is proposed. 3.. Single-Sampled Gain-Compensated Integrator V in V - V out Cs Cf Figure 3.8: Gain-compensated SC integrator with limit in input [] topology of SC integrator with gain compensation shows in Fig. 3.8 is proposed []. The output is valid during phase, and produce an output during phase equal to the output during phase. By maintaining an approximately constant output voltage from phase to phase, V = V out / remains nearly constant during phase and phase as desired. The circuit works well under the assumption that V in is approximately constant. First, we analysis how the circuit work, and discuss the limitation of V in. Then another topology that used to improve this topology will be introduced. Finally, make a comparison between of them. The topology that have effective high gain can be described as follow. The circuit can be analyzed with three half consecutive phase, form (n-3/) to (n-/). First, we assume the circuit start at φ (n-3/) shown in Fig. 3.9(a). During this phase, the circuit not only integrated the input voltage but also mix the error voltage that due to op-amp finite gain. The charge storage in the capacitors and, include the mixed error charge. The mixed error charge that due to the op-amp finite gain is V out (n 3/)/. Next, the circuit 5

38 Cf V in Cs V - (a) Cf V out V in Cs V - (b) V out Figure 3.9: The SC integrator during (a) phase and (b) phase switch to φ (n-) shown in Fig. 3.9(b). The capacitor C s = are used to cancel the input voltage that dump by at previous phase, also integrated the input voltage to output. There will be a problem here for input voltage limitation, and it will be discussed next. During this phase, the voltage V in (n ) and V out (n 3/)/ was integrated to the capacitor C f, where the second term V out (n 3/)/ was dumped by the capacitor. The capacitor C f now storage the previous and this moment input voltage and previous gain error. Then the capacitor will storage the voltage V out (n 3/)/ and V out (n )/ on it. t third phase, the circuit switch to φ (n /), the voltage storage on with V out (n )/ will be canceled by V out (n /)/, and only the term of V out (n 3/)/ preserve. The circuit works like to predict the error voltage and cancel it at next phase. This is how it have effective squared gain. Here shows the charge conservation at op-amp inverted input. First, when φ high, and φ low, the charge conservation at node V can be described as [ V out(n 3 ) + V in(n 3 )] C f[v out (n 3 )] = [ V out(n )] C s [ V out(n ) + V in (n )] C f [ V out(n ) + V out (n )] Second, when φ high, and φ low, the charge conservation at node V can be described as [ V out(n )] [ V out(n 3 ) + V out(n 3 )] (3.0) = [ V out(n ) + V in(n )] [ V out(n ) + V out(n )] (3.) Combining Eq.(3.0) and Eq.(3.) assuming that =, and taking the z-transform, the overall transfer function can be expressed H(z) = V out(z) V in (z) = ( + 4 )z + z [( + 4 )( + ) + ( + 3 )]z [( + 4 )( + )]z (3.) 6

39 The DC magnitude at z= can be expressed H(z) z= = (3.3) To show the disadvantage of slow moving of input show in Fig. 3.8, we first assume ideal switch and ideal op-amp here. The circuit can be analyzed over three consecutive half clock cycles shown in Fig On the last half cycle, phase, V in is integrated onto through to produce V out (n), and can be expressed as V out (n) = V out (n ) V in (n) (3.4) On phase at time (n /), dumps its charge V in (n ) to C f, also C s = inject a charge V in (n /) to C f. The total charge that transferred from C s and can be express Q total = Q Cs (n ) + Q Cs (n /) = V in (n ) V in (n /) (3.5) From Eq.(3.5) can find that V in (n ) V in (n /) is needed, and they are the reason why the input must be slow moving, it means that input must be approximately constant. To solve this disadvantage, another topology have been proposed [3] shown in Fig Fig.3. shows the circuit during φ and φ. It is assumed that the discrete time during φ is (n-/) and that during φ it is n. Thus, the discrete times associate with the previous φ and φ are (n-3/) and (n-), respectively. The charge conversion equation at node V can be described in three half cycle. V in V - V out Cf Cs Figure 3.0: Gain-compensated SC integrator with no limitation for input signal [3] 7

40 V in Cs V - (a) Cf V out Cs V - Cf (b) V out Figure 3.: The SC integrator during phase (a) φ and (b) φ First, when φ, high, and φ, low, the conversion at node V can be described as [V in (n 3 ) + V out(n 3 ) ] + C sv in (n 3 ) C fv out (n 3 ) = [V out(n ) + V out(n ) ] V out (n ) V out (n ) Second, when φ, high, and φ, low, the conversion at node V can be described as (3.6) [ V out(n 3 ) + V out (n 3 )] [ V out(n ) ] = [V in (n ) + V out(n ) ] [ V out(n ) + V out (n (3.7) )] Combining Eq.(3.6) and Eq.(3.7), and assuming the op-amp DC gain [5], the charge conservation equation of the V becomes V out (n )[ + + ] =V out (n 3 )[ + + f + C s )] C (C s V in (n (3.8) ) Taking the z-transform of Eq.(3.8), and assuming C s =, the approximated overall transfer function can be obtained as C f ( H(z) = + Cs ) (3.9) [ Cs ( + Cs )]z C f If = C s = = C f is assumed, Eq.(3.9) becomes H(z) = ( (3.0) )z Where the gain error is / and the pole error is /, the gain is enhanced significantly when compare to the DC gain of for simple integrator as shown in Fig..7. From analysis the 8

41 difference of them, we can find out the key point to design a SC integrator that insensitive to the finite gain of op-amp is the. When always connect at the inverted input of opamp, the voltage of V out / will be sampled at the during both phase. Then the term of V out (n /)( /) and V out (n 3/)( /) will be canceled as shown in Eq.(3.8). It is the reason why have effective finite gain, because only the term / will keep. The offset of the op-amp can also canceled by. The another advantage of Fig. 3.0 is the use of capacitor. The circuit use to sample the input first, and then compensate the voltage that dumped by at previous phase. It makes the disadvantage of slow moving will not happen. Here we use an ideal op-amp to construct the single-sampled integrator shown in Fig In order to test the function of the topology, a 0kHz sinusoidal signal with amplitude of mv is applied to the topology. The sampling frequency is 0MHz, and the gain of the amplifier is 40dB. Then the output magnitude and phase of an ideal inverting integrator is given by H(z) ideal = z = 59.5 e jπ f in fs (3.) H(z) ideal = 90 The output magnitude and phase of the integrator with no compensation shown in Fig. 3.(b) is given by H(z) no compensation = 84.3 ( + ) ( + )z (3.) H(z) no compensation Where is the op-amp finite gain. The output magnitude and the phase of the integrator with gain compensation that paper proposed shown in Fig. 3.0 is given by H(z) paper = ( 55.9 )z (3.3) H(z) paper 9 From Eq.(3.) and Eq.(3.3), can find the SC integrator with gain compensation is very close to ideal ones. The DC magnitude is effectively to /, and makes the op-amp more easier to design without high op-amp gain. The finite gain of op-amp not only reduce the magnitude of output signal but also cause a phase error. The simulation results shown in Fig. 3.3 and Fig. 3.4 are the output signal of the SC integrators for conventional ones with no compensation and paper proposed. The simulation results shown in Fig. 3.5 is an SC integrator with no compensation but constructed of a 80dB op-amp. The output voltage for a high gain op-amp will be more approximately to an ideal SC integrator. The frequency response of the op-amp with finite gain 40dB was shown in Fig

42 Figure 3.: The frequency response of the macro model op-amp with 40dB magnitude Figure 3.3: The output voltage of the SC integrator with no gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB 30

43 Figure 3.4: The output voltage of the SC integrator with gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB Figure 3.5: The output voltage of the SC integrator with no gain compensation, f in = 0kHz with amplitude mv, f s = 0MHz, and =80dB 3

44 The gain-compensated technology that we discussed above are single-sampled topology. It sampled the gain error during one half phase, then compensated it during next half phase. The another one was constructed with a double-sampled technology, which integrated the input voltage during both two half phase, but only one half phase has the gain compensation. Next, we will show a double-sampled gain-compensated SC integrator and find the trade off between both of them. Finally, we design a circuit which is the modification of the paper proposed, and make a comparison of them Double-Sampled Gain-Compensated Integrator topology of SC integrator shown in Fig. 3.6 that combine with the double-sampled technique, and gain compensation has been proposed. The output is valid during both two half phase, and effectively double the sampling rate. The primary difference between doublesampled and single-sampled integrator is the sampling phase. single-sampled SC integrator sample the gain errors only during one half phase, and then compensated it at next half phase. However, there is no additional phase for double-sampled SC integrator to use, because it integrated the input voltage at both two half phase. The circuit has two feedback capacitors and C f, two sampling capacitors and C s, one compensated capacitor C s, and was constructed C s Cs Cf Vin - V Vout Cs Cf C s Figure 3.6: Double-sampled and gain-compensated SC integrator with no limit to input [4] 3

45 in differential pair. It is not only reduced the odd harmonic effects, but also can use by C s to cancel the slow moving effect. There are some other properties for this topology, and can be analyzed from three half consecutive phase as shown in Fig To analyze more convenient, here we assume the capacitor number that connect at inverted input of op-amp during φ is α, during φ is β. C s Cs Cf Cs V in C s - V - V out Vin V Cf Vout C s Cf Cs Cf Cs C s (a) (b) Figure 3.7: Double-sampled and gain-compensated SC integrator with no limit to input during phase (a) φ and (b) φ First, when φ high and φ low, the charge conversion at node V can be described as [V in (n 3 ) + V out(n 3 ) = [ V out(n ) ] C s[ V out(n ) + V in (n )] C C f[ V out(n ) + V out (n )] ] [V out(n ) + V out(n ) ] + [V in(n 3 )] s [ V out(n ) ] Second, when φ high and φ low, the charge conversion at node V can be described as (3.4) [ V out(n ) = [V in (n ) + V out(n ) ] [V out (n 3 ) + V out(n 3) ] ] [V out (n ) + V out(n ) ] (3.5) 33

46 Combining Eq.(3.4) and Eq.(3.5), assuming that = = C s = =, the charge conservation equation of the V becomes V out (n )[ ] + V out(n 3 ) )[ (β ( β )(α + )( + )] + V in(n ) = V out (n )[( + α )( + β )( β )] + V in(n )[( α )( β )] (3.6) Taking the Z-transform of Eq.(3.6), the overall transfer function can be obtained as H(z) = V out(z) V in (z) = ( α )( ) z β z 3 ( ) + z [ (β ) ( )( α + )( + )] + [( + α)( + β )( )] β β (3.7) The DC gain at z= can be described as, and α β H(z) z= = ( β ) ( + α (3.8) α β From Fig. 3.7 can find that the number of capacitors at inverted input of op-amp during both β ) φ (α = 4) and φ (β = ), then substitute the value into Eq.(3.8), the DC magnitude at z= can be expressed as H(z) z= = + 5 (3.9) fter a careful analysis including the op-amp finite gain, here we assume = /µ, the integrator output voltage in the z-domain also can given by[4] Where assume = C s = C s, = C f and E(z) = V out (z) = H i (z)e(z)v in (z) (3.30) H i (z) = z (3.3) x + µ Cs z x( + µ) + z [xµ Cs (µ Cs ) z ( + µ)µ Cs z 3 ] (3.3) x = + µ + 3µ (3.33) H i (z) represents the ideal transfer function of a SC integrator, and E(z) gives an estimation of the transfer-function deviation caused by the op-amp finite gain. The error function magnitude was computed as E. Here we use a SC integrator with no compensation shown in Fig..7, and compare to the circuit shown in Fig The gain errors are in the order of / for compensated topology, but/ for non-compensated topology. s Fig.3.8 demonstrates, the compensated topology has better magnitude accuracy. 34

47 0 0 SC Integrator With No Gain Compensation ( E ) Double Sampled Gain Compensated SC Integrator ( E ) 0 Magnitude Error (db) Op mp DC Gain Figure 3.8: Magnitude errors of the integrator for =, f in = 0kHz, and f s = 0MHz The circuit has twice sampling rate, equivalent high op-amp gain, and no limitation to input signal for slow moving. But there is a disadvantage for op-amp offset voltage, and cannot be canceled. To know how this happen, we can see the capacitors C s and C s shown in Fig During phase φ the right hand side of capacitor connected at inverted input of op-amp, C s short to ground at two side, and C s connect at the inverted input with its left hand side. During phase φ the right hand side of capacitor still connected at inverted input of op-amp, and the offset voltage that storage on the capacitor during previous phase will be canceled. The capacitor C s integrated to the output. The capacitor C s connect to the inverted input of op-amp, and the offset now connect to the inverted input of op-amp with its right hand side to compensate the input voltage that dump by the at previous phase, it also integrated the offset voltage to the output. We can find that the offset voltage will be integrated due to the capacitor C s and C s. If we assume that the offset voltage shows in Fig..4 is mv, it means the mv will be integrated to the output during φ in this topology. One reason that cause the offset voltage is the capacitor not always connect at op-amp inverted input shown in Fig Is it possible to reduce or cancel the offset voltage, and also have gain-compensated effect. In next section we will alter the topology of Fig. 3.6, and explain the trade off between offset voltage, input limitation, gain-compensation, and doublesampled technique. 35

48 3..4 The Modification of Double-Sampled Gain-Compensated SC Integrators In this section, we will vary the circuit of Fig.3.6 and discuss the restrictions when design a double-sampled gain-compensated SC integrator. The modification circuit shown in Fig. 3.9 have two integrating capacitors, two sampling capacitors and three compensated capacitors. There are three steps to design the circuit and we can find out the trade off between offset voltage, input limitation, and gain compensation. + V in - V in Cs Cs V - Cf V out - V in - V in + V in C s C a C b - V - V - V - V + V in + V in - V in C s C a C b + V + V + V + V Cf Figure 3.9: The vary double-sampled and gain-compensated SC with no limit to input + V in - V in C b Cs C a C s C s C a Cs Cs V - Cf V out Cf + V in - V in C b C s C s C b C a Ca Cs Cs V - Cf Cf Cf Vout C b (a) (b) Figure 3.0: The vary double-sampled and gain-compensated SC with no limit to input during (a) φ and φ 36

49 s we can see from Fig. 3.6, the sampling capacitor not always connect at the inverted input of op-amp. It causes the offset voltage cannot be canceled and will integrate to the output. To improve this condition, first, we vary the capacitor and always connect at the inverted input of op-amp shown in Fig. 3.9 to cancel the offset voltage. But now the previous input voltage would be dumped by and C s at next phase. In order to solve this problem, second, we use the capacitors C s and C a to cancel the previous input voltage that dumped by and C s. But now the capacitor C a sample the negative input voltage, it will make the integrator have no input voltage can integrated to output during φ. In order to solve this problem, third, we use the capacitor C b connect to the positive input. There are three steps for us to construct the topology. The capacitors we discuss above are all upper half of the differential pair circuit show in Fig We can find that during each phase, the capacitors are used to solve different problems that cause by the other capacitors. Then, let we check if the offset voltage can be reduced or canceled now. The capacitors and C s shown in Fig. 3.9 will not integrate the offset voltage during each consecutive half phase, because they always connect at the inverted input of op-amp. However, the capacitor C b and C s will contribute a offset voltage now. Compare to the Fig. 3.6 that the offset voltage was caused of the capacitors C s and C s. We can find that the offset voltage still cannot reduced. How about the finite gain in this topology. It can be described with the same way shown in Eq.(3.4) Eq.(3.6). The DC magnitude of this topology can be expressed from Eq.(3.8). Here we assume the capacitors C a = C b = = = C s = =. Substitute α = 6 and β = 4 into Eq.(3.8), the DC magnitude can be expressed H(z) z= = (3.34) s we can see, the performance of the effective finite gain is inferior to Fig To make the effective gain better, here we adjust the size of the capacitors C a and. The capacitors size can be expressed C b = = C s = = C f = C and C a = C s = κc where 0 κ. It will not influence the original integrator function when adjust the size of the capacitors C a and C s, because the input voltage that integrated by C a and are canceled by each other. The input voltage only integrated by C b, during φ, and integrated by, C f during φ. The analysis of this circuit is also the same, and can substitute the value of capacitor number into α and β shown in Eq.(3.8). However the value of α and β should consider of the coefficient κ. In this topology, the coefficients α and β can be expressed as α = 4 + κ β = + κ (3.35) 37

50 Here we make a comparison between the circuit that has been modified by us shown in Fig. 3.9, and paper proposed shown in Fig From the result shown in Fig. 3. can find that the magnitude of the gain errors are proportional to the coefficient κ. We can find that the magnitude for both two circuits are very approximate, when κ is smaller than /8. The derivation of Eq.(3.4) and Eq.(3.5) describe the charge conservation at inverted input of opamp. We can find that the gain errors due to op-amp finite gain are attenuated during three half consecutive phase. There is only one integration capacitor can integrate the input voltage more accuracy, the another one is inferior corresponsively. Because the circuit need to sample the previous gain errors first and then cancel it at next phase. The two topologies all have at least one sampling capacitor always connect at the op-amp inverted input. It makes the gain errors can be stored and then compensated at next half phase. The effective finite gain of the SC integrator is enhanced, because it reduce the gain error at inverted input, and the charge can transferred to the output more accuracy. In order to show how this work, we use an op-amp macro model with several finite gains to construct the two topology and simulate it by HSPICE. 0 0 Modification SC Integrator ( E, k=/) Modification SC Integrator ( E, k=/8) Paper Proposed SC Integrator ( E, k=0) 0 Magnitude Error (db) Op mp DC Gain Figure 3.: The comparison of gain errors between paper proposed and we proposed for κc a = C b = = κc s = C s = = C f, f in = 0kHz, and f s = 0MHz 38

51 In order to test the function of an integrator, a 0kHz sinusoidal signal with amplitude of mv is applied to the integrator. To see the gain-compensated effect more clear, here we assume the gain is small. The sampling frequency is 0MHz, and the gain of operational amplifier is 40dB. The magnitude of an ideal non-inverting integrator is given by f in fs z / H(z) ideal = z = e jπ = 59.5 e jπ f in fs (3.36) H(z) ideal 90 The magnitude of an integrator with no compensation shown in Fig. 3.6 is given by, where is the op-amp finite gain z / H(z) no compensation = 84.3 ( + ) ( + )z (3.37) H(z) no compensation 3.53 The magnitude of the inverting integrator that paper proposed shown in Fig. 3.6 is given by, where α = 4, β = ( α H(z) paper = )( ) z β z 3 ( ) + z [ (β ) ( )( α + )( + )] + [( + α)( + β )( )] β β 56.7 H(z) paper 9.89 (3.38) The magnitude of the inverting integrator that we proposed shown in Fig. 3.9 is also can given by Eq.(3.38), where α = 4 8, β = 8 ( α H(z) alter = )( ) z β z 3 ( ) + z [ (β ) ( )( α + )( + )] + [( + α)( + β )( )] β β 56.3 (3.39) From the simulation results shown in Fig. 3.8 and Fig. 3.9, can find that the charge on the capacitors and C f are different, it verify the inequality that we derive above. The gain-compensated situation only occurred during one half phase, the another half phase has no compensation. The double-sampled technique integrated the input voltage during both two half phase, so the sampling rate is twice as fast as the single-sampled technique. The effective DC gain is proportional to /. It makes the op-amp don t need to be designed to a very high gain and also can reduce the power consumption. 39

52 Figure 3.: The output voltage for a non-inverting SC integrator with no compensation shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB Figure 3.3: The transferred charge on the integration capacitor, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB shown in Fig. 3.6, 40

53 Figure 3.4: The output voltage for a SC integrator that paper proposed shown in Fig. 3.6, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB Figure 3.5: The transferred charge on the integration capacitor, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB shown in Fig. 3.6, 4

54 Figure 3.6: The output voltage for a SC integrator shown in Fig. 3.9, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB Figure 3.7: The transferred charge on the integration capacitor, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =40dB shown in Fig. 3.9, 4

55 Figure 3.8: The transferred charge on the integration capacitor, shown in Fig. 3.9, k=/8, f in = 0kHz with amplitude mv, f s = 0MHz, and =0dB Figure 3.9: The transferred charge on the integration capacitor, f in = 0kHz with amplitude mv, f s = 0MHz, and =0dB shown in Fig. 3.6, 43

56 The simulation result shown in Fig. 3. is the output voltage of a double-sampled SC integrator with no gain compensation. It shows the magnitude for a sinusoidal input, and was derived by Eq.(3.37) that combined with a term of. Compared the Fig. 3.4 with Fig. 3.6, which are the simulation results for a gain-compensated SC integrator that paper proposed and it s modification that we proposed. We can find the accuracy for those two circuits are very approximate. It also can derived from Eq.(3.38) and Eq.(3.39) independently, that combine with a term of. The charge transferred form sampling capacitor to the integrating capacitor was restricted by the op-amp finite gain. Here we reduce the op-amp finite gain to 0dB to see the difference of the charge that transferred between sampling and integrating capacitors shown in Fig. 3.8 and Fig The integrating capacitor that during compensated half phase have higher amplitude. Because it reduce the error voltage due to op-amp finite gain to V out /, then the stored charge on sampling capacitor can transferred to integrating capacitor more accuracy. However, the another one half phase don t have gain compensation, because it was used to sample the errors. This is why only a half of phase can compensated the gain errors. s we can see, when the gain of op-amp is higher the charge during the two integrating paths will more closer shown in Fig. 3.5 and Fig The double-sampled gain-compensated SC integrators have the trade off between offset voltage and gain compensation, because it only have a half of phase to cancel the offset, however the input voltage always integrated at both two half phase. lthough the double-sampled SC integrator cannot cancel the offset voltage completely, but it can use other auxiliary circuits to accomplish this purpose. There are some ways to reduce the offset voltage, which can be digital [5], or analog circuits [5]. Those circuits were proposed by papers and let the double-sampled gain-compensated technique can solve this problem more easier. The way that used to cancel the offset voltage, and reduce the flicker noise can be classified into two type. First, is the correlated double sampling(cds) technique. Second, is the CHopper Stabilization(CHS) technique. The way that we use can be generalized to CDS, which can enhance the op-amp finite gain effectively. The another way of CHS technique can also makes offset voltage does not count anymore and flicker noise impact is highly reduced. But the disadvantage is that the effective gain is usually reduced[7], and usually used in continuous time system. The double-sampled gain-compensated technique is very useful and attractive in the application that need high gain and wide bandwidth. 44

57 3.3 New Single-Sampled Gain-Compensated SC Integrator R R C c f C c Vin Vout C c f C c R R Figure 3.30: new single-sampled gain-compensated SC integrator The single-sampled and double-sampled gain-compensated SC integrators have been discussed above. In this section we proposed a new topology shown in Fig that use an additional op-amp and two compensated capacitors C c and C c to cancel the gain errors. The DC magnitude of the topology is ideally infinite, and can be described as follow. The circuit can be analyzed with three half consecutive phase, from (n 3/) to (n /). First, we assume the circuit start at the phase φ (n 3/) shown in Fig. 3.3(a). During this phase, the circuit integrated the input voltage to the output, and the errors due to op-amp finite gain also stored in the capacitors C c and C c. The charge in the C c is three times of the charge in the C c, because it was amplified by a feedback non-inverting op-amp. Next, the circuit switch to the phase φ (n ) shown in Fig. 3.3(b), the capacitors C c and C c are connect together, and the charge that have been stored during previous phase will make an average now. During third phase, the capacitor C c will connect to the op-amp input and cancel the errors due to op-amp finite gain, then the input voltage can transferred to the capacitor completely. The gain errors in this topology is ideally zero. Here we will derive the charge conservation at op-amp inverted input. 45

58 K C c - V C c C c - V C c C c V out Vin Vout C c C c C c K (a) (b) Figure 3.3: single-sampled gain-compensated SC integrator during (a) phase (b) phase First, when φ high, φ low, the charge on the capacitor C c can be described as Q Cc (n 3 ) = C c[ V out(n 3 )] KC c[ V out(n 3 )] (3.40) Where K is the closed loop gain of the feedback op-amp, and is the op-amp finite gain. Second, when φ high, φ low, the charge conservation at node V can be described as [ V out(n 3 ) + V out(n 3 )] [V in (n )] + Q Cc (n 3 ) = [ V out(n ) + V out(n )] [ V out(n )] C c[ V out(n )] (3.4) Combining Eq.(3.40) and Eq.(3.4), and taking the z-transform, the overall transfer function can be expressed as H(z) = V out(z) V in (z) = z [ C f + C c + C s + ] [ C f + (C c + KC c ) + ]z ssuming C c = C c = =, K=3, then the DC magnitude at z= can be expressed as (3.4) H(z) z= = (3.43) Form Eq.(3.43) can find that the topology have infinite DC magnitude and have no pole error. It works like an ideal SC integrator under the assumption that the feedback op-amp can amplify the input voltage by a factor of three exactly. Here we use an macro op-amp model to construct the topology shown in Fig Then an real op-amp will substitute for the macro model, and the simulation results will also discussed in next chapter. 46

59 X β Y Figure 3.3: simple feedback system In order to test the function of the topology, a 0kHz sinusoidal signal with amplitude of mv is applied to the topology. The sampling frequency is 0MHz, and the gain of the amplifier is 40dB. Then the output magnitude and phase of the topology is given by z / H(z) propose = ( + 3 ) z ( ) (3.44) H(z) propose 90 Where the gain error is 3/ and pole error is zero. The simulation result shown in Fig is the output voltage of the topology. Compare to the circuit shown in Fig. 3.0, the phase error of the output signal was improved. The transfer function with no pole error is very attractive for the delta sigma modulator with MSH structure. The difficult of this topology is need to make the feedback op-amp can amplify the error voltage by a factor of three exactly. However, it is not difficult to have a precision value of a factor of three, because of the gain desensitization. It can be described as [6] Y X = + β β ( β ) (3.45) Where β was called the loop gain, which plays an important role in feedback system. We see from Eq.(3.45) the higher β is the less sensitive Y/X will be to variations in shown in Fig Here we take an example of the feedback system. ssuming the feedback factor β of the feedback amplifier is / and op-amp finite gain is 70dB. Then the gain error /(β) can be reduced to about 0.063%. The topology of the feedback op-amp is a single-end foldedcascode amplifier, and it can be designed to have a high gain. The DC magnitude of Eq.(3.43) with a finite gain feedback op-amp can be described as H(z) z= = z ( + 3 ) z ( + K+3 ) z= = Where the closed loop gain of the feedback op-amp can given by 3 K (3.46) K = X Y = f + f 3 (3.47) 47

60 Combining Eq.(3.46) and Eq.(3.47), the DC magnitude can be described as H(z) z= = (3 + f) 9 (3.48) Where f is the feedback op-amp finite gain shown in Fig From Eq.(3.48) we can find that the effective finite gain is the multiplication of the two opamps, and f. The conventional gain-compensated integrator used itself amplifier to achieve the effective gain of. However, this topology shown in Fig used an additional feedback amplifier to get the effective gain of f. The feedback amplifier was constructed of singleend topology, and can be achieve high gain easily. s we know, a traditional SC integrator was constructed with a single amplifier and sampling capacitors and integrating capacitors. If it was a gain-compensated topology, there will have additional compensation capacitors. The primary op-amp in the SC integrator need to deal with the input signal, and should be designed with high gain and wide bandwidth. However, there is a trade off when design a high gain and wide bandwidth amplifier. In this topology, we can design the primary amplifier for lower gain, and the feedback amplifier to have higher gain. lthough the traditional gain-compensated SC integrator and the topology that we proposed are both can get a high effective gain of op-amp. However, the topology that used an auxiliary feedback amplifier is more attractive, because it can enhance the SC integrator DC gain with an additional op-amp and the whole circuit with no stable problem. fter a careful analysis including the op-amp finite gain, here we describe the gain error of this circuitry. The output voltage in the z-domain can given by V out (z) = H i (z)e(z)v i (z) (3.49) Where H i (z) is the ideal transfer function, E(z) is the error transfer function, and is given by H i (z) = E(z) = z z z ( + 3 ) z ( + K+3) (3.50) The error function magnitudes was computed as E. Here we use a SC integrator with no compensation to compare with this topology and shown in Fig s it demonstrates, the gain-compensated topology has better magnitude accuracy. 48

61 Figure 3.33: The output voltage for a SC integrator shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =40dB, and f = 80dB 0 SC Integrator With No Gain Compensation ( E ) Single sampled Gain Compensated SC Integrator ( E ) 0 Magnitude Error (db) Op mp DC Gain Figure 3.34: Magnitude errors of the integrator for = = C c = C c, f in = 0kHz, and f s = 0MHz 49

62 The error transfer function of Eq. (3.50) can also be described as E(z) = + 3 z ( z ) 9+6f + (3+ f ) + 3 = + 3 ( z ) z ( E pole ) (3.5) Where the pole error of Eq. (3.5) is given by E pole = 3 9+6f 6+ f + 3 = 9 ( + 3)( f + 6) (3.5) Compare to the conventional single-sampled gain-compensated integrator shown in Fig. 3.0, where the pole error is. The pole error of Eq. (3.5) is inverse proportional to the gain of f. The comparison between both the two topology is shown in Fig. 3.35, the pole error can be reduced by increasing a feedback amplifier. It is very useful on the application of sigma delta modulator with MSH structure. 0 0 Pole Error of Conventional Gain Compensated Integrator Pole Error of New Gain Compensated Integrator (f = 66dB) Pole Error of New Gain Compensated Integrator (f = 69dB) 0 Magnitude of Pole Error (db) Op mp DC Gain Figure 3.35: Magnitude of pole errors for conventional circuit and new gain-compensated topology 50

63 3.4 Simulation nd Results In order to construct the new topology of Fig. 3.30, here we use a folded-cascode fully differential amplifier with a gain 50dB to substitute the op-amp on the signal path. The feedback amplifier was constructed with a current feedback single-end amplifier. This type have high gain and high speed. One of this op-amp s advantages is its closed-loop gain can be changed, when used in the feedback application, without significantly affecting its loop gain [4]. dditionally, this current feedback op-amp use of an output buffer for resistive feedback network. Here, we construct it with a gain of 60dB. The sampling and integrating capacitors are all pf. ll of the switches would be realized by n-channel transistors only, expect for the switches connected to the outputs, which was realized by transmission gate to accommodate a wider signal swing. The resistance of the transmission gate is about 800Ω. In order to test the topology, we give a sinusoidal input with different frequency, then examine the output signal. The ratio of input signal frequency over sampling frequency, OSR, should be selected advisably to prevent the op-amp s output swing distortion. Here, the sampling frequency is 0MHz and the input frequency is 0KHz or even larger. The results were verified by simulation results, and used TSMtandard 0.35µm CMOS technology to implement Operational mplifier nd Common Mode Feedback The fully differential analog circuits are used throughout the modulators for two reasons. First, a fully differential topology provides for high rejection of common-mode disturbances, such as common-voltage offset, supply and substrate noise. Second, for a given voltage range, a differential signal has twice the amplitude of a single-ended signal. fully differential folded-cascode operational amplifier shown in Fig The output swing of this amplifier can be greater than a direct stack of transistors. The output swing of the op-amp is determined by the cascode NMOS, M 7 and M 8, and by the cascode PMOS, M 9 and M 0. For proper operation, all transistors should be operating in a saturation region. The new gain-compensated SC integrator operate in 0MHz sampling frequency. To make sure it has enough settling time for % accuracy. From Eq. (.9) we can know the op-amp should have at least 60MHz unit-gain-bandwidth (UGB) where β = /3. The op-amp also need a common-mode feedback, a constant current bias circuit, and they will also be discussed at next. From MOS current equation, the overdrive voltage can given by 5

64 V DD V bp M 4 M M V bp + V in M 3 M M - V in M9 M0 - V out + V out M 7 V bn M 8 Vcm C C C C Vcm V ctr Vbn Vbn M 5 M 6 V SS Figure 3.36: fully differential folded-cascode operational amplifier with common-mode feedback I D = µc OX W L (V GS V t ) = µc OX V DS,sat = I D L µc OX W W L V DS,sat (3.53) The cascode devices operated in the saturation region limit the output swing of the op-amp. given by (3.54) From Fig.3.36 can derive small-signal parameters of the op-amp. The output impedance is R out [g m8 r o8 (r o //r o6 )]//[g m0 r o0 r o ] (3.55) The open loop gain is given by = g m R out (3.56) If the second pole is behind of the unity-gain frequency, then the unit-gain-bandwidth of the amplifier is derived by (s) = g m (R out // sc L ) g m sc L = (3.57) 5

65 ω UGB = g m C L (3.58) Where C L is the op-amp output load capacitance, ω UGB is the unit-gain-bandwidth. The load capacitance will create a dominant pole at a frequency ω UGB = g m C L = g m R out ω p (3.59) ω p = Where ω p is the op-amp dominant pole frequency. R out C L (3.60) For better speed, N-channel devices should be chosen for the input pair, because of their higher mobility. Since the unit-gain-bandwidth of the op-amp is determined by the ratio of the transconductance of the input device to the output load capacitance. But the P-channel devices have better noise performance. Typically, P-channel transistors have less flicker noise than N-channel transistors. In CMOS P-substrate fabrication, P-channel transistors are isolated substrate-noise by n-well protection. For low noise and high accuracy consideration, we choose P-channel transistors as input devices. The mobility of the input devices can be compensated by increasing the width of the PMOS. The flicker noise is inversely proportional to the transistor area, (W L) [6]. The PMOS has less flicker noise than NMOS, if they have the same mobility. Here we choose the PMOS transistor as the input devices of op-amp. From Eq.(3.58) can find that the op-amp could be made fast by increasing the width and bias current of the input devices. However, to maintain stability, all concomitant poles must occur at the frequencies higher than the unit-gain-bandwidth of the op-amp. Therefore, the speed of op-amp is limited by the location of the first non-dominant pole. The pole is given by ω p = g m8 8 (3.6) It is the ratio of the transconductance of the cascode N-channel devices to the total capacitance on its source. The non-dominant-pole frequency can be increased by increasing the current density through the cascode device M 8. The common mode output level of the amplifier is maintained by the Seedback circuitry also shown in Fig The common-mode feedback (CMFB) circuit is based on the use of SC circuits. In this approach, capacitor C generate the average of the output voltage, which is used to create control voltage for the op-amp output current sources, M 5 and M 6. This circuit acts like a simple SC low-pass filter having a DC input signal. The bias voltage is designed to be equal to the difference between the desired common-mode voltage, V cm, and the desire control voltage, V ctr used for the op-amp current source. The capacitor C form a voltage divider to 53

66 V DD V bp M 8 M 7 M V bp M9 M 6 M0 M 4 V SS M 8 V bn M 3 M4 M 5 M3 M5 M6 V bn M M M M 7 R b Bias Loop V SS Cascode Bias Strat-up Figure 3.37: wide-swing constant transconductance bias circuit drive node V ctr, the gates of the NMOS current source transistors in the output stage. If the voltage V + out and V out raise, the V ctr also raise to keep the charge of C at the same time. It increase the NMOS current source and reduce the output common mode voltage. The bias circuit of the op-amp is implemented by incorporating wide-swing current mirrors into the constant-transconductance bias is shown in Fig The circuit includes wide swing cascode current mirrors, stable transconductance bias circuit, and a start-up circuit [4]. The bias circuit is presently becoming the most popular CMOS bias circuit. The stable transconductance bias is provided by the resistor R b and transistors M, M in the bias loop shown in Fig If (W/L) 7 and (W/L) 8 is the same. The equality results M and M of the circuit having the same current due to the current mirror pair M 7, M 8. The loop consisting of M, M and R b, can obtain V GS = V GS + I D R b (3.6) 54

67 Subtract the threshold voltage V t from both sides can get V GS V t = V GS V t + I D R b (3.63) The Eq.(3.63) can be rewritten as I D I D = + I D R b (3.64) µ n C ox (W/L) µ n C ox (W/L) Since I D =I D, Eq.(3.64) can also be written as We also know that µn C ox (W/L) I D ( From Eq.(3.65) and Eq.(3.66), can obtain (W/L) (W/L) ) = R b (3.65) g m = µ n C ox (W/L) I D (3.66) g m = R b ( (W/L) (W/L) ) (3.67) The transconductance of M is determined by the ratio of M and M size only. It is independent of power supply voltage, process parameter, temperature, or any other parameters with large variation. For special case of (W/L) = 4(W/L), can simplified Eq.(3.67) as g m = R b (3.68) The circuit is necessary to add a start-up circuit that only affects the operation if all the currents are zero at start up. The start-up circuit consists of transistors M 5, M 6, M 7, and M 8. In the state that all currents in the bias loop and cascode bias are zero, the gate voltage of M 7 would close to V ss, and M 7 would be turn off. We assume the aspect ratio (W/L) 8 is very small, so the output impedance of M 8 would be very large. Since the M 8 operates as a high-impedance load is always on. The gates voltage of M 5 and M 6 would be pulled up. The transistors M 5 and M 6 will inject currents into M 9 and M 4, respectively, which will start up the bias loop. Once the loop start up, the bias voltages, V bp, V bp, V bn, and V bn, would settle to a stable state, then M 7 would turn on and sinking all the current from M 8. Then M 8 operates in the saturation region and M 7 operates in the triode region. This pull down the gate voltage of M 5 and M 6 and thereby turns them off so no longer affect the bias circuit. The frequency response of the fully differential folded-cascode op-amp simulated by HSPICE is shown in Fig The transient response of the bias circuit is shown in Fig. 3.39, and it start up at t=00 ns. Then the simulated performance is summarized in Table

68 ( a) ( b) Figure 3.38: The frequency response of the fully differential folded-cascode amplifier (a) 50dB magnitude (b) 88 phase margin Figure 3.39: Simulation of bias output voltage 56

69 DC Gain 50 db Load pf Phase Margin 88 Unit-gain Frequency 63. MHz Slew rate 3.9 V/µs Power. mw Supply Voltage 3.3 V Process 0.35 µm P 4M Table 3.: Simulated summary of the fully differential folded-cascode amplifier Single-End Op-mp V DD M 4 V bp M M M 3 V bp V bn M9 M0 M 5 M 3 + V in M M - V in M 4 C C V out M 6 V bn M 7 M8 V bn M 5 M 6 V SS Figure 3.40: Single-end folded-cascode op-amp with output buffer single-end op-amp shown in Fig with buffer circuit is used to isolate the op-amp from the load. The load can be resistive, capacitive or a combination of the two. Capacitor C c is used to compensated the circuit with a technique called Miller compensation. However, it will cause a zero at right-hand plane, and the stability degrades considerably. The gate-drain connected MOSFETs M3 and M4 can be though of as zero-canceling resistors, which used to shift the right-hand plane zero into the left-hand plane []. The current through M3 and M4 is well defined, and increase the lengths of them can push the zero further into the left-half plane. Normally, since the gain of the output buffer can be low, the output MOSFETs, M5 and M6, can be sized with minimum or near-minimums lengths. The frequency response shown in FIg. 3.4 has 60 db magnitude and 84 phase margin. 57

70 ( a) (b) Figure 3.4: The frequency response of a single-end folded-cascode op-amp (a) 60dB magnitude (b) 84 phase margin 3.4. Switch The speed of the sampling circuit is an important factor to influence the harmonic distortions of the integrator. Since the output voltage of the sampling circuit speed would take infinite time to become equal V in. We consider the output voltage V out settled when it is within a certain error band, V, around the final value. Thus, the speed specification must be accompanied by an accuracy specification as well. The source and drain voltages to be approximately equal after switch turns on t s seconds shown in Fig The speed of a sampling circuit is given by two factors, the on-resistance of the switch and the sampling capacitor. In order to achieve higher speed, a large W/L and small capacitor should be used. However, the on-resistance depends on the input level shown in Fig In the case of NMOS switch, the time constant is proportional to the increasing positive input voltage. In Fig. 3.4, for V out V in, the transistor must operate in deep triode region and hence the upper bound of V in equals V DD V t. Thus, we can obtain the on-resistance V ds I d = R on,n = W µ n C ox (V L gs V tn ) = W µ n C ox (V L DD V in V tn ) (3.69) 58

71 V ctrl V ctrl V DD V in V out 0 t V out V in ΔV 0 t s t Figure 3.4: Definition of speed in a sampling circuit for NMOS switch The on-resistance of the switch shown in Fig as a function of the input level. In the figure, for a NMOS switch, the sharp rise as V in approaches V DD V t. The device threshold voltage directly limits the input voltage swings. In order to accommodate greater voltage swings in the sampling circuit, we can observe a PMOS switch exhibits a on-resistance that decrease as the input voltage becomes more positive. Then, it is reasonable to employ a transmission gate shown in Fig.3.43 as the sampling switch at the input of integrators. The transmission gate allows rail-to-rail swings, and produce an equivalent resistance which can be described as R on,eq =R on,n R on,p = µ n C ox ( W ) L n(v DD V in V tn ) µ p C ox ( W ) L p(v in V tp ) = µ n C ox ( W ) L n(v DD V tn ) [µ n C ox ( W ) L n µ p C ox ( W ) L p]v in µ n C ox ( W ) L pv tp From Eq.(3.7), if (3.70) µ n C ox ( W L ) n = µ p C ox ( W L ) p (3.7) The R on,eq is independent to the input signal level. The turn on resistance of the transmission gate is shown in Fig. 3.44, it has less variation than the corresponding to only a NMOS or PMOS switch alone. In order to prevent the incomplete settling noise in the integrator, the sampling and integrating times of the integrator should be at least five times the RC time constant for a % accuracy shown in Fig It can express as, T s is sampling period R on,eq < 5 (T s ) (3.7) 59

72 V ctrl V out V in ΔV Vin Vout 0 t s t V ctrl V ctrl V DD 0 t Figure 3.43: Definition of speed in a sampling circuit for Transmission gate Figure 3.44: Comparison of on-resistance of switch Simulations Of New Single-End Gain-Compensated Integrator In order to test the new SC integrator, a 0kHz sinusoidal signal with amplitude of mv is applied to the topology, and the sampling frequency is 0MHz. The Fig Fig show its output voltage with different input frequency. The Fig and Fig show a conventional non-inverting SC integrator with no compensation to make a comparison with the new topology. The Fig is the post layout simulation with 0KHz input frequency, and is approximate to the pre-simulation shown in Fig The Fig shows a comparison between real circuit and ideal one, and the results also conform to the specifications. 60

73 Figure 3.45: The output voltage for a SC integrator with no compensation shown in Fig. 3.(a), f in = 0kHz with amplitude mv, f s = 0MHz, and =50dB Figure 3.46: The FFT of the output voltage for a SC integrator with no compensation shown in Fig. 3.(a), f in = 0kHz with amplitude mv, f s = 0MHz, and =50dB 6

74 Figure 3.47: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB Figure 3.48: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB 6

75 Figure 3.49: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB Figure 3.50: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB 63

76 Figure 3.5: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 30kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB Figure 3.5: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, f in = 30kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB 64

77 Figure 3.53: The post simulation for a SC integrator that we proposed, f in = 0kHz with amplitude mv, f s = 0MHz, =50dB, and f = 60dB The Magnification of Math Derivation The Magnification of HSPICE Simulation 0 Magnitude Input Frequency (Hz) x 0 4 Figure 3.54: The magnification for a SC integrator that we proposed by varying the input frequency shown in Fig. 3.30, with amplitude mv, f s = 0MHz, =50dB, and f = 60dB 65

78 Figure 3.55: Layout photo of the new gain-compensated switched capacitor integrator 66