DØ Run IIb L1Cal Overview (the stuff you already know)

Transcription

1 DØ Run IIb LCal Overview (the stuff you already know) Hal Evans Columbia University Why Give This Talk?. Recall Problems & Solutions 2. Reminder of System Architecture & Confusing Acronyms 3. Overview of Issues to Discuss During the Meeting 4. Remember Constraints: Cost & Schedule H.Evans Saclay Trigger Workshop: 5-Nov-02

2 Seizing the Moment The Higgs is w/in our grasp! If enough luminosity (~5 fb - ) performant detector (b-tag) strong trigger leptons, b-jets, taus, Et-miss Trig eff assumed for Higgs Lepton 00% Jet+Met 00% And don t forget other physics Tevatron plans Scheme baseline no L level still alive Lumi (x0 32 cm -2 s - ) BC [ns] <N int > L Level yes no no DØ Changes Integ Lumi New Si Inst Lumi Upgr Trigger Focus on High Pt Phys frees trig bandwidth but not enough H.Evans Saclay Trigger Workshop: 5-Nov-02 2

3 LCal is the Key L Calorimeter Trigger is the primary mechanism for collecting: e/γ, Jets, Invisible Particles (ME T ) Physics Electro-Weak Sample Channels W lν / Z l + l Cal Triggers EM, ME T Top Higgs New Phenomena t t lν + jets tt all jets Z bb WH lνbb ZH ννbb (*) H W W ~ ± χ ~ 0 χ ~ χlν ~ χl l ~ + 0 t bw ~ χ G KK γγ EM, Jet (calibrate E-scale) EM, Jet, ME T EM, Jet, ME T H.Evans Saclay Trigger Workshop: 5-Nov-02 3

4 But there are Problems 396 ns LCal Signals 32 ns EM TT Signal Signal Shape Rise Time > 32 ns not entirely understood dispersion in cables? can cross threshold before peak Trigger on Wrong Crossing affects interesting high-e events Note: this is only an issue at 32 ns BC Solution Advantages Digital Filtering of BLS of input signals more flexible than analog shaping Baseline: Match Filt. + Peak Det. allows running at 32 ns tunable response improved energy resolution H.Evans Saclay Trigger Workshop: 5-Nov-02 4

5 and More Problems Trigger Run IIa Definition Example Channel L Rate [khz] (no upgrade) Core Trigger Menu EM DiEM Muon EM TT > 0 GeV EM TT > 7 GeV 2 EM TT > 5 GeV Mu Pt > GeV CFT Track W ev WH evjj Z ee ZH eejj W µv WH µvjj L = 2x0 32 cm -2 s - BC = 396 ns Total L Bandwidth Limit = 5 khz Di-Mu e + Jets 2 Mu Pt > 3 GeV CFT Tracks EM TT > 7 GeV 2 Had TT > 5 GeV Z/ψ µµ ZH µµjj WH evjj tt ev+jets Solution (LCal) Better Algorithms Jet, EM, Tau Mu + Jet Jet+MEt Mu+EM Iso Trk Mu Pt > 3 GeV Had TT > 5 GeV 2 TT > 5 GeV MEt > 0 GeV Mu Pt > 3 GeV + Trk EM TT > 5 GeV Iso Trk Pt > 0 GeV WH µvjj tt µv+jets ZH vvbb H WW,ZZ H ττ, W µv <0. 2. <0. 7 Clustering similar to what is done at L2 now Implies that L2 must improve as well Di-Trk Total Rate Iso Trk Pt > 0 GeV 2 Trk Pt > 5 GeV Trk matched w/ EM H ττ 0.6 ~30 Baselines Chosen: Atlas sliding windows H.Evans Saclay Trigger Workshop: 5-Nov-02 5

6 Digital Filter Performance Criteria latency, #params, satur. Et-res, BC mis-id, t noise, phase, jitter, shape Algorithms Studied Deconvolution FIR Peak Detector Matched Filt + Peak Det baseline Linearity Behavior under Saturation Matched Filter H.Evans Saclay Trigger Workshop: 5-Nov-02 6

7 Digital Filter Algorithm Matched Filter + Peak Detector. Impulse filter Et 2. 3-Point Peak Detector Find peak Strengths linearity robust against signal phase shift [-32ns +32ns] stable under modest saturation Relative Weaknesses latency can be large does not resolve signals very close in time (few BC) Testing the Algorithm current: a few digital scope traces of signals soon: real data using Splitter Boards More Details in Talk by Denis Calvet H.Evans Saclay Trigger Workshop: 5-Nov-02 7

8 Sliding Windows ( a ) ( b ) Jet Algorithm Parameters RoI Size (a) Declustering Region RoI s comp to find local max effective sep. b/w LM s (b) Et cluster region (c) Naming: a,b,c 2,, Jet Algo EM Algorithm Sliding Windows LM (a,b) using only EM Isolation Region (d) EM isolation Had Veto Naming: a,b,d Tau Algorithm 2,, EM Algo Sliding Windows LM (a,b) use EM+Had Isolation Region (d) Et(2x2) / Et(4x4) > cut Naming: a,b,d E T Cluster Region 3x3 RoI 2x2 RoI 5x5 RoI declust reg. TT sep for LMs Data Needed for Declustering O O O O O O O O O O O O X O O O O O O O O O O O O Cand. RoI center > > > > > > > S(T) > > > H.Evans Saclay Trigger Workshop: 5-Nov-02 8 X RoI / EM cluster EM Isolation RoI RoI center used for compares Had Isolation 2,, Tau Algo X RoI / Tau cluster EM + Had Isolation

9 Algorithm Results Et(trig) / Et(reco) w/ Run IIa Data! Turn-on Curves from data TTs Ave = 0.4 RMS/Ave = 0.5 ZH ννbb Sliding Windows Ave = 0.8 RMS/Ave = 0.2 x3 Algo Jet EM Tau ICR Algorithm Study Status Rate const eff 2.5 3? O(2)? Comments most studied gains possible??? very preliminary tools available More Details in Talks by Emmanuelle Perez & Jovan Mitrevski H.Evans Saclay Trigger Workshop: 5-Nov-02 9

10 The Bottom Line Trigger EM DiEM Run IIa Definition EM TT > 0 GeV EM TT > 7 GeV 2 EM TT > 5 GeV Example Channel W ev WH evjj Z ee ZH eejj L Rate [khz] (no upgrade) L Rate [khz] (w/ upgrade) Core Trig Menu L = 2x0 32 BC = 396 ns Muon Di-Mu e + Jets Mu + Jet Jet+MEt Mu Pt > GeV CFT Track 2 Mu Pt > 3 GeV CFT Tracks EM TT > 7 GeV 2 Had TT > 5 GeV Mu Pt > 3 GeV Had TT > 5 GeV 2 TT > 5 GeV MEt > 0 GeV W µv WH µvjj Z/ψ µµ ZH µµjj WH evjj tt ev+jets WH µvjj tt µv+jets ZH vvbb < < < Not Yet Included LCal Topo cuts EM Algo Tau Algo MEt w/ ICR Mu+EM Mu Pt > 3 GeV + Trk EM TT > 5 GeV H WW,ZZ <0. <0. Iso Trk Di-Trk Total Rate Iso Trk Pt > 0 GeV Iso Trk Pt > 0 GeV 2 Trk Pt > 5 GeV Trk matched w/ EM H ττ, W µv H ττ ~30.0 < Total L Bandwidth = 5 khz H.Evans Saclay Trigger Workshop: 5-Nov-02 0

11 DØ Calorimeter Hermetic η < 4.2 E-Res EM:~4%/ E <% Jet:~80%/ E Cells η φ=0. 0. Sampling 4 EM 4-5 Had Trigger 32 φ x 40 η ICR at ±9,20 H.Evans Saclay Trigger Workshop: 5-Nov-02

12 The Run IIa Trigger System Level- Mainly detector-based Correlations Cal-Trk: quadrant level Mu-Trk: Ltrk info LMu Not deadtimeless Out rate ~5 khz (r dout time) Level-2 Calibrated data Extensive correlations Physic objects out (e,µ,τ,j ) Out rate ~khz (cal r dout) Accept Rate Limits L = 5 khz L2 = khz Cannot change Improve triggering by increasing bgrd rej. at same eff. Detector CAL c/f PS CFT SMT MU FPD Lumi Level Level 2 7 MHz 5 khz khz LCal LPS LCTT LMu LFPD Framework 50 Hz L2Cal L2PS L2CTT L2STT L2Mu Global L2 L3/DAQ Level 3 H.Evans Saclay Trigger Workshop: 5-Nov-02 2

13 L Cal in Run IIa Level- Calorimeter Trigger Using Run Ib System (990) Unit = Trigger Tower (TT) η φ = EM Had Compromise b/w Jet & EM EM Molière Radius ~0.02 Jet Radius ~0.5 Trigger Outputs # EM TTs > 4 Thr H Et veto avail. not used also avail. by quadrant # EM+H TTs > 4 Thr also avail. by quadrant Global E T Sum Missing E T (E x & E y ) Cal Preamp miss Et Adder Tree EM Cnt EM Add EM+H Cnt Trigger Framework Σ 4 TTs cnt>thr Σ 4 TTs cnt>thr Σ 4 TTs 7 inputs st Tier Adder Card 32 TT Precision Readout Trig Pickoff (shaping) L2/L3 rdout pipeline 8 EM 3-4 H EM+H Px & Py EM Et EM+H Et 7 inputs Adder Card 256 TT Sum Cal Cells in depth ADC (8-bit) H veto BLS Card (near detector) 4 EM 4 H 4 EM + 4 H TTs Total E T Adder Tree 2 nd Tier 3 rd Tier 4 inputs Sum Cal Towers laterally 0.2x0.2 Trig Towers EM or H TT Analog FE (E to Et scaling) CTFE Card (4 EM + 4 H TTs) Adder Card 280 TT BLS out: 4 EM TT 4 H TT Cmp to Thr s Totals: 280 EM 280 H H.Evans Saclay Trigger Workshop: 5-Nov-02 3

14 LCal in Run IIb EM H BLS Σ Σ 2 EM + 2 H ADF Timing Fanout Existing BLS Cards: 2560 TT 0.2x0.2 Board timing/ctrl ADC + Digital- Filter (ADF) 8-bit TT Et 6 EM 6 H x 80 TT Signal Processing Signals from L Track Trig Algo s (TAB) Sliding Windows Framework Interfaces Timing (SCL) L2 & L3 Control (TCC) No timing/ctrl clusters x 8 sums encoded clusters Cal-Trk Match Input (η φ) Global + Control (GAB) Global Sums Output (η φ) Jets EM Tau Et,Mpt x F r a m e w o r k Purpose New Features Digital Filter Jet,EM,Tau Clusters topology & isolation ICR in Global Sums & Clusts Clusts output to Cal-Trk Match ADF: ACD/Dig. Filt. 80 4x4 4x4 digitize, filter, E-to-Et ATF: ADF Timing F out all all ADF control/timing TAB: Trig Algo Board 8 40x2 3x4 algo s, Cal-Trk out, sums GAB: Global Algo Board all all TAB ctrl/time, sums, trigs to FWK H.Evans Saclay Trigger Workshop: 5-Nov-02 4

15 The ADF BLS 7.6 MHz x8 Analog Rcvr Baseline Subtr Anti Alias 0-bit ADC 30.3 MHz x4 4x4 η φ 6 EM TTs 6 H TTs x32 x8 x8 Dig Filt & E Et x4 Dig Filt & E Et 8-bit 60.6 MHz LVDS & MUX 424 MHz 3 cables out BLS x8 Analog Rcvr Baseline Subtr Anti Alias 0-bit ADC More Details in Talk by Denis Calvet H.Evans Saclay Trigger Workshop: 5-Nov-02 5

16 TAB L2/L3 Buffer L2/L3 TAB Components 30 Chan Link Rcv 40x2 η φ 960 TTs in 0 Sliding Windows Chips Algo s here ~9x9 TTs in ~4x4 LM out Global Chip 3x4 LMs out η edge effects clust counts Et sums Cal-Trk out 3 SLDBs xmit to Cal-Trk 364 MHz 6 MHz ADF ADF x 30 Chan Link (LVDS) Chan Link (LVDS) Sliding Windows 9 MHz ReSynch 8 to 2 bit x 0 Sliding Windows ReSynch 8 to 2 bit Jet Algo EM Algo Et Sum Jet Algo EM Algo Et Sum Tau Algo Tau Algo Global Clust Count & Et Sums Cal-Trk Reformat Chan Link (LVDS) More Details in Talk by John Parsons H.Evans Saclay Trigger Workshop: 5-Nov-02 6 Cal- Trk SLDB GAB

17 Global Design Issues to Discuss. Data Out to Cal-Trk latency 2. ADF-to-TAB Data Transfer baseline: National Channel-Link LVDS drivers/receivers w/ AMP 2mm HM cables each ADF has 3 identical outputs ADF-to-TAB transfer protocol clocks, error detection, etc. 3. Monitoring Data Quality raw data to ADF? 0-bit data transfer to TAB? filter coefficients? algorithm performance? dead/noisy channels? (see talk by Philippe Laurens) 4. Data to Outside World Cal-Trk content L2/L3 content Triggers to TFW 5. Testing and Commissioning digital filter tuning w/ data Splitter Boards (see talk by Denis Calvet) ADF-to-TAB xfer scheme Cable Tester (see talk by Jovan Mitrevski) Integration Tests (see talks by Dan Edmunds and Philippe Laurens) Parasitic Running 7. Algorithm Choices Finalize Jet Algo Studies Finish ICR Studies Set Params for EM & Tau Algo s (see talk by Emmanuelle Perez) H.Evans Saclay Trigger Workshop: 5-Nov-02 7

18 LCal Latency Latency budget is rather tight increase available time by lengthening depth of FE pipelines Step Muon system scintillators and PDTs are the bottleneck Change clock frequency on readout electronics BC to ADF Digitization Digital Filter Output to TAB Resynch Inputs Cal-Trk requires small degradation in time resolution gain 6, 32 ns ticks in pipeline depth Input Data Checks Jet/EM Algorithms Construct Output SLDB t [ns] Elapsed t [ns] ADF TAB as is system pipeline depth increased H.Evans Saclay Trigger Workshop: 5-Nov Comments calo to ADF in

19 ADF-to-TAB Data Routing System Design driven by data sharing req s of jet algorithm 2,, algo data from 6x6 TTs for LM include ICR in jets each TAB gets all data in η Minimize Data Sharing/Cabling only certain config s possible Large number of signals well matched to serial data xfer and serial algo s Board ADF TAB (2,,) Cables In 4 BLS ATF? 30 ADF GAB? Question to Discuss: Cables Out 3/? TAB (4x4) GAB (3x4) 3 Cal-Trk L2 ADF data duplication at ADF or TAB? TAB 8 φ=32-29 TAB 7 φ=28-25 TAB 6 φ=24-2 TAB 5 φ=20-7 TAB 4 φ=6-3 TAB 3 φ=2-9 TAB 2 φ=8-5 TAB φ= η=40- φ=32-29 η=40- φ=28-25 η=40- φ=24-2 η=40- φ=20-7 η=40- φ=6-3 η=40- φ=2-9 η=40- φ=8-5 η=40- φ=4- ADFs 80-7 ADFs 70-6 ADFs 60-5 ADFs 50-4 ADFs 40-3 ADFs 30-2 ADFs 20- ADFs 0- H.Evans Saclay Trigger Workshop: 5-Nov-02 9

20 ADF-to-TAB Data Protocol Data Transmission Hardware Channel-Link MUX 48:8 Chan-Link DS90CR483 / 4 8 output pairs 7-bits/cycle clock pair total: 8 lines Cable 4x5 2mm HM AMP total: 20 connectors Normal Mode ADF output 32 x 8-bit filtered TT Et s Monitor Mode ADF output 32 x 0-bit BLS input E Pins Possible Signals to Send Signal Diff. Data Out 0 Diff. Data Out Diff. Data Out 2 Diff. Data Out 3 Diff. Data Out 4 Diff. Data Out 7 Diff. Clock Framing Bit 8/0 Bit Select? Input Data (0-3) (w/ DC Balance) 0,,2,3,4,5 8,9,0,,2,3 6,7,8,9,20,2 6,7,4,5,22,23 24,25,26,27,28,29 30,3 Question to Discuss: Parity? Other Signals? error/synch detection 2 Grounds? monitoring inputs H.Evans Saclay Trigger Workshop: 5-Nov-02 20

21 TAB Data Formats 2-bit Sliding Windows to Global Chip Data No Type EM highest thresh [0=fail or -7] η=4,φ= 3, 2,, 2 Jet highest thresh [0=fail or -7] 4, 3, 2,, 3 Tau highest thresh [0=fail or -7] 4, 3, 2,, 2 Tau highest thresh [0=fail or -7] 4,4 3,4 2,4, EM: Sum Et EM+H: Sum Et Sum EM Et over η: φ= Sum EM+H Et over η: φ=4 No bit Global Chip to GAB Data Jet Count: Thr= EM Count: Thr= Jet Count: Thr=7 EM Count: Thr=7 Tau Count: Thr=2 Tau Count: Thr= Sum EM Et over η: φ= Sum EM+H Et over η: φ=4 EM+H Ex EM+H Ey Formats set by Architecture changes can be difficult constrain possible trigger terms that GAB can construct need to start thinking about these H.Evans Saclay Trigger Workshop: 5-Nov-02 2

22 Data to Cal-Trk No 8 Type 2-bit Sliding Windows to Global Chip Cal-Trk Data EM: count over thresh 4 η Jet: count over thresh 4 η -09 thr=4,φ= thr=4, φ= 4 Need to Verify that this scheme is acceptable , 3, , 2, ,,4 No Tau Info Sent would increase latency Et info only in Thr passed reduce transfer time No P 0 E 0 6-bit Cal-Trk Data from TAB 5-08 NULL NULL Count + Et Word: bits 07-04: count thr n Jet: count + Et: φ=,all η Jet: count + Et: φ=4,all η EM: count + Et: φ=,all η EM: count + Et: φ=4,all η bits 04-00: thr s passed 5 Longitudinal Parity H.Evans Saclay Trigger Workshop: 5-Nov-02 22

23 No No Data to L2/L3 Minimum L2/L3 Data from TAB 5-08 EM+H TT Et: η=, φ= EM+H TT Et: η=40, φ= EM+H TT Et: η=40, φ=4 L2/L3 Data from GAB EM TT Et: η=, φ= EM TT Et: η=40, φ= EM TT Et: η=40, φ=4 Mask EM clust s over L2 thr: η=5, φ=-6 Mask EM clust s over L2 thr: η=5, φ=7-32 Mask EM+H clust s over L2 thr: η=35, φ=-6 Mask EM+H clust s over L2 thr: η=35, φ=7-32 EM Sum Et EM+H Sum Et EM+H Sum Ex EM+H Sum Ey L2/L3 Data from TAB Run IIa: all TT Et s is cluster info useful? adds a lot of data L2/L3 Data from GAB note: only 35 possible cluster positions in eta because of edge effects Is this a sensible set? Start Run IIa L2/L3 Format # Bytes Data L2 Header EM TT seed mask EM+H TT seed mask EM TT Et s EM+H TT Et s L2 Trailer H.Evans Saclay Trigger Workshop: 5-Nov-02 23

24 The Schedule Project ADF & Co Task Analog Splitter built & tested ADF Timing Fanout built & tested Fabricate/Assemble prototype ADF End Date 9/7/02 /3/03 2/28/03 Silicon Silicon Ready Ready July July ADF prototype shipped to Fermilab 5/2/03 Production & Testing complete 2/8/04 ADF Crates Prototype Crate built & tested 5/29/03 Final Crates built & tested /9/03 TAB Fabricate/Assemble prototype /9/03 TAB prototype complete 5/6/03 Production & Testing complete 0/8/04 GAB GAB prototype complete 7/6/03 Production & Testing complete 2/7/05 Cables Test ADF to TAB cables //02 Integration Prototype Integration 0/9/03 Pre-Production Integration 5/2/04 We will be held strictly to this schedule! H.Evans Saclay Trigger Workshop: 5-Nov-02 24

25 The Bill Project Costs [FY02 k$] M&S equip Labor Total ADF + Splitter + Timing ADF Crates TAB GAB Cables TAB Crates & Services Integration Totals,430,425 2,855 Contingency Our Estimate: 45% Lehman Committee lower still being finalized Again we will be held to these numbers! H.Evans Saclay Trigger Workshop: 5-Nov-02 25

26 Summary Thanks to the efforts of Everyone We have an approved Project!!! Now we have to make it Work Let s get to It!!! H.Evans Saclay Trigger Workshop: 5-Nov-02 26