NCV Low I Q Low Dropout Linear Regulator

Transcription

1 NCV- Low I Q Low Dropout Linear Regulator The NCV is functionally and pin for pin compatible with NCV with a lower quiescent current consumption. Its output stage supplies ma with.% output voltage accuracy. Maximum dropout voltage is mv at ma load current. It is internally protected against V input transients, input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features. Features 3.3 V and. V Fixed Output.% Output Accuracy, Over Full Temperature Range A Maximum Quiescent Current at I OUT = A mv Maximum Dropout Voltage at ma Load Current Wide Input Voltage Operating Range of. V to V AECQ Grade Qualified and PPAP Capable Internal Fault Protection V Reverse Voltage Short Circuit/Overcurrent Thermal Overload This is a PbFree Device 3 TAB x A L Y W SOT3 ST SUFFIX CASE 3E SOIC Fused CASE 7 = (. V Version) = 3 = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package MARKING DIAGRAM AYW Vx Vx ALYWX (Note: Microdot may be in either location) PIN CONNECTIONS (SOT3) PIN FUNCTION V IN,TAB GND 3 V OUT (SOIC Fused) PIN FUNCTION NC, V IN 3 GND. V OUT. NC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Semiconductor Components Industries, LLC, July, 7 Rev. 9 Publication Order Number: NCV/D

2 NCV IN OUT.3 V Reference + Error Amp - Thermal Shutdown GND Figure. Block Diagram PIN FUNCTION DESCRIPTION Pin No. SOT3 SOIC Symbol Function V IN Unregulated input voltage;. V to V. 3 GND Ground; substrate. 3 V OUT Regulated output voltage; collector of the internal PNP pass transistor. TAB GND Ground; substrate and best thermal connection to the die., NC No Connection. OPERATING RANGE Rating Symbol Min Max Unit V IN, DC Input Operating Voltage (Note 3) V IN. + V Junction Temperature Operating Range T J + C MAXIMUM RATINGS Rating Symbol Min Max Unit V IN, DC Input Voltage V IN + V V OUT, DC Voltage V OUT.3 + V Storage Temperature T stg + C Moisture Sensitivity Level SOT3 SOIC Fused MSL 3 ESD Capability, Human Body Model (Note ) V ESDHB V ESD Capability, Machine Model (Note ) V ESDMIM V Lead Temperature Soldering Reflow (SMD Styles Only), Lead Free (Note ) T sld pk C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. This device series incorporates ESD protection and is tested by the following methods: ESD HBM tested per AECQ (EIA/JESDA C) ESD MM tested per AECQ3 (EIA/JESDA C). Lead Free, sec sec above 7 C, sec max at peak. 3. See specific conditions for DC operating input voltage lower than. V in the ELECTRICAL CHRACTERISTICS table at page 3

3 NCV THERMAL RESISTANCE Parameter Symbol Min Max Unit JunctiontoAmbient SOT3 SOIC Fused R JA 99 (Note ) C/W JunctiontoCase SOT3 SOIC Fused R JC 7 ELECTRICAL CHARACTERISTICS (V IN = 3. V, T J = C to + C, unless otherwise noted.) Characteristic Symbol Test Conditions Min Typ Max Unit Output Voltage. V Version Output Voltage 3.3 V Version Output Voltage 3.3 V Version V OUT. ma IOUT ma (Note ). V V IN V V OUT. ma IOUT ma (Note ). V V IN V.9.. V V V OUT I OUT = ma, V IN = V (Note 7) V Line Regulation. V Version V OUT vs. V IN I OUT =. ma. V V IN V mv Line Regulation 3.3 V Version V OUT vs. V IN I OUT =. ma. V V IN V mv Load Regulation V OUT vs. I OUT. ma I OUT ma (Note ). + mv Dropout Voltage. V Version V IN V OUT I OUT = ma (Notes & ) 7 mv Dropout Voltage 3.3 V Version V IN V OUT I OUT = ma (Notes & ). V Quiescent Current I q I OUT = A T J = C T J = C to + C T J = C to C Active Ground Current I G(ON) I OUT = ma (Note ).. ma Power Supply Rejection PSRR V RIPPLE =. V PP, F = Hz 7 db Output Capacitor for Stability. V Version Output Capacitor for Stability 3.3 V Version C OUT ESR C OUT ESR I OUT =. ma to ma (Notes & 7) I OUT =. ma to ma (Notes & 7) PROTECTION Current Limit I OUT(LIM) V OUT =. V (. V Version) (Note ) V OUT = 3. V (Note ) Short Circuit Current Limit I OUT(SC) V OUT = V (Note ) ma Thermal Shutdown Threshold T TSD (Note 7) C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. oz., mm copper area.. Use pulse loading to limit power dissipation.. Dropout voltage = (V IN V OUT ), measured when the output voltage has dropped mv relative to the nominal value obtained with V IN = 3. V. 7. Not tested in production. Limits are guaranteed by design.. V DO = V IN V OUT. For output voltage set to <. V, V DO will be constrained by the minimum input voltage A F F ma. V Input C in nf V in V out Output C OUT F. V Version F 3.3 V Version GND Figure. Applications Circuit 3

4 NCV TYPICAL CHARACTERISTIC CURVES V Version 9 Unstable Region 7 ESR () 3 Stable Region V in = 3. V C out F 7 Figure 3. ESR Stability vs. Output Current ( V Version) QUIESCENT CURRENT (ma) C V IN = 3. V C C Figure. Quiescent Current vs. Output Current ( V Version) QUIESCENT CURRENT (ma) V IN = 3. V C C C Figure. Quiescent Current vs. Output Current (Light Load) ( V Version)... C. DROPOUT VOLTAGE (V) C C OUTPUT VOLTAGE (V) Figure. Dropout Voltage vs. Output Current ( V Version) TEMPERATURE ( C) Figure 7. Output Voltage vs. Temperature ( V Version)

5 NCV TYPICAL CHARACTERISTIC CURVES V Version. T A = C 3 T A = C OUTPUT VOLTAGE (V) R L =. Figure. Output Current vs. Input Voltage ( V Version) Figure 9. Output Voltage vs. Input Voltage ( V Version) QUIESCENT CURRENT (ma) R L = R L = 3 Figure. Quiescent Current vs. Input Voltage ( V Version)

6 NCV TYPICAL CHARACTERISTIC CURVES 3.3 V Version 3. QUIESCENT CURRENT (ma) C C C V in = 3. V 7 OUTPUT VOLTAGE (V) I out = ma 3 3 Figure. Quiescent Current vs. Output Current Figure. Output Voltage vs. Input Voltage 3.3 QUIESCENT CURRENT (ma) 7 3 I out = ma I out = 33 ma 3 3 OUTPUT VOLTAGE (V) V in = 3. V I out = ma Figure 3. Quiescent Current vs. Input Voltage TEMPERATURE ( C) Figure. Output Voltage vs. Temperature QUIESCENT CURRENT (A) 3 V in = 3. V I out = ma TEMPERATURE ( C) Figure. Quiescent Current vs. Temperature Figure. Output Current vs. Input Voltage

7 NCV TYPICAL CHARACTERISTIC CURVES 3.3 V Version Unstable Region ESR () Stable Region 3 Figure 7. ESR Stability vs. Output Current 9 V in = 3. V C out F 7

8 NCV Circuit Description The NCV is functionally and pin for pin compatible with NCV with a lower quiescent current consumption. Its output stage supplies ma with.% output voltage accuracy. Maximum dropout voltage is mv at ma load current. It is internally protected against V input transients, input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features. Regulator The error amplifier compares the reference voltage to a sample of the output voltage (V OUT ) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperaturestable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. Regulator Stability Considerations The input capacitor C I in Figure is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately in series with C I. The output or compensation capacitor, C OUT helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. Tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however, attention must be paid to ESR constraints. The capacitor manufacturer s data sheet usually provides this information. The value for the output capacitor C OUT shown in Figure should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed at values of C Q F, with an ESR 9 for the. V Version, and C Q F with an ESR for the 3.3 V Version within the operating temperature range. Actual limits are shown in a graph in the Typical Performance Characteristics section. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure ) is: PD(max) (eq. ) VIN(max) VOUT(min) *IOUT(max) VIN(max) *Iq Where: V IN(max) is the maximum input voltage, V OUT(min) is the minimum output voltage, I OUT(max) is the maximum output current for the application, and I q is the quiescent current the regulator consumes at I OUT(max). Once the value of P D(max) is known, the maximum permissible value of R JA can be calculated: PJA ( C T A ) (eq. ) PD The value of R JA can then be compared with those in the package section of the data sheet. Those packages with R JA s less than the calculated value in Equation will keep the die temperature below C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram. Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R JA : RJA RJC RCS RSA (eq. 3) Where: R JC = the junctiontocase thermal resistance, R CS = the casetoheat sink thermal resistance, and R SA = the heat sinktoambient thermal resistance. R JA appears in the package section of the data sheet. Like R JA, it too is a function of package type. R CS and R SA are functions of the package type, heat sink and the interface between them. These values appear in data sheets of heat sink manufacturers. Thermal, mounting, and heat sinking are discussed in the ON Semiconductor application note AN/D, available on the ON Semiconductor Website.

9 NCV JA ( C/W) SOIC Fused SOT3 3 7 COPPER AREA (mm ) Figure. JA vs. Copper Spreader Area SOT3 SOIC Fused R(t) ( C/W) PULSE TIME (sec) Figure 9. R(t) vs. Pulse Time ORDERING INFORMATION Device Package Shipping NCVSTT3G NCVST33T3G SOT3 (PbFree) SOT3 (PbFree) / Tape & Reel / Tape & Reel NCVD33RG SOIC Fused (PbFree) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. 9

10 NCV PACKAGE DIMENSIONS SOT3 (TO) CASE 3E ISSUE N. (3) H E e A e D b 3 A b E L L C NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: INCH. MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A A b b c D E e e L.. L H E SOLDERING FOOTPRINT SCALE : mm inches

11 NCV PACKAGE DIMENSIONS Y B X A S. (.) M Y M SOIC NB CASE 77 ISSUE AK K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.. 7 THRU 7 ARE OBSOLETE. NEW STANDARD IS 77. Z H G D C. (.) M Z Y S X S SEATING PLANE. (.) N X M SOLDERING FOOTPRINT* J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.7 BSC. BSC H.... J K..7.. M N.... S SCALE : mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 9 E. 3nd Pkwy, Aurora, Colorado USA Phone: 3377 or 33 Toll Free USA/Canada Fax: 3377 or 337 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 37 ON Semiconductor Website: Order Literature: For additional information, please contact your loca Sales Representative NCV/D