Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores

Transcription

1 Test Panning for Mixed-Signa SOCs with Wrapped Anaog Cores Anuja Sehga, Fang Liu, Sue Ozev and Krishnendu Chakrabarty Abstract Many SOCs today contain both digita and anaog embedded cores. Even though the test cost for such mixed-signa SOCs is significanty higher than that for digita SOCs, most prior research in this area has focused excusivey on digita cores. We propose a ow-cost test deveopment methodoogy for mixed-signa SOCs that aows the anaog and digita cores to be tested in a unified manner, thereby minimizing the overa test cost. The anaog cores in the SOC are wrapped such that they can be accessed using a digita test access mechanism (TAM). We evauate the impact of the use of anaog test wrappers on area overhead and test time. To reduce area overhead, we present an anaog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduing. We aso demonstrate the feasibiity of using anaog wrappers by presenting transistor-eve simuations for an anaog wrapper and a representative core. We present experimenta resuts on test scheduing for an ITC 02 benchmark SOC that has been augmented with five anaog cores. 1 Introduction Advances in semiconductor technoogy are contributing to the increasing compexity of system-on-chip (SOC) integrated circuits. Many SOCs in use today are mixed-signa circuits containing both digita and anaog embedded cores [1, 2]. There are enormous costs associated with the testing of mixed-signa SOCs. The cumuative test cost of an SOC has three main components: (i) the cost of the Automatic Test Equipment (ATE); (ii) the cost of siicon area overhead due to the on-chip test hardware; (iii) the cost due to test appication time. In order to reduce the overa test cost of mixed-signa SOCs, a of the above components of the test cost shoud be minimized. Most prior research on test cost reduction for SOCs has focused on digita SOCs. owever, since the test cost of a mixed-signa SOC is much higher than that of digita SOCs [3] and many SOCs today have significant anaog content, there is a need for efficient test methodoogies that can hande mixed-signa SOCs and reduce their test cost. Many consumer eectronics products, such as MP3 payers, PDAs, and audio receivers contain a sma number of anaog cores that operate in the ow to mid-frequency range; these cores are embedded in an SOC together with a arge number of digita cores. Consumer eectronics products beong to a high voume, ow profit-margin domain, where reducing test cost is of prime importance. Moduar testing of embedded cores in SOCs is being increasingy advocated to simpify test generation, enhance test reuse, and reduce test cost [4]. Test wrappers are used to isoate a core, whie test access mechanisms (TAMs) transport test patterns and test responses between SOC pins and core I/Os. This research was supported in part by the Semiconductor Research Corporation under contract no TJ Department of Eectrica & Computer Engineering Duke University, Durham, C 27708, USA In [], preiminary work was done on the use of anaog test wrappers to eiminate the need for expensive mixed-signa testers and aow a unified test approach for both digita and anaog cores. The anaog test wrappers can be used for ow-frequency appications that require anaog tests in the audio frequency range. These wrappers aow an unified testing of the digita and anaog cores in an SOC, thereby reducing test appication time. In this paper, we improve upon [] in the foowing ways: We propose a new resource optimization technique that reduces the overa area and routing overhead by using shared test wrappers for the time-mutipexed testing of anaog cores. We propose a test panning method that combines a previousy deveoped TAM optimization approach [6] with the new resource optimization approach. It eads to a TAM architecture that is efficient in terms of area, routing costs, and overa test time. We impement anaog wrappers in a present transistor-eve simuation resuts. AMI technoogy and Anaog wrappers can contribute significanty to area overhead. ence, if the number of test wrappers is reduced, the area overhead is aso reduced. In the proposed resource optimization technique, we share test wrappers for time-mutipexed testing of anaog cores. This approach reduces the area overhead due to the anaog wrappers; however, it can potentiay increase the testing time for the SOC. The proposed cost optimization approach evauates judiciousy chosen combinations of shared anaog wrappers, and chooses the best wrapper architecture for the anaog cores in terms of overa test cost of the SOC. A pruning technique based on ower bounds on the test time, area overhead, and routing overhead, is used to reduce the number of wrapper combinations that are evauated. ence this approach is computationay inexpensive. In the absence of mixed-signa SOC benchmarks, we present resuts for a mixed-signa SOC that has been crafted by adding five anaog cores to a digita SOC from the ITC 02 SOC test benchmarks [7]. These resuts demonstrate that a significant reduction in the overa test cost can be achieved using the proposed approach. The rest of this paper is organized as foows. Section 2 presents a review of reevant prior work. In Section 3, we detai the anaog wrapper optimization approach, which is foowed by a description of the cost-optimization approach in Section 4. In Section, we describe the impementation of the wrapper architecture and present resuts for one of the anaog core tests. In Section 6, we present experimenta resuts for an ITC 02 benchmark SOC. Finay, we concude the paper in Section 7. 2 Review of Prior Work In the anaog testing domain, research has primariy focused on defining core-eve measurement and test methods. Attempts have aso been made to reduce the overa test time for anaog circuits. In [8, 9], ony a subset of parameters are tested, which are seected based on Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 0) /0 $ IEEE

2 - anaog in from TAM f TAM encoder register f update f s contro test enabe Anaog Phase Shift sef-test register seria-to-parae ratio anaog out Figure 1. Bock diagram of the anaog test wrapper []. decoder to TAM parameter correations. Automated generation of test stimui has aso been used as a means to reduce test time of anaog circuits [10]. Significant research has been done to eiminate the need for an expensive anaog or mixed-signa ATE. The use of on-chip data converters, proposed in [11, 12], obviates the need for expensive anaog testers. Severa BIST techniques have aso been proposed for mixed-signa bocks that cannot be directy tested by an - pair. Such BIST techniques target either data converters themseves [16, 17, 18, 1] or PLLs [21, 20, 19]. Recenty, in [], test wrapper design for anaog cores has been deveoped to obviate the need for mixed-signa testers. The anaog test wrappers contain on-chip data converters that convert anaog cores into virtua digita cores. Thus, the wrapped anaog cores can be tested in a unified manner with the digita cores on a digita TAM. The test wrappers are reconfigurabe for different data resoutions and frequencies. The reconfigurabiity aows the use of the wrapper for a variety of anaog tests that may potentiay differ in TAM width and samping frequency requirements. The on-chip impementation of the data converters can be used for a wide range of ow frequency appication. In [], however, the impact of test wrappers on overa area overhead of the SOC was not considered. Aso, an on-chip impementation of the wrappers was not done to evauate their feasibiity. Figure 1 shows a bock diagram of the anaog wrapper proposed in []. The contro and cock signas generated by the test contro circuit are highighted. The registers at each end of the data converters are written and read in a semi-seria fashion depending on the frequency requirement of each test. The digita test contro circuit seects the configuration for each test. This configuration incudes the divide ratio of the digita TAM cock, the seria to parae conversion rate of the input and output registers of the data converters, and the test modes. The test modes of the wrapper incude a norma mode, a sef-test mode and a core-test mode. With the conversion of the anaog cores into virtua digita cores, TAM optimization techniques can be used to optimize a digita TAM architecture for the testing of digita and anaog cores of mixed-signa SOCs. 3 Anaog Wrapper Optimization In Section 2, we discussed the anaog test wrapper design proposed in []. The - pair, together with the encoder-decoder pair, forms the predominant part of the anaog test wrapper. The encoder and decoder aow the wrapper to be reconfigured for a set of different tests. In our proposed approach, we expoit this feature of reconfigurabiity to optimize the resource utiization and reduce the area overhead cost. We propose that an anaog test wrapper be designed such that it can support testing of more than one anaog core mutipexed in time from one test to another. In our proposed approach we use the reconfigurabiity feature of the anaog wrappers to aow the test of mutipe anaog cores, using a singe wrapper, thereby reducing the overa area overhead significanty. The design proposed in [] can be easiy modified to accommodate this feature. Figure 2 iustrates two anaog cores sharing test wrappers (ony the - pair of the wrappers are shown for the purpose of iustration). The time-mutipexed testing of the cores can be ensured by the use of mutipexers. Athough the use of anaog mutipexers may resut in additiona parasitic noise, the use of anaog mutipexers is an accepted practice in anaog testing, and design methods exist to aeviate the noise probem [22, 23, 24, 2]. The sizes of the encoder, decoder, and the - pair in a shared anaog wrapper are determined such that they can satisfy the requirements of a the cores sharing the wrapper. The resoution of the - pair in the proposed shared anaog wrapper is seected to be the maximum of the - resoution requirements of a the anaog cores sharing the wrapper. Simiary, the encoder and decoder are designed for the test with the argest TAM width requirement. The encoders and decoders can be configured to test any of the anaog cores. owever, a modue that requires high-speed and ow-resoution data converters cannot share its wrapper with a modue that requires high-resoution and ow-speed data converters. It may not be feasibe to satisfy the requirements of high-speed and high-resoution with reasonabe overhead. Wrapper sharing resuts in a certain routing overhead that needs to be accounted for. For anaog cores that are separated by a arge distance, sharing is ess advantageous since the routing overhead wi be high. In this work, we evauate the area overhead due to anaog test wrappers as foows. The routing overhead is considered to be a percentage of the wrapper architecture s area overhead. This percentage depends on the reative on-chip ocation of the anaog cores. Typicay this ocation is determined by the functiona proximity between the anaog core and other cores in the system. Thus, an approximate idea about the proximity of anaog wrappers can be obtained prior to ayout. The area overhead is estimated as the ratio of the area overhead due to sharing, to the area overhead if there is no sharing of wrappers. When there is no sharing of wrappers between cores, the area overhead is maximum. The area overhead due to test wrappers can be expressed as: " $ & ( * $ * + (1) where, -. : number of anaog wrappers used; : the number of anaog cores; : the routing overhead for shared wrapper 0 ; $ * : area overhead of anaog wrapper 1 ; $ & ( : maximum of the individua wrapper area overheads of the cores for the shared wrapper 0. The cost function defined above is used for preiminary cost anaysis. Using the above estimate, it is possibe to determine the reative cost of the different sharing combinations among the various anaog cores. The routing overhead of a wrapper that serves 3 cores is defined as 3 4 +,where 6 is a factor proportiona to 8 the cumuative distance of the 3 cores from each other. In this work, without oss of generaity, we have considered a representative vaue of to iustrate the approach. Thus, wrappers that serve ony one core have a routing overhead of. ote that : shoud aways be ower than 100. The sharing combinations that exceed the overhead of the no-sharing case shoud not be considered. In order to avoid potentia resource conficts, it is imperative that the tests for cores that share a wrapper do not not overap in time in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 0) /0 $ IEEE

3 " " b from TAM f ck. Anaog core Anaog core to TAM Figure 2. Shared test wrapper for anaog cores. ; < = B ; < = B 4 D A,CE D A,D,EE 31.4 D C,DE D A,B,C,DE 98.7 D C,EE D A,B,C,EE D A,BE D A,C,D,EE 78.6 D A,DE D A,B,D,EE 2.8 D A,EE D A,B,CE D DEE D D,EE D A,C,DE D B,EE D A,B,CE D A,C,EE D B,DE 69.7 D A,C,DE D A,D,EE D B,CE 68. D A,C,EE D C,D,EE D A,BE 7.2 D A,B,DE D A,B,EE D C,DE 6.0 D C,D,EE D A,B,DE D C,EE 1.6 D A,B,EE D A,B,C,D,EE ; : umber of wrappers; < : Combination of cores that share a wrapper. Tabe 1. Area overhead costs for a combinations of wrapper sharing. the test schedue. Thus, we constrain the TAM optimization procedure such that the tests for cores sharing the same wrapper are schedued seriay in time. In this way, the tota test time usage of the test wrapper is the sum of the test times of the anaog cores that share the wrapper. A ower bound on the overa test time of a the anaog cores can now be cacuated as the maximum of the usage of every anaog test wrapper, i.e., if three anaog test wrappers are used to test a the anaog cores, then a ower bound I K on the test time is the maximum of the test time usage of the three anaog test wrappers. Tabe 1 shows the : vaues for a the combinations of sharing between the five anaog cores considered in the experimenta setup. The normaized ower bound for each case is aso presented; these vaues have been normaized to the maximum ower bound. A detaied description of the five anaog cores abeed $ to L is presented in Section 6. (Since Core $ and Core M have identica tests, ony unique combinations for Core $ are presented.) 4 Test Cost Optimization In this section, we define the test cost minimization probem for a given TAM width. The objective is to minimize the test cost in terms of test appication time and the area overhead. We use a previousy deveoped TAM optimization technique, based on rectange packing [6], to obtain the test appication time for an SOC. Unike the approach described in [], this approach expoits the disparity in the TAM width requirements of digita and anaog cores to reduce the overa test time of the SOC. The TAM width requirements of an anaog core are usuay much smaer than that of most digita cores []. Moreover, their testing time does not reduce with an increase in the number of digita TAM wires aocated for them. For digita cores, there exists a staircase variation of testing time with TAM width [13], hence their testing time can be reduced with an increase in the TAM width. Thus, there is often a substantia disparity between the TAM width requirements of digita and anaog cores. As a resut, when anaog cores are tested seriay with digita cores on the same TAM partition, the anaog cores do not use a the TAM wires. Consequenty the overa time taken to test the SOC is not optimized. We therefore use a TAM optimization approach, based on a fexibewidth TAM architecture, that can hande digita and anaog cores in a unified manner, yet bridge the gap in TAM width requirements of digita and anaog cores. The test cost for a given SOC-eve TAM width can be minimized as foows. The tota test O cost is expressed O as (2) where O is the cost weighting factor for the test appication time, and O is the cost weighting factor for the area overhead cost.the weighting factors are defined such that O O. The cost of test appication time is expressed as X, + V V where is the test time of the SOC when a the anaog cores V share a singe anaog wrapper. This case represents the most constrained scenario for test scheduing, hence for any given TAM width, it is ikey to yied the highest test time. Essentiay, is the test time normaized to the maximum possibe test time. The TAM optimization procedure is used to obtain the vaue of for a given TAM V width. The area overhead cost incudes the cost of the anaog core wrappers and the routing overhead of shared wrappers as expained in : [ \ ] ^ _ Section3.Boththecosts: and have been defined to have vaues between 1 and 100. ow, the probem of minimizing the overa test cost of an SOC can be stated as foows. Probem : Given the test data parameters for the digita cores, the testing time in cock cyces and the core-eve TAM widths for the anaog cores, the tota SOC-eve TAM width,and the test time cost and area overhead cost weights O and O respectivey, determine (i) the wrapper design for digita cores, (ii) the groups of anaog cores that share anaog wrappers, (iii) the TAM width for each core and test schedue for the SOC, such that the tota number of TAM wires utiized at any moment does not exceed the overa TAM width, and the tota cost O O is minimized. The Design wrapper agorithm from [13] is used to design the wrappers for digita cores. ext, the grouping of the anaog cores is determined, such that the anaog cores grouped together share the same anaog test wrapper. Finay, the TAM optimization approach is used to to determine a test schedue for the digita and anaog cores. Depending on the specified weights O and O, the anaog cores can be grouped such that they share anaog wrappers and the overa cost of the wrappers is minimized. The degree of sharing is dictated by the weighting factors in the cost function. If O d O,thetest time is given more weightage in optimization. In this case, the degree of wrapper sharing may be chosen such that the area overhead cost Oreduction d O is compromised to achieve better test times. Simiary if, the degree of sharing is chosen such that the area overhead minimization has priority over test time minimization. One approach for soving probem [ e f g i is to evauate the overa cost for every possibe configuration of shared anaog wrapper (as presented in Tabe 1) for a given TAM width and weights O and O. This exhaustive approach requires the TAM optimization procedure to be run for every combination of anaog cores to obtain the vaues. This is computationay expensive for a arger probem instance with many anaog cores since the number of distinct combinations increases exponentiay with the number of anaog cores. We propose a heuristic approach that scaes we with the increase in the number of anaog cores and provides a near optima resut. We use a pruning technique based on the area overhead costs and anaog test time ower bounds I K, which are avaiabe prior to cost op- Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 0) /0 $ IEEE

4 ~ - d j q k Procedure Cost Optimizer(j k 1. Group combinations having the same degree of sharing to form m n m p m q p s s s p m v ; 2. for x y n z to { do 3. for y n z to ~ m do 4. Evauate ƒ ~ m ~ y n j ) Ž I K ~ m ~ j Ž ~ m ~ ; x y n z { ƒ ~ m ~ n š š v ƒ ~ m ~. od; 6. od; 7. for to do 8. Seect ; 9. Run ž Ÿ x x ƒ procedure to get the test times ž ~ of eement m ~ ;od; 10. ž y n š š v ~ ž ~ 11. for x y n z to { do 12. Evauate cost ª ~ for seected eement; 13. od; 14. Seect ª v n x { š š v ª ~ ; 1 for x y n z to { do 16. if ª ª v, eiminate group x ; 17. od; 18. Evauate a eements of the groups that have not been eiminated; 19. Return the eement that resuts in the smaest ª ~ ; Figure 3. Pseudocode for procedure Cost Optimizer. timization. Figure 3 detais the pseudocode for the proposed heuristic procedure Cost Optimizer. First (in Line 1), a the combinations of anaog cores sharing test wrappers are grouped by their degree of sharing. i.e., combinations that have the same area overhead cost ( ) are grouped together. A the groups together form a set. The goa is to be abe to eiminate an entire group without having to do compete evauation. Compete evauation for a combination entais finding a test schedue by using the TAM optimization procedure. The next step (ine 4) is to estimate preiminary costs for every combination based on area overhead, cost weights, and the ower bounds on anaog test times. We cacuate the preiminary costs : ± for every combination as: O O : ± 1 I K 1 : 1 (3) where, 1 is combination 1 of group. Based on the : ± vaues, the combination/eement that has the smaest : ± vaues is chosen from every group 0 (Line 8). ext, the TAM Optimizer procedure is used to evauate the : vaues of the chosen eements of each group. These vaues are used to determine the : vaue for the chosen eements. The group with the minimum cost v is not eiminated. ext, any group that satisfies the eimination criteria (i.e., v ² ) is eiminated. The eimination criteria can be reaxed by making the threshod ² arger. Anaog Wrapper Impementation We next present impementation detais of the anaog test wrapper and demonstrate its functionaity by appying a test to a wrapped anaog core. We design the wrapper using an 8-bit - pair. A simuations and ayout are done in a process technoogy. The impementation of the and in a wrapper is critica to the performance and area-overhead of the wrapper. We use a moduar pipeined architecture for the 8-bit [14], using two fash s and one. Figure 4(a) shows a bock diagram of the. The moduar architecture of the reduces the area overhead significanty. An -bit fash requires comparators, thus an 8-bit fash architecture typicay requires 26 comparators. In contrast, Vin V[0:3] V[4:7] MSB LSB MSB First 4 bits (a) (b) V1 - Vin Vq + 1/ LSB Lower 4 bits Vout Figure 4. (a) Bock diagram of a moduar 8-bit [14]; (b) Bock diagram of a moduar 8-bit. the moduar approach needs ony 32 comparators. The comparators are the primary contributers to the overa area of the. Simiary, we use a moduar votage-steering 8-bit architecture [14], which is constructed from two s. Figure 4(b) shows a bock diagram of the 8-bit. This moduar approach reduces the number of resistors used by a factor of 8. Athough the moduar approach aso adversey impacts the speed of operation of the data converters, it does not prevent us from achieving our desired performance for the owspeed appications that are being targeted here. To demonstrate the accuracy of using digita test patterns to test wrapped anaog cores, we appy a cut-off frequency test µ e to anaog core A (a detaied description of the core and its tests is presented in Tabe 2 of Section 6). The core is tested for cut-off frequency by appying a muti-tone signa. The frequency spectrum of the resuting signa is used to extrapoate the cut-off frequency of the fiter. We compare the frequency spectrum obtained without using a wrapper and doing a direct anaog test to that of the test responses obtained from the wrapped anaog core. Figure shows the SPICE simuation resuts for the two scenarios. The error in the response from the wrapped anaog core is approximatey. This error can be reduced further by using a more frequencies in the input signa; for the purpose of iustration, we have chosen an input with ony three frequencies. The frequency spectrum is obtained by post-processing the transient anaysis data obtained from the simuations. The system cock frequency is 0Mz and the samping frequency of the input signa is 1.7Mz. The number of sampes used is 41. The suppy votage used is 4V. We have aso impemented a test chip for testing and characterizing an 8-bit anaog wrapper. Its area in the process is ony Preiminary comparison with an industria core impemented in 0.12 technoogy indicates that the wrapper, even though it is impemented in 0. technoogy, is ony one-eight the size of the core. We expect this ratio to be significanty smaer (6 X )if the wrapper is impemented in the same technoogy as the core. In this work, we have not considered the overhead of testing the and in the wrapper. Efficient BIST techniques can be used for testing the data converters [16, 17, 18] in the sef-test mode of the wrapper. 6 Experimenta Resuts In this section, we present the description and specifications of the anaog cores used in our mixed-signa SOC. ext, we study the impact of shared test wrappers on the overa SOC test cost. We aso present a Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 0) /0 $ IEEE

5 Û ê LPF i/p (db) Frequency (Kz) LPF o/p (db) f c =61kz Frequency (Kz) Wrapper o/p (db) f c =8Kz Frequency (Kz) Figure. (a) Frequency spectrum of the appied anaog test; (b) Frequency spectrum of the anaog response of the core; Frequency spectrum of the response of the wrapped anaog core. ¹ º» ¹ ¼ ½ ¾ À Ã Ä Å Á Â Ã Ç È Æ É Ê Ã Ë È É Ê Ì Ì Í Î Ï Ð Ñ Ñ Ò Ó Ô Ð Ã Ä Å < Æ Õ Ö Ì Ì Í Î Ö Á Ö Ø Ú Ø Á Test Cores & : I- transmit 0kz 0kz 1.Mz 0, kz kz 1.Mz 13,63 4 & 1Mz 2Mz 8Mz 12, kz 20kz 8Mz 26,973 2 DC DC 10kz kz 400kz 1Mz 32,000 4 Core : CODEC audio 20kz 20kz 640kz 80, kz kz 1.Mz 136,33 1 2kz 31kz 2.46Mz 83,22 1 Core : Baseband down converter 3.2Mz 9.7Mz 78Mz 1, Mz 26Mz 26Mz 9, Mz 26Mz 26Mz 31,08 4 Core : Genera purpose ampifier 69Mz 69Mz 69Mz,400 8Mz 8Mz 8Mz 2,00 1 Tabe 2. Test requirements for the anaog cores. comparison of the cost-optimization heuristic with the exhaustive costoptimization approach. For our experimenta set-up, we have used a digita SOC from the ITC 02 SOC test benchmarks, namey p We consider ony p93791 because the test time for the other SOCs reaches a ower bound for reativey sma vaues of TAM width. We have added five anaog cores to the SOC. We refer to the mixed signa SOC as p93791m. The anaog cores consist of a pair of baseband I- transmit path with a bandwidth of 00kz, a CODEC audio path with a bandwidth of 0kz, a baseband down conversion path, and a genera purpose ampifier. These anaog cores are taken from a commercia baseband ceuar phone chip. The test set specifications for each of these anaog cores are given in Tabe 2. Due to the ack of a standardized anaog test generation too, anaog tests are defined manuay based on the core specifications. For the I- transmit path pair, six distinct specification-based tests are defined. These incude the pass-band gain ( Ü Ý ), the cut-off frequency (µ e ), the attenuation eves at 1Mz and 2Mz ( Þ ß à and q Þ ß à ), the third order input intercept (á á [ â ), and the DC offset Ò Ó (ã f ä ä ), and the phase mismatch (å f ä ä ). For the audio CODEC path, the specifications incude Ü Ý, µ e, and the tota harmonic distortion ( ). The Baseband down conversion path has three specified V æ ç tests, namey a test for the á á [ â, a test for the gain ( $ é ), and a test for the dynamic range ( ). Lasty, the tests for the genera purpose ç ê ampifier incude a test for the sew rate (ë ) and a test for the $ é. The TAM width requirements ì for each of the anaog cores are aso #of Wrapper í î ï wrappers sharing î ð ñ ò î ð ó õ î ð ö ó 4 D A,CE D C,DE D C,EE D A,BE D A,DE D A,EE D D,EE D A,B,CE D A,C,DE D A,C,EE D A,B,DE D C,D,EE D A,B,EE D A,D,EE D A,B,C,DE D A,B,C,EE D A,C,D,EE D A,B,D,EE D A,B,CE D D,EE D A,C,DE D B,EE D A,D,EE D B,CE D C,D,EE D A,BE D A,B,EE D C,DE D A,C,EE D B,DE D A,B,DE D C,EE D A,B,C,D,EE Tabe 3. Test time resuts for SOC p93791m for different combinations of anaog wrapper sharing. presented in Tabe 2. The sef-test mode test time has not been considered for both anaog and digita cores, thus, Tabe 2 presents the test time on the core-test mode ony. It shoud be noted that the anaog test wrappers are not imited to the tests isted in Tabe 2. The proposed test wrappers can be used for anaog tests that are within the operating frequency and resoution of the data converters in the anaog test wrappers. ext, we study the impact of wrapper sharing among the anaog cores on the overa test time of an SOC. Tabe 3 presents resuts for SOC p93791m. The test time is presented for a the combinations of anaog wrapper sharing. The test times are normaized to the case of maximum test time, thus they are essentiay the : vaues for the combinations. As expected, the test time for the case when a the anaog cores share the same wrapper resuts in the maximum test time. The combinations that resut in the owest test time are highighted in Tabe 3. We concude from the resuts that as the TAM width increases, the anaog core combinations have a greater affect on the overa SOC test time. This is because with an increase in TAM width, the test time of the digita cores decreases and the test time of the anaog cores Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 0) /0 $ IEEE

6 : : î þ ü > > > ð ð ð þ Û ÿ þ À ð ù ú û, Û À = = ü ½ ý ½ ý A,B,EE C,DE A,B,EE C,DE A,B,DE C,EE A,B,DE C,EE C,D,EE A,BE C,D,EE A,BE A,B,EE C,DE A,B,EE C,DE A,B,DE C,EE A,B,DE C,EE 61. À ð ù ú õ, À ù ú ò D A,B,EE D C,DE D A,C,D,EE D A,B,DE D C,EE D A,B,DE D C,EE D C,D,EE D C,EE D C,D,EE D C,EE D A,B,EE D C,DE D A,B,EE D C,DE D A,B,DE D C,EE D A,B,DE D C,EE 61. À ð ù ú ò, À ù ú õ D A,C,DE D B,EE D A,C,DE D B,EE D A,B,DE D C,EE. 10 D A,B,DE D C,EE D A,B,EE D C,DE.3 10 D A,B,EE D C,DE D A,B,EE D C,DE.1 10 D A,B,EE D C,DE D A,B,DE D C,EE D A,B,DE D C,EE ± with the exhaustive eva- Tabe 4. Comparison of : uation approach. ù ú û becomes more prominent. Thus, the difference between the owest and the highest test times of the various combinations for,and 64 are 2.4, 7.36, and 17.18, respectivey. It is aso seen that the owest test times are obtained for combinations with a ower degree of sharing. owever, for and, the owest test times can aso be obtained with combinations that have a high degree of sharing. These cases show that some test schedues can resut in a ow test test time, even with a high degree of sharing. Tabe 4 presents the cost of sharing for a set of O and O vaues. The proposed : 0 0 ± procedure is compared with the exhaustive evauation approach described in Section 4. (ote that whie exhaustive enumeration is possibe for these test cases, the high CPU time notwithstanding, it is unikey to be feasibe for arger SOCs.) The vaues used are the same as those presented in Tabe 1. And the eimination criteria ² for the : 0 0 ± approach is chosen to be zero. Reca that the exhaustive evauation approach aways resuts in optima resuts, athough at the expensive of greater computation time. It is seen that the : 0 0 ± procedure aso gives optima resuts for a but one case with a much ower computation time. In Tabe 4, and represent the number of combinations evauated to arrive at the resuts, and ë represents the combination of core sharing seected. is aways 26, since there are a tota of 26 combinations. The ower bound on is 4, since the best combinations of four groups have to be evauated. It is seen that the reduction in the number of combinations evauated is significant even for the cases where 0 0 ± yieds optima resuts. The percentage reduction in ü ½ ý the number of evauations is aso reported ( ü ). ½ ý + On an average, the : 0 0 ± procedure takes 6 minutes to compete on a SunW Utra 10, whereas the exhaustive approach requires approximatey 20 minutes to compete. 7 Concusion We have presented a resource optimization technique and a costoriented optimization heuristic to reduce the overa test cost of mixedsigna SOCs. In the resource optimization approach, we show that mutipe anaog cores can share anaog test wrappers to reduce the area overhead. The cost-oriented optimization approach uses a we known TAM optimization approach together with the anaog wrapper optimization technique to give a cost efficient TAM architecture and test schedue for a mixed-signa SOC. We have aso presented transistoreve simuation resuts to demonstrate the feasibiity of the anaog test wrappers. We have presented experimenta resuts demonstrating that the test cost can be reduced significanty, using the proposed optimization techniques. As part of future work, we are studying ways of refining the cost measure based on the knowedge of core pacement. We are investigating the cost of testing the data converters in the anaog test wrappers. We are working with industria partners to appy this method to rea-ife mixed-signa SOCs. References [1] T. amamoto et a. A mixed-signa 0.18-m CMOS SoC for DVD systems with 432-MSampe/s PRML read channe and 16-Mb embedded DRAM. In IEEE JSSC, vo. 36, pp , [2]. Kundert et a. Design of mixed-signa systems-on-a-chip. In IEEE TCAD, vo. 19, pp , [3] B. Koupa, T. Lee and B. Gravens. Buetooth singe chip radios: hoy grai or whie eephant. two chip.pdf. [4]. Zorian, E. J. Marinissen and S. Dey. Testing embedded-core-based system chips. IEEE Computer, vo. 32, pp. 2 60, June [] A. Sehga, S. Ozev and K. Chakrabarty. TAM optimization for mixed-signa SOCs using anaog test wrappers. In Proc. IEEE ICCAD, pp. 9 99, [6] V. Iyengar, K. Chakrabarty and E. J. Marinissen. On using rectange packing for SOC wrapper/tam co-optimization. In Proc. IEEE VTS, pp , [7] E. J. Marinissen, V. Iyengar and K. Chakrabarty. ITC 02 SOC test benchmarks web site. [8] S. D. uss and R. S. Gyurcsik. Optima ordering of anaog integrated circuit tests to minimize test time. In Proc. IEEE, pp , [9] L. Mior and A. L. Sangiovanni-Vincentei. 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