Top Down Design of Joint MODEM and CODEC Detection Schemes for DSRC Coded-FSK Systems over High Mobility Fading Channels

Transcription

1 Top Down Design of Joint MODEM and CODEC Detection Schemes for DSRC Coded-FSK Systems over High Mobiity Fading Channes Juinn-Horng Deng, Feng-Chin Hsiao, and Yi-Hsin Lin Department of Communications Engineering Yuan Ze University 135 Yuan-Tung Road, Chung-Li, Taiwan E-mai: Abstract The joint detection and verification of frequency shift keying (FSK) moduation and demoduation (MODEM), Manchester coding and decoding (CODEC) schemes are proposed for dedicated short range communication (DSRC) systems over high mobiity fading channes. The proposed joint coded-fsk detection scheme with ow compexity benefit can outperform the conventiona separated coded-fsk detection scheme. It is due to the joint scheme with time diversity gain to enhance the detection performance. Moreover, the proposed joint agorithms with foating-point and fixed-point designs are verified in the software-defined-ratio (SDR) patform. Based on the measurement resuts via SDR equipments, it is confirmed that the impementation of VHDL hardware circuit design of the proposed joint detection scheme can provide robust performance over high mobiity Rician mutipath fading channe environment. Keywords frequency shift keying (FSK) modem, dedicated short range communication (DSRC), coding and decoding (CODEC), software-defined-ratio (SDR). I. INTRODUCTION Recenty, the dedicated Short Range communication (DSRC) systems [1]-[2] have drawn a ot of attention for high speed vehicuar communications. For the DSRC system, the ASK and FSK moduations with FM and Manchester encoders are the mandatory techniques, which can provide for high data rate and high mobiity communications. In this paper, we wi focus on the FSK moduation and demoduation (MODEM), and Manchester coding and decoding (CODEC) design to enhance the transceiver performance. For the conventiona detection scheme, the demoduation and decoding schemes are separated to detect the origina transmit signa for DSRC system [3]. However, for the separated receiver, the BER performance woud be degraded due to the time-varying fading channe and noise effects. In order to combat the probem, we propose a joint MODEM and CODEC schemes to enhance the detection performance, decrease the energy ose, and reduce the computationa compexity. Moreover, we evauate the BER performance of the foating-point and fixed-point designs for the proposed joint detection schemes. Next, we estabish a software-defined-ratio (SDR) patform and measure the experimenta resut to confirm the feasibiity of the above proposed scheme. The SDR patform incudes transmitter and receiver equipments, i.e., aptops, WARP FPGA modues [4], WARP DAC/ADC modues, WARP RF Up/Down converter modues, and mobie fading channe equipments. That is, aptops are used to transmit coded-fsk signa which is designed by MATLAB software. Next, the baseband signas are buffered in WARP FPGA modue. Then, the anaog and RF transmitted signas are generated by WARP DAC and RF Up converter modues. Furthermore, the RF signa is faded by the high mobiity channe which is generated by channe emuator. At the receiver, the WARP RF down converter and ADC modues are used to transfer the faded signa back to baseband signa. In the end, the digita signa can be received by aptop via Ethernet cabe. Therefore, the MATLAB software can be used to design the joint demoduation and decoding agorithms and detect the origina transmitted signa. However, For the DSRC systems, many iteratures [5]-[7] are proposed to use SDR techniques to verify or impement the vehice communications. They are ony used for the computer simuation, FPGA modue verification, or DSP modue evauation, which are different from the proposed SDR patform. That is, our proposed SDR patform can reaize the overa communication system, which invoves the rea time baseband signa generation, RF up/down converters, mobie fading channe effect, and the received baseband signa processing. To the best of our knowedge, there is no pubication paper proposed joint MODEM and CODEC schemes with SDR patform verification for DSRC coded-fsk system. Finay, based on the above simuation and verification resuts, the hardware design structure is proposed and impemented by VHDL hardware circuit design. The proposed structure invoves the advantage of ow computationa compexity, i.e. the ower sices and mutipies in impementation. After the impementation of the FPGA hardware modues, it confirms that the proposed agorithms and hardware design structure can be robust reaization in the DSRC system over high mobiity environments. Summariy, it is noteworthy that the top down design scheme of the proposed system invoves with three contributions. Firsty, the joint MODEM and CODEC schemes are proposed to enhance BER performance. Secondy, the SDR patform with

2 equipments, hardware modues and aptops is estabished to measure the detection performance of the proposed scheme over high mobiity fading channe. Thirdy, a hardware design structure with ow computationa compexity is proposed and impemented to confirm the proposed detection scheme with robust performance. II. JOINT MODEM AND CODEC DESIGN FOR DSRC CODED-FSK SYSTEM Consider a DSRC system over high mobiity fading channes. The overa schematic diagram of DSRC coded- FSK transceiver is depicted in Fig. 1. Fig. 1 Transceiver bock diagram of the proposed joint MODEM and CODEC design for DSRC coded-fsk systems. (a) Transmitter. (b) Receiver. At the transmitter, a source data d(n), n=1,,n is transmitted, where data is consisted of one or zero. Then, using Manchester encoding scheme, they are encoded into s(n) signa. i.e., [ 1], if d( n) = [ s(2n 1) s(2 n) ] = (1) [1 ], if d( n) = 1 Note that the Manchester encoder generates s(n) signa with 2N size. Next, the encoding signa is moduated by FSK moduation scheme [8], i.e., m cos(2 π f ), if s( n) = 1 y( m) M (2) = m cos(2 π f ), if s( n) = 1 2 M The moduation scheme generates two different carrier frequency signas ( f 1, f 2 ) with the duration size being M for each FSK moduation symbo. Thus, the size of the FSK moduated signa of each frame transmission is 248 M. As the DSRC system, before the FSK signa is transmitted, a preambe sequence is added to use for the synchronization and channe estimation. Therefore, the overa transmitted signa is expressed by p( k), for 1 k K f ( k) = (3) y( k K), for K + 1 k K + 248* M where p(k) is the preambe sequence with the size being K and the given sequence being ±1, and y(k) is the FSK moduated signa. Finay, the transmitted signa is upsamped and convoved by shaping fiter, which can generate the band-imited transmitted signa. t( i) = ( f ( k) δ ( i ki )) g ( i) i= = f ( k) g ( i ki) i= T where I is the number of oversamping, is the convoution operation, δ ( ) is the impuse function, gt ( i ) is the SRRC fiter coefficients with ength T. Thus, the moduation and coding signa is transmitted in Fig. 1(a). Moreover, the transmitted signa is up-converted to RF band with 5.8 GHz carrier frequency. Then, it is transmitted through the timevarying mutipath fading channe [9]. After the down-convert processing, the digita received signa can be expressed by L j 2π f i ( ) = α ( ) ( τ ) + ( ) = 1 T (4) r i i t i e n i (5) where f is the carrier frequency offset, n(i) is the AWGN noise, L is the number of mutipath fading channe, τ is the deay time of mutipath, α ( i) is the time-varying fading channe response. At the receiver, the bock diagram is shown in Fig. 1(b). In (5), the transmitted signa is affected by time-varying mutipath channe fading and osciator frequency offset. In order to detect the origina transmitted signa, the we-known method is the separated demoduation and decoding schemes. In this paper, we propose a joint demoduation and decoding scheme to detect the origina transmitted signa and enhance the detection performance. The receiver design is depicted in Fig. 1(b). First, assume the preambe sequence synchronizing the start time of frame. Thus, the received signa can be designed to match the coefficients of SRRC fiter and then down-sampe the matched signa, i.e, v( i) = g ( j) r( i j) T (6) j = w( m) = v( mi ) where w(m) is the down-sampe received signa after preambe code remova. Next, the down-samping signa invoves the FSK moduation signa and the Manchester coding signa. Therefore, in order to detect the origina transmitted signa d ˆ( n ), a joint detection scheme is proposed, i.e., joint FSK demoduator and Manchester decoder : M 1 M 1 (7) x = w( m)cos2 π f m/ M+ w( m+ M)cos2 π f m/ M m= m= M 1 M 1 (8) x = w( m)cos2 π f m/ M+ w( m+ M)cos2 π f m/ M m= m= 1, if x < x 1 2 dˆ( n ) = (9), if x x 1 2 In the above equations, x 1 and x 2 are the match fiter (MF) output signas for different reference signas consisted by different FSK moduation and Manchester encoding signas. Finay, depending on the MF output energy, we can easiy acquire the detect signa. In next simuation and verification section, the foating/fixed point simuation and the SDR patform verification are performed to confirm the proposed joint detection scheme.

3 III. JOINT MODEM AND CODEC CIRCUIT DESIGN FOR DSRC CODED-FSK SYSTEM In previous section, the joint MODEM and CODEC agorithms are proposed. Next, we wi propose the joint MODEM and CODEC circuit design with ow compexity advantage to reaize the proposed agorithm. First, the transmitter bock diagram is shown in Fig. 1(a). For the hardware design and test, the origina data is buffered in ROM with the memory size. Then, the source binary data (N=124) can be acquired by the controer and paraeto-seria processing of the ROM output data. It is shown in Fig. 2. paper, we proposed that the sub-coefficients of fiter are seected and outputted by controer, simutaneousy. Next, the sub-coefficients are mutipied by the transmitted data with different deay time. Then, using the adder to combine the different deay output data for the band-imited signa transmission, the proposed structure is shown in Fig. 6. It is noteworthy that, for exampe oversamping size being I=5 and fiter coefficient size being T=3, the number of mutipier of the conventiona FIR scheme is about 3. However, the proposed scheme ony utiizes the 6 mutipiers, which is a ow compexity design structure. Based on the above design procedures in Figs. 2-6, we can impement the joint FSK moduation and Manchester coding transmission scheme. Fig. 2 The bock diagram of binary source data generator. Next, the binary data is encoded by the Manchester encoder in (1), which encoder generates the switching data between (1, ) and (, 1). It can be impemented by inverter, mutipexer, and controer, which is shown in Fig. 3. Moreover, the encoded data is mapped for different frequency moduation, i.e., cos(2 π f1m / M ) and cos(2 π f2m / M ). That is, the two ROM memories with singe cosine periodic waveform and mutipexing scheme are designed to impement the FSK signas, which are controed by encoder output data. The impement structure is depicted in Fig. 4. Note that if the coded-fsk moduation scheme is designed by the conventiona finite impuse response (FIR) fiter, it wi induce mutipe mutipies to reaize the FSK signas. However, for the proposed scheme, we don t use any mutipier which obviousy performs the benefit of the ow computationa compexity. Fig. 3 The circuit design bock diagram of Manchester encoder cos 2 π f m / M cos 2 π f m / M 1 2 Fig. 4 The circuit design bock diagram of FSK moduation. Next, as shown in Fig. 5, the frame data is constructed by inserting the preambe code into the FSK moduation data. It can be designed by the ROM memory with preambe code, mutipexing, and controer schemes. Finay, at the transmitter, the oversamping and shaping fiter schemes need to impement for the band-imited transmitted signa requirement. For the convectiona scheme, FIR fiter is often used to impement the band-imited signa generation. In this Fig. 5 The circuit design bock diagram of Frame data generator Fig. 6 The circuit design bock diagram of over-samping and shaping fiter. For the receiver side, the bock diagram is shown in Fig. 1(b). First, the received signa is fitered by the shaping coefficients and down-samped to acquire the symbo-based received signa. The received agorithm is described in (6). On the basis of (6), it can be simpy impemented by FIR fiter. However, the conventiona FIR fiter design invoves mutipe mutipiers to convove the received signa, which induces arge computationa compexity. In order to reduce the computationa compexity, we propose the nove fiter structure that the fiter coefficients with the different deay time are mutipied by the received signa, simutaneousy. Next, the mutipied signas are combined by accumuator. Then, the controer and mutipexing schemes are designed to down-sampe the parae output sub-fiter data. The proposed design structure is shown in Fig. 7. It obviousy reveas that a few mutipier designs can reaize the shaping fiter and down-samping schemes.

4 Tabe 1 Simuation parameters for the DSRC coded-fsk systems. Simuation Parameters Setting Moduation Method FSK Encoder Type Manchester Packet Data Length 124 bits Sinusoida Frequency Shifting f 1=1MHz f 2=2MHz Oversamping Size 5 Shaping Fiter Length 3 Mutipath Channe Type 2 Path Rician Veocity of Mobie Fading Channe 1Km/Hr Fig. 7 The circuit design bock diagram of down-samping and shaping fiter Next, as shown in Fig. 1(b), the down-samped data needs to be demoduated and decoded by the proposed joint processing technique, which the agorithms are proposed in (7)-(9). In order to reduce the computationa oading, the two ROM memories with the different frequency shifting waveforms being 2M size, i.e., [cos(2 π f1m / M ) cos(2 π f2m / M )] and [cos(2 π f2m / M ) cos(2 π f1m / M )], are used to impement the demoduation and detection schemes of the receiver. That is, using two ROM memories, mutipier, accumuator, I/Q adder, and comparator can impement the joint demoduation and decoding techniques, which is shown in Fig. 8. Note that, the two branches of integrating output data are performed the noncoherent matched fiter of FSK signas, which sti can be impemented by the conventiona FIR fiters with arger mutipiers. However, for the proposed joint detection design, it can provide ow computationa compexity advantage. Overa, the ow compexity transceiver design of the joint FSK MODEM and CODEC system is proposed in the impementation section. In next section, the impementation resuts wi confirm the performance of the proposed circuit design structure.. Next, for a simuations, we assume the idea frame synchronization. The proposed transceiver performance is evauated for the foating-point and fixed-point system design over high mobiity fading scenarios. Moreover, we estabish the SDR patform, which can generate a high mobiity Rician fading channe and verify the joint detection agorithm. Finay, VHDL hardware circuit is designed to reaize the proposed impementation structure of the joint MODEM and CODEC scheme in Section 3. Then, FPGA patform is used to confirm the hardware design circuit with an efficient impementation and ow compexity Computer Simuation In the first set of simuations, the bit error rate (BER) performance of the proposed joint MODEM and CODEC schemes over time-varying fading channe with mobiity 1 Km/Hr is shown in Fig. 9. The simuation resuts are evauated by the foating-point design for the proposed system. For the circe ine, it is the BER performance of the conventiona separated FSK MODEM and Manchester CODEC schemes. The BER performance of the proposed joint scheme is shown in the square ine, which obviousy provides better performance than the conventiona method due to the joint detection being robust to noise and fading channe effects. 1 FSK(Sepa rate MODEM and CODEC) FSK(J oint MODEM a nd CODEC) 1-1 [cos2 π f m/ M cos2 π f m/ M] 1 2 BER 1-2 [cos2 π f m/ M cos2 π f m/ M] 2 1 Fig. 8 The circuit design bock diagram of joint FSK demoduation and Manchester decoding. IV. SIMULATION AND IMPLEMENTATION RESULTS In this section, simuation and impementation resuts are demonstrated to confirm the performance of the proposed joint MODEM and CODEC transceiver design of the DSRC coded-fsk systems. The simuation parameters of the DSRC coded-fsk systems are summarized in Tabe Eb/N (db) Fig. 9 BER performance as a function of Eb / N for the proposed joint MODEM and CODEC detection scheme, and the conventiona separated MODEM and CODEC detection scheme. In the second set of simuations, we consider the different fixed-point design for the proposed system over high mobiity 1 Km/Hr scenario. As shown in Fig. 1, when the number of the fixed-point design is decreased, the BER performance is degraded. Especiay, the degradation of the 4 bits fixed-

5 point design is more serious than other bits. It is because the truncated received signa cannot be efficienty matched by the FSK reference waveforms. For the ow compexity and robust performance issues, the 6 bits fixed-point design can be considered for the hardware circuit design to impement the proposed joint detection system. BER FSK (Mobiity 1Km/Hr, Fixed-Point 4 bits) 1-4 FSK (Mobiity 1Km/Hr, Fixed-Point 5 bits) FSK (Mobiity 1Km/Hr, Fixed-Point 6 bits) FSK (Mobiity 1Km/Hr, Fixed-Point 8 bits) 1-5 FSK (Mobiity 1Km/Hr, Fixed-Point 1 bits) FSK (Mobiity 1Km/Hr, Foating-Point) Input SNR (db) Fig. 1 BER performance as a function of Eb / N for the foating- point and fixed-point design of the proposed joint detection scheme over high mobiity fading channes Equipment-Based SDR Patform Verification To verify the feasibiity of the proposed joint MODEM and CODEC detection scheme, SDR patform is estabished by equipments, radio-board modues, and aptops. The bock diagram of the SDR patform with time-varying fading channe emuator is shown in Fig. 11. The SDR patform consists of aptops, WARP FPGA modues, WARP DAC/ADC modues, WARP RF Up/Down modues, and mobie fading channe equipments (Eektrobit Propsim C2 hardware channe emuator [1]). Fig. 11 The bock diagram of design structure of SDR patform. The SDR patform can assist us in verifying the performance of the proposed software agorithms in Section 2. Moreover, the transmitted coded-fsk signa can be generated by the MATLAB program in aptop. Then, the digita signas can be downoaded into WARP FPGA modue by Ethernet cabe. Next, the anaog and RF signas wi be up-converted by WARP DAC & RF modues. Thus, the RF signa can be fed into C2 fading channe emuator to perform the mobie fading signa. At receiver side, the WARP RF modue downconverts the RF mobie fading signa to the anaog baseband signa. Next, the anaog signa can be samped by the WARP ADC modue to generate the digita signa. Then, the digita signa can be buffered in the WARP FPGA modue and transferred to aptop by Ethernet. Finay, the digita received signa with the joint coded-fsk data via SDR transceiver patform can be synchronized, equaized, detected by the proposed receiver MATLAB software program. Based on the previous SDR design procedures, we can verify the performance of the proposed agorithms in Section 2 over Rician mobie fading channe environment. The overa SDR hardware patform is shown in Fig. 12. Using the SDR patform, the frame error rate (FER) performance resuts of the foating-point and fixed-point coded-fsk signa detection are shown in Tabe 2. For the evauation scenario, the two path mobie Rician fading channe, i.e. 1 Km/Hr, are generated by the C2 channe emuator. Note that, as shown in Tabe 2, the foating-point and 6 bits fixed-point design can obviousy provide better performance than the 4 bits fixedpoint design. Moreover, the SDR patform can assist us in confirming the 6 bits fixed-point design for the proposed joint scheme with exceent performance and provide the ow computationa compexity. Laptop Scope WARP FPGA & ADC/DAC & RF Modues C2 Mobie Channe Emuator Fig. 12 The hardware prototype of SDR patform. Laptop Tabe 2 Frame error rate of the proposed joint detection scheme. FSK Mode SNR (db) FER of 4bits Fixed Point FER of 6bits Fixed Point.56.4 FER of Foating Point.48.3 Spectrum Anayzer 4.3. VHDL Hardware Circuit Design and Impement After the simuation and verification of the above Subsections 4.1 and 4.2, the 6-bits fixed-point design is confirmed for the quantization bit of the hardware circuit impementation of the proposed joint detection scheme. First, on the basis of the hardware structure of the joint MODEM and CODEC schemes in Section 3, we design the VHDL hardware code to reaize in Xiinx Spartan 3 FPGA chip, which can operate in 4MHz cock rate. Based on the FPGA pace and route circuit mapping and the component utiization rate in Tabe 3, it can confirm the transmitter circuit design with ow computationa compexity, i.e., sices 2% and mutipies 3% utiization rate. Moreover, we design the VHDL hardware circuit and impement in Xiinx Spartan 3 FPGA chip for the joint transceiver structure in Section 3. Simiar, the circuit mapping resut of FPGA pace and route in Fig. 13 and utiization rate resut of FPGA components in Tabe 4 sti provide ower compexity performance for the overa transceiver design, i.e., sices 55% and mutipies 6%. Finay, as shown in Fig. 14, the joint demoduation and decoded data is performed to consist with the origina transmitted data, i.e, the goden testing pattern 55, AA, 1, 2,. Besides, Fig. 14 shows the deay resut between the

6 transmitted data and the received detect data, which is due to the hardware circuit processing deay time. After the above three parts anaysis and verification, they confirm that the proposed joint MODEM and CODEC system can provide better performance and ower computation resut, which can satisfy the requirement of the DSRC system used for high mobiity fading channe environments. V. CONCLUSIONS The joint detection design and evauation of the MODEM and CODEC schemes for DSRC coded-fsk system are proposed in this paper. After computer simuation, SDR patform verification, and VHDL hardware design impementation, the proposed system can provide better BER performance and ower computationa compexity than the conventiona separated detection system. Furthermore, the proposed system can perform the efficiency of the robust detection over high mobiity Rician fading channe environments. ACKNOWLEDGEMENTS This work is sponsored by the Nationa Science Counci, R.O.C., under Contract NSC E Fig. 13 FPGA pace and route circuit mapping for the proposed transceiver VHDL circuit design. Fig. 14 FPGA impementation resut of the proposed VHDL circuit design of the joint MODEM and CODEC scheme. Tabe 3 Component utiization rate of the proposed transmitter circuit design in Xiinx Spartan 3 FPGA chip. Design Summary Report Eements Utiize Number Utiization Rate Sice Fip Fops 215 out of % 4 input LUTs 246 out of % MULT18X18SIOs 6 out of 2 3% bonded IOBs 32 out of 158 2% Sices 13 out of % BRAMs 2 out of 2 1% GCLKs 1out of 24 4% REFERENCES [1] K. Kwon, J. Choi, Y. Hwang, K. Lee, and J. Ko, A 5.8GHz integrated CMOS dedicated short range communication transceiver for the Korea/Japan eectronic to coection system, IEEE Trans. on Microwave Theory and Techniques, vo. 58, no. 11, pp , Jan [2] J. B. Kenney, Dedicated short-range communications (DSRC) standards in the United States, Proceedings of the IEEE, vo. 99, no. 7, pp , Juy 211. [3] ML58 Datasheet, 5.8GHz ow-if 1.5Mbps FSK transceiver, Micro Linear Corporation, Mar. 24. [Onine]. Avaiabe: [4] Rice Univ. Wireess Open-Access Research Patform Project. [Onine]. Avaiabe: [5] J. Mar, C. C. Kuo, Y. R. Lin and T. H. Lung, Design of software defined radio channe simuator for wireess communications: Case study with DSRC and UWB channes, IEEE Trans. Instrum. Meas., vo. 58, no. 8, pp , Aug. 29. [6] Umemoto, An experimenta DSRC mutimode termina using software defined radio technoogy, IEEE Radio and Wireess Conference, pp , 21. [7] A. Bakhraiba, et a., Digita moduation identification in terms of software defined radio for traffic management system, IEEE Nationa Conference on Teecommunication Technoogies, pp , 28. [8] J. G. Proakis, M. Saehi, and G. Bauch, Contemporary Communication Systems Using MATLAB, PWS Pubishing Company, pp , 27. [9] C. Meckenbrauker, A. Moisch, J. Kareda, F. Tufvesson, A. Paier, L. Bernado, T. Zemen, O. Kemp, and N. Czink, Vehicuar channe characterization and its impications for wireess system design and performance, Proceedings of the IEEE, vo. 99, no. 7, pp , Juy 211. [1] Eektrobit Propsim C2 hardware channe emuator. [Onine]. Avaiabe: Tabe 4 Component utiization rate of the proposed transceiver circuit design in Xiinx Spartan 3 FPGA chip. Design Summary Report Eements Utiize Number Utiization Rate Externa IOBs 73 out of % BUFGMUXs 1 out of 24 4% MULT18X18SIOs 12 out of 2 6% RAMB16s 7 out of 2 35% Sices 2589 out of % SLICEMs 92 out of %