ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-ends: a Power and Performance Perspective

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1 ADC Precision Requirement for Digita Utra-Wideband Receivers with Subinear Front-ends: a Power and Performance Perspective Ivan Siu-Chuang Lu Nei Weste Sri Parameswaran Dept. of Computer Science & Eng. Dept. of Eectronics Dept. of Computer Science & Eng. The University of New South Waes Macquarie University The University of New South Waes Kensington, NSW, Austraia North Ryde, NSW, Austraia Kensington, NSW, Austraia e-mai: ivan@cse.unsw.edu.au nweste@bigpond.net.au sridevan@cse.unsw.edu.au Abstract This paper presents the power and performance anaysis of a digita, direct sequence utra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signa to noise and distortion ratio (SNDR) and bit error rate (BER) were evauated with varying degrees of front-end inearity and anaog to digita converter (ADC) accuracy. The anaysis and simuation resuts indicate two or more ADC bits are required for reiabe data reception in the presence of strong interference and intermoduation distortion. In addition to BER performance, power consumption of different hardware configurations is aso evauated to form the cost function for evauating design choices. The combined power and performance anaysis indicates that starting with one-bit ADC resoutions, a substantia gain in reiabiity can be attained by increasing ADC resoution to two-bits or more. When the ADC resoution improves beyond three bits, front-end inearization achieves simiar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a resut, inear front-end designs become significant ony when high precision ADCs are utiized.. Introduction The UWB radio is a new technoogy that continues to generate considerabe interest for its usage in both miitary and consumer communication appications. Recenty, severa standards based on puse and orthogona frequency division mutipexing (OFDM) have been proposed to reaize UWB wireess persona area networks. By communicating via short nanosecond puses, puse based UWB systems promise ow power, high data rate communication whie providing fine mutipath resoution in the time domain, unmatched by existing narrowband systems []. Currenty, commercia UWB appications have been approved by the Federa Communications Commission to operate in the 3 to GHz band under a power emission imit of dbm/mhz. Athough its operating distance is restricted, power imited UWB signas can ead to ow power, high performance impementation of the front-end circuitry. For traditiona high power, narrowband radio systems, non-inearity in the receiver front-end generates undesirabe distortion, eading to in-band and adjacent channe interference. As a resut, reiabe performance can be obtained ony through the use of highy inear anaog front-ends []. For puse based UWB systems, the received signa is broadband with ow peak to average power ratio. Therefore, stringent front-end inearity requirement of narrowband receivers may no onger be necessary. The authors in [3] have demonstrated that puse doubets can be used to mitigate non-inearity induced distortion. Thus, radio frequency (RF) circuits can be greaty optimized for other performance metrics such as noise, power and gain by trading off inearity. Area savings derived from reduced inearization circuitry aso drive down production cost and offer greater commerciaization advantages. However, the anaysis presented in [3] was ony appicabe to anaog correation based receivers since the impact of ADC quantization on puse doubets was not evauated. Digita UWB receiver architectures have been proposed by [4, 5] as digita correation offers considerabe fexibiity and technoogy r(t) BPF Frontend X LNA a(t) X LO VGA FILTER I Stream b(t) x[i] ADC Reference PLL ADC Q Stream Digita RX Processing ` Timing / RF Contro Figure : Digita UWB receiver system diagram scaing benefits. An exampe of a digita receiver is shown in Fig.. The ADC is a key bock in the digita receiver chain, having a arge impact on overa power dissipation and system performance. Due to the wide bandwidth of the UWB puse, the ower bound imposed by the Nyquist theorem on the samping rate is typicay in the GHz range. Efficient impementations of such high speed ADCs mandate the use of fash architectures which exhibit an exponentia increase in comparator area and power with the resoution specification. State of the art fash ADCs reported in [6], [7], and [8] have a maximum resoution of six bits whie consuming significant power and occupying substantia chip area. Steep tradeoffs between the ADC s performance and impementation costs have prompted authors in [4, 5] to investigate the minimum precision necessary to maintain accurate data detection. Authors in [4] have shown that four bits are sufficient for reiabe detections of UWB signas under both additive white gaussian noise (AWGN) and narrowband interference (NBI) dominated cases. In contrast, authors in [5] proposed that ony a singe bit is required under severe NBI. Their anaysis concentrate mainy on system reiabiity without evauation of power usage. In addition, the effect of ADC precision on digita UWB systems working with subinear front-ends and possibe trade-offs with inearity are yet to be addressed. This paper presents, for the first time, digita UWB system s SNDR and BER performance considering interference power and frequency, ADC precision, and RF circuit non-inearity characteristics. When combined with detaied power anaysis, we demonstrate that at east two quantization bits are necessary to maintain accurate detection. Furthermore, our investigation indicates that carefu trade-off between front-end inearity and ADC accuracy is required when designing UWB receivers with power and performance. This paper is organized as foows. In section, we describe the receiver inearity mode using Tayor-series anaysis, foowed by an introduction to the UWB receiver system mode. Mathematica equations are formuated in section 3 to investigate SNDR and BER performance in the presence of NBI, under varying circuit nonineariy and ADC precision. Section 4 estimates power usage for the ADC and common front-end components such as ow noise ampifiers(lna), mixers and baseband ampifiers. The theoretica formuas presented in Sections 3 and 4 are empoyed in Section 5 to anayze the tradeoffs between power consumption, inearity and ADC precision. Pareto optima configurations in the fu design space are then Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE

2 evauated and discussed. Concusions are drawn in Section 6.. System Mode. Non-inearity Mode RF circuits commony behave in a weaky non-inear fashion under norma operating conditions and have been anayzed using different techniques in the iterature [9, ]. In this paper, we empoy a non-inear memory-ess mode for anaog circuits with no frequency dependency, which can be characterized as foows: Y (t) =α α x(t)α x(t) α 3x(t) 3... () x(t) is the input to the system and α ns are the n th order coefficients of non-inearity. The effect of non-inearity can be observed by setting the input to two signas with ampitudes V f and V f,and frequencies ω f and ω f respectivey: π π V in = V f cos(ω f t)v f cos(ω f t), The output V out = V fund V harmon V IM wi contain undesired harmonic and intermoduation components not present in the input. Due to the wide bandwidth occupied by UWB signas, these component often appear in the operating band and corrupt the signa of interest. The strength of the intermoduation products can be measured by the input third order intermoduation intercept point: 4 IIP 3 = 3 α () which is defined as the input ampitude at which the third order intermoduation tones are equa to the fundamenta tone. Non-inearity aso causes sma signa gain compression and reduces the signa gain with increasing input eve.. DS-UWB System Mode In a direct sequency utra-wideband (DS-UWB) system with N p piconets each with N u users, mutipe access within each piconet is achieved via a time division mutipe access (TDMA) scheme, whie co-ocating piconets communicate using code sequences with ow cross-correation. In the p th piconet, user k s DS-UWB transmitted puse train using bi-phase moduation is α 3 N c u p k (t) = f p j β kw(t jt f c k j T c) (3) j= N c is the tota number of puses in the puse train, j is the puse number, T f is the frame time, T c is the chip duration and c k j is the k th user s random hopping sequence. The transmitted Gaussian monopuse is bi-phase moduated by binary data sequence β k and piconet code sequence f p j for pth piconet to form the transmitted signa. This signa is processed by the receiver shown in Fig. The received signa at the output of the antenna-fiter submodue can be characterized as: r k (t) = ( A k u p k (t τ k)i(t)n(t) ) h RF (t) (4) A k u p k (t τ k) is user k s received UWB signa with ampitude A k after deay of τ k and N I(t) = V n(t)cos(ω fn t φ n(t)) n= represents the narrowband interferences with ampitude V n(t), frequency ω fn and random phase φn(t), whie n(t) is the white channe noise with variance contributed by the temperature and the fiter Π bandwidth. Symbo denotes the convoution operation and h RF (t) is the impuse response of the pre-seect fiter. The received signa r k (t) is then ampified by the non-inear wideband LNA. Due to r k (t) being a combination of periodic and stochastic signas, precise mathematica representation of the signa at the output of the non-inear system is non-trivia. However, it is not difficut to see that the output wi consist of a inear repica of the input signa and an error signa. The inear repica contains ony the desired fundamenta terms. The error signa is introduced by the noninear response, producing strong narrowband spectra components and distortion from the stochastic signas. Without oss of generaity, ony the I channe of the receiver is examined. After down conversion and baseband gain and fitering stages, a baseband signa b k (t) is produced: b k (t) = [ ] a k (t)v fc cos(ω fc t φ(t)) h LP (t) (5) a k (t) is the signa from the output of the LNA, and f c is the centre frequency of the desired UWB signa. This baseband signa b k (t) is then samped and quantized by the ADC, producing signa X[i] which is digitay correated with the tempate signa to compute the decision statistic d. Each of the LNA, down-conversion mixer and baseband gain stages are modeed by a Tayor series with non-inear coefficients set by overa receiver IIP 3 and gain requirements. The next section wi formuate the reationship between distortion and ADC precision in order to examine their impact on system SNDR and BER. 3. ADC Performance Anaysis After the digitization process, signa at the output of the ADC can be expressed as: X[i] =S[i]I[i]N[i]Q[i] (6) each of the variabes X, S, I, N and Q are vectors of ength T s, = N ct f is the capture window ength and T s is the T samping interva of the ADC. Hence, S =[s[] s[] s[n f c T s ]] and represents sampes of the desired UWB puse. I represents the narrowband interference and distortion effects due to front-end noninearity. N is the Gaussian therma noise introduced by the channe with variance set by the temperature, noise figure, power gain and the bandwidth of the front-end circuitry. The ast term Q represents the quantization error of the ADC due to the finite accuracy of digitization. Assuming an idea automatic gain contro circuitry and ADC, Q is gaussian with variance of V sb,v sb = X Q is the b quantization step size. After correation against a tempate signa T [i], the digita correator produces decision statistic d m for user k s m th received symbo. Without oss of generaity, perfect synchronization between the tempate and the received signa is assumed and the decision statistic of the first symbo is expressed as : d = Ts Ts s = X[i] T [i] = s I n m q (7) β k (α χ)a k f p j w[i] A kf p j w[i] (8) corresponds to the signa portion at the output of the correator and evauates to s = N c(α χ)a kβ k R ww (9) R ww = Ts w[i] w[i] is the autocorreation function of the received waveform and χ = 3 4 α3a3 k 3 N α3a k Vn () n= Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE

3 is the signa compression factor and is a function of the 3 rd order non-inearity coefficient α 3, number of narrowband interferers, and their maximum signa strength. The term Ts I = ξ[i jt f c k j T c] f p j w[i] () accounts for the effect of externa interferences and their higher order harmonics and intermoduation products. The next term n is the channe s noise contribution to the decision statistic and the fina term q represent the contribution of the quantization error to the correation vaue. The SNDR for the first symbo at the output of the correator is defined as: SNDR = s E[σ ]σ σ I n q The signa energy of the received UWB signa is () s = N c (α χ) A 4 kr ww (3) The distortion contribution at the output of the correator is represented by the variance of I : σ I = E(I )= α A k Ts R ξξ R ww (4) T s This variance vaue changes upon the hopping sequence c k j which is changed every symbo. Due to the non-static nature of σ I,the expected vaue of this variance is used in the SNDR cacuation. Since noise has a Gaussian distribution and each of the j th chip s samped noise is independent of each other, the variance of n is computed as σ n = KTB N cαa kr ww (5) Finay, quantization noise is assumed Gaussian and uncorreated with a other noise and interference terms. Therefore, ADC s quantization noise power equates to σ q = V sb Ncα A kr ww (6) With the SNDR formuated, the BER can be cacuated as: ( ) BER = Q s E[σ ]σ σ i n q (7) Using ()-(6), Monte-Caro simuations were performed to obtain system SNDR. In the simuation environment, four. ns Gaussian doubets with a center frequency of 4 GHz and power spectra density (PSD) of -6 dbm/hz were received per data symbo. Gaussian doubets with spacing of 4 ns, as proposed in [3], were empoyed to produce spectrum nus to suppress interference and intermoduation distortion effects. The channe noise PSD was set by the 3K noise temperature and the 7 db noise figure of the receiver frontend, which simuated an SNR of 3 db in the absence of quantization error and non-inearity effects. Two externa interferers residing in the.4 GHz ISM and 5 GHz UNII bands with -4 dbm power and random phase were aso incuded. The RF pre-seect fiter contains a 3 to 4 GHZ nd order bandpass fiter and nd order notch fiters at.4 GHz and 5 GHz. Anti-aias baseband fiter was modeed using 4 th order Butterworth fiters. The simuated SNDR and the corresponding BER are potted in Fig. and Fig. 3 respectivey. It is seen in these figures that the performance of the system improves significanty with higher resoution ADCs. This demonstrates that a reasonabe ADC precision is necessary to preserve the shape of the doubets and to cance out interference effectivey. Greatest performance improvements occur when the accuracy is increased from SNDR (db) bit bit IIP3(dBm) Figure : SNDR vs IIP3 for different ADC resoution Bit error rate bit bit IIP3(dBm) Figure 3: BER vs IIP3 for different ADC resoution one to two bits. This BER improvement sowy diminishes with finer ADC resoution. The other trend that can be observed in the figures is that the BER is a decreasing function of IIP3 for a ADC resoutions. This can be expained by the system experiencing more benign intermoduation distortion and gain compression effects with a inear front-end. With ow resoution ADCs, this trend is difficut to identify as the BER is dominated by quantization error. As the number of ADC bit increases, BER is no onger imited by the quantization error, and improvement from a inear front-end grows significanty. It shoud be noted that the negative effect of inearity on SNDR and BER can be reduced by stronger fitering functions prior to the LNA. Moreover, whie the resuts obtained is specific to the conditions set in the simuation environment, the performance improvements due to increase in ADC resoution are simiar to previous work, and hence appicabe to puse based UWB systems in genera. 4. Hardware Power Estimation In this section, we investigate the power-inearity trade-off in the RF front-end, foowed by power anaysis of the fash ADC architecture. The overa receiver power is estimated and the reationship between power, inearity and ADC precision anayzed. 4. RF Front-end Power Estimation The receiver front-end shown in Fig. consists of a LNA, a pair of mixers and a pair of baseband ampifiers, a of which operate with a.8v suppy votage. We start our anaysis with MOS transistors, which is the main source of non-inearity in RF circuits and fundamenta to the accurate anaysis of front-end distortion. 4.. Transistor Mode and Noninear Coefficients Continuous MOS transistor modes presented in [] provides good accuracy in both weak and moderate inversion regions, and the drain current I d is given by X I d = K θx X =ηφ ( tn e (Vgs V th ) ) (ηφ t ) (8) (9) Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE

4 Vdd Vdd 5 L tune L tune Out IF IF- 5 In L g Degeneration LO LO- LO L s L s RF RF Id (ma) Figure 4: IIP3 vs I d for a typica.8 µm CMOS process In the equations above, K is a constant depending on the transistor size and the underying technoogy and θ approximatey modes the combined mobiity degradation and veocity saturation effects. Furthermore, φ t = kt/q is the therma votage, V gs is the gate-source votage, V th is the threshod votage, whie parameter η is reated to the subthreshod factor and determines the rate of exponentia increase of I d with V gs in the subthreshod region. The drain current i d (v gs) of the CMOS transistor mode above can be represented by a third order Tayor series expansion as i d (v gs) =α v gs α v gs α 3v 3 gs... () α n = n I d n! n V gs () Vgs=VGS are the noninear coefficients. It can be seen that () is equivaent to () defined previousy if we substitute v gs for x(t) and i d for Y (t) respectivey. From (8), (9), and (), noninear coefficients can be derived according to [] : X( θx) α = K ( θx) ( s ) α 3 = K ( 6 6θK ( θx) 4 s K X( θx) 6 ( θx) ( K ( θx) 3 ) 3 (s s ) (ηφ t) (s s ) 3 ηφ t( s )(s s ) ) () (3) s = e (vgs v th/(4ηφ t )). By Setting V gs V th to. V and varying the device W/L ratio, (), (3), (), and typica.8µm CMOS parameters obtained from [3] can be utiized to derive the reationship between IIP3 and I d. Fig. 4 shows a narrow peaking at I d =.5mA. This inearity sweet spot is the subject of ongoing research [3]. The ocation of the peaking region, however, vary significanty with process variations, making operation in the sweet spot difficut to guarantee. Ignoring this narrow peaking, the pot shows a cear positive reationship between IIP 3 and I d. Since these transistors are the fundamenta buiding bocks of the RF front-end, this inearity power trade-off is common in a front-end circuitry, as wi be evident in the subsequent sections. 4.. Low Noise Ampifier The LNA empoys a stagger-tuned architecture shown in Fig. 5(a) to obtain fat gain in the 3 to 4 GHz range. Both gain stages are inductivey degenerated common-source (CS) stages for input matching and improved inearity. Cascode transistors are incuded to improve isoation and prevent circuit instabiity. Cosed form expressions for the third-order intermoduation distortion (IM3) of a degenerated cascode CS ampifier have been derived previousy and (a) Wideband LNA Figure 5: Front-end Circuits (b) Gibert mixer interested readers are referred to [4] for detaied derivation. Using the cacuated IM3, theiip3 of a singe ampifier stage can be computed as : v IIP3= in (4) IM3 In an N stage cascaded system each stage j provideagainof G j, the overa IIP 3 can be expressed as foows []: IIP3 tot = IIP3 j N ( j= IIP3 j j G i ) (5) Fig. 6(a) iustrates the power inearity reationship for a singe CS gain stage, and the overa two-stage LNA. The first stage gain G = α Z L is cacuated with Z L set to Ω. As expected, a tradeoff between power and inearity can be observed. However, the deta improvement in overa IIP3 diminishes with increasing power due to the increasing gain in the first stage Down-conversion Mixer One of the most popuar down-conversion mixer topoogies is the Gibert ce shown in Fig. 5(b). This topoogy provides advantages such as high conversion gain and a high degree of isoation. We utiize the anaytica expressions deveoped in [] assuming a 4 GHz oca osciator (LO) with ampitude of.6 V. Note that ony the ow frequency effects are incuded in our anaysis. This is vaid because the capacitance effects at high frequency has minima impact for LO drive of up to approximatey.8v []. The switching pair s distortion behavior can be described by: b i = pi, i d = b i s b i s b 3 i 3 s (6) = TLO p i(t)sin(πf LOt) (7) T LO and p i(t) are the i th order time-varying noninear coefficients that are functions of the bias current, LO votage and the device characteristics. After cascading the switching pair with the driver stage, the tota mixer third-order intermoduation is approximated by IM3 mixer 3 ( a 3 Vin b3 a V ) in (8) 4 a b a 3 and a are the noninear coefficients of the driver stage. Using (4) and (6) - (8), IIP3 of the mixer is estimated and shown in Fig. 6(b). The pot indicates inearity improvement with increasing power for power eves beow approximatey 3 mw. Beyond that point, inearity decreases with increasing power. This is a direct resut of the combined action of the driver and the switching transistors. In the ow power region, inearity improvements of the driver transistor dominate. As the biasing power continues to increase, the existing eve of LO drive is no onger sufficient to maintain reiabe switching, resuting in inearity degradation. Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE

5 singe stage overa (a) Wideband LNA (b) Gibert mixer (c) Differentia CS ampifier Figure 6: IIP3 vs power Vref In ROM Decoder Latch Digita Out -3 Overa -4 LNA Mixer Baseband Figure 7: IIP3 vs power for RF front-end 4..4 Baseband Ampifier The baseband ampifier bock is configured as four cascaded stages of differentia pair configuration. Compex negative feedback networks are avoided in order to maximize bandwidth and aeviate potentia for circuit instabiity. In order to desensitize the overa ampifier s inearity from the gain in the first three stages, ony the ast stage s biasing power was varied. This ensures inearity improvements with increasing power consumption. Using [5], the third order harmonic distortion (HD3) of a singe stage differentia CS ampifier can be expressed as HD3 diff and the IIP3 of a singe stage is v in 3(v gs v th ) (9) IIP3 diff = v in 3HD3 (3) The overa IIP3 of the four-stage ampifier is then obtained via (3), (5) and shown in Fig. 6(c) 4..5 Overa Front-end By treating the receiver as a cascaded system consisting of the LNA, mixer and baseband ampifier, the overa front-end inearity is predicted with (5). The LNA gain G LNA = α Z L is cacuated with Z L set to.5k Ω. The mixer s oad resistance R L is set to Ω for cacuating G mixer. The IIP3 of the individua bocks and the overa front-end is potted against tota front-end power budget in Fig. 7. As expected in a cascaded system, the overa inearity is mainy restricted by the inearity of the ast stage (baseband ampifier) and the gain of the previous stages (LNA and mixer). Approximatey db enhancement in inearity can be observed when the power increases from 3 mw to 85 mw. With additiona power dissipation, gain in the LNA and mixer stages increases, resuting in gradua compression of the overa inearity. This effect is demonstrated by the diminishing inearity improvements in the high power region when compared to the ow power region. - N - Pre-Ampifier N - Comparator Figure 8: N bit fash converter architecture 4. ADC power estimation As is generay known, fash ADCs are we suited to high speed, ow resoution appications [6]. Fig. 8 shows the bock diagram of an N bit fash converter which consists of a reference adder and anaog pre-ampifiers, foowed by high speed digita comparators and decoding circuitry. The reference adder subdivides the divider reference votage in a set of N reference votages, which are compared with the anaog input signa in parae and converted to a binary code. For the purpose of estimating the power usage, the pre-ampifier and comparator stages are examined. The anaog pre-ampifier often assumes a differentia pair structure to provide gain and minimize the effect of kickback noise from the subsequent comparator stage [6]. In the power estimation, it is assumed that the pre-ampifier used for a singe bit is biased with I d of 5µA. A factor of four increase in power for every bit increase in ADC accuracy is necessary because of device matching considerations [7], yieding the foowing expression for the power of the pre-ampifier: P preamp =( N ) V dd I d (3) Estimation of the digita comparator array s power have been formuated in [8] and [9]. Comparisons between the two work with pubished ADCs found [8] to be more accurate for integrated ADCs, and its power estimation formua is: P comp = α V dd β V swing η V dd L min f sampe (3) α =.5, β =.3, andη =3. x 3 are empirica coefficients found in [8]. L min is the effective transistor ength, f sampe = GHz is the samping speed and ENOB is the effective number of bits. In practice, an ADC s ENOB deviates sighty from the number of bits in the ADC specification due to impementation oss. Therefore, N can be substituted for ENOB with sufficient accuracy for power estimation purposes. Summation of the comparator and pre-ampifier power produces the tota power for each of the ADCs in the I and Q streams of the receiver. Mutipying by two wi produce the overa ADC power as shown in Fig. 9 Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE

6 6-3 Power (mw) bit bit 3 4 ADC bit Figure 9: Tota ADC power consumption 4.3 Overa Receiver Power Estimation The compete receiver power for different ADC resoutions and front-end inearity is shown in Fig. and demonstrates that the ADC s power dissipation is substantia even with ony one or two bit accuracy. Further improvements in the ADC accuracy increase the power usage beyond mw, dominating the overa receiver power. 5. Power and Performance Anaysis In this section, the resuts obtained in section 3 and section 4 are summarized to investigate the trade-off between inearity and ADC accuracy with regards to their effects on system BER and power budget. Shown in Fig. is the power consumption potted against BER performance for a possibe configurations in the design space. From this graph, suitabe architectura choices can be made based on the specific constraints of particuar appications. For appications such as a high speed wireess home theater, high quaity of service must be maintained, three or four bit ADCs are necessary. In contrast, a ow rate, battery operated sensor can toerate higher BER in exchange for ower power dissipation and extended battery ife. The Pareto optimum points iustrate the best configurations for any given combination of power consumption and BER performance. Cose examination of these Pareto points revea that inearity are ess important for receivers empoying ow resoution ADCs, as evidenced by the fact that a subinear front-end with two bit ADC is more optima than a inear front-end with one bit ADC. However, inearity is more critica when used in conjunction with higher resoution ADCs. The Pareto points ceary indicate that a inear frontend with three bit ADCs is more power efficient than a subinear front-end with four bit ADCs. The reason behind these observations are two fod. Firsty, higher ADC resoutions resut in diminishing BER reduction and exponentia increase in power consumption. In the mean time, more accurate ADCs reduce the quantization error, and the effect of front-end inearity on BER are more pronounced. Therefore, with high resoution ADCs, improving front-end inearity is a more power effective soution to reducing the BER. 6. Concusion In this paper, the performance of digita DS-UWB systems operating with subinear anaog front-ends are evauated. The simuation resuts show that a minimum ADC resoution of two bits is necessary to obtain a reasonabe BER in the presence of interference and intermoduation distortion. Front-end inearity becomes increasingy critica for three or more bits of precision. Anaysis of the hardware power dissipation is incuded and combined with BER performance to derive the optima circuit configurations. It is shown that tradeoffs in front-end inearity and ADC precision exist and can be utiized to optimize system reiabiity and power consumption. 7. References [] M. Win and R. Schotz, Utra wide bandwidth time hopping spread spectrum impuse radio for wireess mutipe access communications, in IEEE Transaction on Communications., vo. 48, no. 4, Apr, pp [] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits. Cambridge University Press, Cambridge, UK, 998. [3] Removed for bind review Figure : Compete receiver power consumption Power (mw) Non Optima Points bit bit Bit Error Rate - Figure : Fu design space [4] R. B. P. P. Newaskar and A. P. Chandrakasan, A/D precision requirements for an utra-wideaband radio receiver, in IEEE Workshop on Signa Processing Systems., vo., October, pp [5] I. D. O Donne, M. S. Chen, et a., An integrated, ow power, utra-wideband transceiver architecture for ow-rate, indoor wireess systems, in IEEE CAS Workshop on Wireess Communications and Networking, Sept. [6] K. Uyttenhove and M. S. J. Steyaert, A.8-v 6-bit.3-GHz fash ADC in.5- µm CMOS, in IEEE Journa of Soid State Circuits, vo. 38, no. 7, Juy 3, pp. 5. [7] P. C. S. Schotens and M. Vertregt, A 6-b.6-Gsampe/s fash ADC in.8- µm CMOS using averaging termination, in IEEE Journa of Soid State Circuits, vo. 37, no., December, pp [8] C. Sandner, M. Cara, et a., A 6bit,.Gsps ow-power fash-adc in.3µm digita CMOS, in IEEE Design Automation and Test in Europe Conference, vo. 3, March 5, pp [9] B. C. S. Kang and B. Kim, Linearity anaysis of CMOS for RF appication, in IEEE Transactions on Microwave Theory and Techniques, vo. 5, no. 3, Mar 3, pp [] P. Wambacq, P. Dobrovon, et a., Compact modeing of noninear distortin in anaog communication circuits, in IEEE Transation on Computer-Aided Design of Integrated Circuits and Systems, vo., no. 9, Sep 3, pp [] K. S. Y. Tsividis and K. Vaveidis, A simpe reconciiation MOSFET mode vaid in a regions, in Eectron. Lett, vo. 3, March 995, pp [] M. T. Terrovitis and R. G. Meyer, Intermoduation distortion in currentcommutating CMOS mixers, in IEEE Journa of Soid-State Circuits., vo. 35, no., October, pp [3] C. P. B. Tooe and M. Coutier, RF circuit impications of moderate inversion enhanced inear region in MOSFETs, in IEEE Transation on Circuits and Systems, vo. 5, no., February 4, pp [4] C.-H. Feng, F. Honsson, et a., Anaysis of noninearities in RF CMOS ampifiers, in IEEE Internationa Conference on Eectronics, Circuits and Systems, vo., September 999, pp [5] B. Razavi, Design of Anaog CMOS Integrated Circuits, W. Stephen, Ed. McGraw-Hi, New York, NY,. [6] R. van de Passche, CMOS Integrated Anaog-to-Digita and Digita-to-Anaog Converters. Kuwer Academic Pubishers, Dordrecht, The Netherands, 3. [7] K. Uyttenhove and M. S. J. Steyaert, Speed-power-accuracy tradeoff in highspeed CMOS ADCs, in IEEE Transactions on Circuits and Systems., vo. 49, Apri, pp [8] A. Huang and P. Zhong, An architectura power estimator for anaog-to-digita converters, in IEEE Internationa Conference on Computer Design, vo., October 4, pp [9] E. Lauwers and G. Gieen, Power estimation methods for anaog circuits for architectura exporation of integrated systesms, in IEEE Transactions on Very Large Scae Integration (VLSI) Systems, vo., no., Apri, pp Proceedings of the 9th Internationa Conference on VLSI Design (VLSID 6) /6 $. 6 IEEE