l ARRANGE A SECOND PLURALITY OF Z-A STAGES TO PROVIDE A SECOND ADC CHANNEL m

Transcription

1 USOO B2 (12) United States Patent (10) Patent No.: Umann et a. (45) Date of Patent: Dec. 30, 2014 (54) CONFIGURABLE HARDWARE-SHARING USPC /143; 341/120; 341/155 MULTI-CHANNEL ADC (58) Fied of Cassi?cation Search USPC /141,143,155 (75) Inventors: Igor Umann,V111ach (AT); Christoph See appication?e for compete search history. Schneebacher, Viach (AT) (56) References Cited (73) Ass1gnee: Iggneon Technoogies AG, Neubberg Us PATENT DOCUMENTS ( * ) Notice: Subject to any discaimer, the term ofthis B1* 7/2004 A' / B1 * 5/2005 Robinson 341/143 patent is extended or adjusted under / A1 * 2/2004 Kawamura. 341/143 U_S_C_ 154(1)) by 0 days_ 2008/ A1* 3/2008 Kim eta / / A1* 5/2009 Di Giandomenico. et a /143 (21) App' NO" 13/ / A1 * 3/2011 Chen et a /143 (22) Fied: Mar. 26, 2012 * cited by examiner (65) Prior Pubication Data Primary Examiner * Howard Wiiams US 2013/ A1 Sep. 26, 2013 (74) Anomey Age or Firm * SPYYIP LLC (57) ABSTRACT (51) Int. C H03M1/00 (200601) Representatve 1mpementatons of dev1ces and techmques H0 3 M 3 /02 ( ) provide con?gurabe muti-channe anaog-to-digita conver H0 3 M 1/16 (200601) sion. In a muti-channe anaog-to-digita converter (ADC), (52) U 5 C ' one or more ADC stages may be operativey couped to a ' H03M1/004 ( ) H03M1/164 different ADC in each ofvarious operating modes. ( ) 24 Caims, 4 Drawing Sheets [ 400 First Operationa Mode ARRANGE A FIRST PLURALITY OF Z-A STAGES TO PROVIDE A FIRST ADC CHANNEL M ARRANGE A SECOND PLURALITY OF Z-A STAGES TO PROVIDE A SECOND ADC CHANNEL m Second Operationa Mode \ ADJUST THE SECOND PLURALITY OF Z-A STAGES TO OPERABLY COUPLE ONE OR MORE Z-A STAGES T0 THE FIRST ADC CHANNEL

2 US. Patent Dec. 30, 2014 Sheet 1 0f 4 oowkk Nor /\ m 690

3 US. Patent Dec. 30, 2014 Sheet 2 0f 4 wow

4 US. Patent Dec. 30, 2014 Sheet 3 0f 4 F102 CHANNEL A CHANNEL B CHANNEL C E M Q i > I_E:11:}:::E::::}1:1}1111}13/ 7 Q I Q 7 Q : > L L L ~ : / 104 I_E:1:1}:::}1:::?1:111111}13/ I Q Q Q i > L k. L i / 302 _ _ _: FIRST OPERATING MODE / 102 CHANNEL A I I / 302 CHANNEL C ' Q Q Q i > : i _ J: SECOND OPERATING MODE FIG. 3

5 US. Patent Dec. 30, 2014 Sheet 4 M4 First Operationa Mode ARRANGE A FRST PLURALITY OF Z-A STAGES TO PROVIDE A FRST ADC CHANNEL? 1 ARRANGE A SECOND PLURALITY OF Z-A STAGES TO PROVIDE A SECOND ADC CHANNEL m Second Operationa Mode ADJUST THE SECOND PLURALITY OF Z-A STAGES TO : OPERABLY COUPLE ONE OR MORE Z-A STAGES TO : THE FIRST ADC CHANNEL 406 FIG. 4

6 1 CONFIGURABLE HARDWARE-SHARING MULTI-CHANNEL ADC BACKGROUND Various types of systems may use an anaog-to-digita con verter (ADC) to convert an anaog signa originating from a sensor, for exampe, to a digita signa that can be processed by a computer, a processor, a microcontroer, or the ike. Some types of ADCs convert anaog signas to digita signas using mutipe stages. Mutipe stages may provide a resou tion and/or signa-to-noise ratio to match the type of anaog signa being converted. For exampe, an ADC with one or a few stages may be used to convert a signa with a ower resoution or ow signa-to-noise speci?cations. Atematey, anadc with more stages may be used to convert a signa with a higher resoution and/or higher signa-to-noise speci?ca tions. Many modern systems, such as those for industria, aero space, and automotive appications, and the ike, have mu tipe sensors, for exampe, providing many anaog signas to be processed, often at the same time. Muti-channe ADC arrangements (e.g., devices, systems, circuits, etc.) may be used to convert severa anaog signas concurrenty. Muti channe ADC arrangements generay have two or more chan nes operating in parae, each incuding an ADC. However, due to manufacturing constraints, muti-channe ADC arrangements have commony been designed to deiver a?xed performance per channe across each of the channes. In other words, each channe of the muti-channe ADC arrangement may be designed aike and has the same resou tion and/or signa-to-noise capabiities (i.e., may have the same number of ADC stages in each channe). Thus, for a given appication, a muti-channe ADC arrangement may be seected that has a performance high enough to meet the processing needs of the highest quaity input signa. This may be overki and a waste of hardware-ef?ciency, power, and the ike, for other channes on the muti-channe ADC arrange ment that are used for converting ower resoution signas. Further, custom muti-channe ADC arrangements may be better suited to a variety of mutipe input signas, but can be costy if taiored for speci?c appications. BRIEF DESCRIPTION OF THE DRAWINGS The detaied description is set forth with reference to the accompanying?gures. In the?gures, the eft-most digit(s) of a reference number identi?es the?gure in which the reference number?rst appears. The use of the same reference numbers in different?gures indicates simiar or identica items. For this discussion, the devices and systems iustrated in the?gures are shown as having a mutipicity of components. Various impementations of devices and/or systems, as described herein, may incude fewer components and remain within the scope of the discosure. Aternatey, other impe mentations of devices and/or systems may incude additiona components, or various combinations of the described com ponents, and remain within the scope of the discosure. FIG. 1 is a schematic drawing of an exampe muti-chan ne, muti-stage anaog-to-digita converter (ADC) arrange ment in a?rst operating mode, according to an impementa tion. FIG. 2 is a schematic drawing of the exampe muti-chan ne, muti-stage anaog-to-digita converter (ADC) arrange ment in a second operating mode, iustrating hardware shar ing, according to an impementation FIG. 3 is schematic diagram of the exampe muti-channe, muti-stage anaog-to-digita converter (ADC) arrangement in a?rst operating mode and a second operating mode, according to another impementation. FIG. 4 is a?ow diagram iustrating an exampe process for adjusting a muti-channe ADC arrangement, incuding shar ing ADC stages, according to an impementation. DETAILED DESCRIPTION Overview Representative impementations of devices and techniques provide con?gurabe muti-channe anaog-to-digita conver sion. In a muti-channe anaog-to-digita converter (ADC) arrangement, each channe of the muti-channe ADC arrangement incudes a con?gurabe ADC made up of mu tipe stages. One or more of the ADC stages may be opera tivey couped to a different ADC (i.e., hardware sharing) in each of various operating modes. For exampe, a singe ADC stage may be an eement of a?rst ADC channe in one opera tiona mode and may be an eement of a second ADC channe in another operationa mode. Hardware sharing between the ADCs provides a?exibe ADC arrangement that reduces hardware or power waste in muti-channe appications. A?exibe architecture aso aows individua channes to be adjusted to more cosey meet the speci?cations of individua input signas. In various aternate impementations, mutipe ADC stages are either party or fuy integrated with a hardware compo nent. The ADC stages may be arranged in one or more con?gurations, often using the same amount of area, to form one or more muti-stage ADC arrangements. For exampe, the same matrix of ADC stages may be arranged in a?rst con?guration to form three ADC channes or in a second con?guration to form two ADC channes, where the two ADC channes have a greater quantity of stages per ADC channe, and have a higher resoution or a greater signa-to-noise ratio. Accordingy, the same chip design may be mass produced to meet the needs of a variety of appications with differing performance speci?cations. Impementations are expained in more detai beow using a puraity of exampes. Athough various impementations and exampes are discussed here and beow, further impe mentations and exampes may be possibe by combining the features and eements of individua impementations and exampes. Exampe Muti-Channe, Muti-Stage ADC Arrangement FIG. 1 is a schematic drawing of an exampe muti-chan ne, muti-stage anaog-to-digita converter (ADC) arrange ment 100 in a?rst operationa mode, according to an impe mentation. It is to be understood that muti-channe ADC arrangements (such as ADC arrangement 100) may be impe mented as stand-aone circuits, apparatuses, or devices, or as part of another system (e.g., integrated with other compo nents, processors, etc.). The iustrated muti-channe ADC arrangement 100 in FIG. 1 is shown and described in terms of a sigma-deta ADC arrangement, which may have noise shaping or noise reducing properties. This iustration is, however, for ease of discussion. The techniques and devices described herein with respect to muti-channe ADC arrange ments is not imited to the circuit diagram iustrated in FIG. 1 or to a sigma-deta device, and may be appied to other types of ADC arrangements (e. g., direct-conversion, successive approximation, ramp-compare, subranging, etc.), or other ADC designs without departing from the scope of the disco sure. In some cases, additiona or aternative components may be used to impement the techniques described herein.

7 3 As shown in FIG. 1, in a?rst operationa mode, a muti channe ADC arrangement 100 incudes at east two anaog to-digita converters (ADCs) 102 and 104. In some impe mentations, a muti-channe ADC arrangement 100 incudes a greater number of ADCs. Each ADC (102 and 104) com prises mutipe stages 106. The ADC arrangement 100 ius trated in FIG. 1 shows a 2x arrangement, meaning 2 ADCs (102 and 104), with each having a cascade of three stages 106 (i.e., 1A, 2A, 3A and 1B, 2B, 3B). In an impementation, the quantity of stages 106 in anadc (102, 104) determines a resoution of the ADC, a signa-to noise ratio (SNR) of the ADC, a signa-to-noise pus distor tion ratio (SNDR) of the ADC, a bandwidth of the ADC, and the ike. For exampe, anadc (102, 104) with two stages 106 may be a second-order ADC, an ADC (102, 104) with three stages 106 may be a third-order ADC, and the ike. In an impementation, the greater the quantity of stages 106 in the ADC (102, 104), the greater the resoution, SNR, SNDR, bandwidth, noise reduction, and so forth. In various impementations, stages 106 may be arranged to form mutipe ADCs (102, 104). In an impementation, one or more of the ADCs (102 and 104) are arranged as a muti-stage noise shaping (MASH) ADC. For exampe, each stage 106 of the MASH ADC (102, 104) reduces the noise of the signa it receives from the output of the stage 106 before it. In various impementations, one or more of the stages 106 of the ADCs (102, 104) are sigma-deta devices. In other impementations, the stages 106 are other technoogy stage devices according to other arrangements. In one impementation, the sigma-deta stages 106 are arranged to provide mutipe ADCs in channes on a singe integrated circuit (IC). In aternate impementations, the sigma-deta stages 106 are arranged on mutipe ICs or com ponents. The iustrated ADCs (102, 104) in FIG. 1 are shown with three stages 106 each for ease of discussion. An exampe ADC (102, 104) may have any number of stages 106 and remain within the scope of the discosure. In an aternate impementation, anadc 102 may have a different quantity of stages 106 than an ADC 104. As shown in FIG. 1, a cock signa (cocka and B) is provided to each of the stages 106 in an ADC (102, 104) for timing purposes. Additionay, as shown in FIG. 1, an ADC (102, 104) may incude a digita correction network (DCN) 108. The DCN 108 may be couped at the output end of the stages 106, to prepare the resuting signa for digita?tering and process ing.aso as shown in FIG. 1, the output of theadc (102, 104) may be?tered by a digita?ter (e.g., a decimation?ter), LP Fiter A and B, respectivey. For exampe, each ADC (102, 104) may have a DCN 108 and a digita?ter associated with the ADC. In an aternate impementation, a singe?ter may be associated with mutipe ADCs (102, 104), using mutipexing. Further, a DCN 108 may be partiay or fuy shared by two or more ADCs, as wi be discussed further. In an impementation, as shown in FIG. 1, the ADC 102 is incuded in a?rst channe, Channe A, and the ADC 104 is incuded in a second channe, Channe B. In various impe mentations, a muti-channe ADC arrangement 100 may have any number of channes, each incuding an ADC (102, 104). In one impementation, the channes (A, B) of an ADC arrangement 100 are non-time-intereaved channes operat ing in parae. For exampe, the channes (A, B) operate neary simutaneousy or concurrenty, rather than taking turns in a cyce. In various impementations, the muti-stage ADC arrange ment 100 is impemented at east in part in hardware. For exampe, the ADC arrangement 100 may be impemented at east in part using accumuators, adders,?ip-?ops, and the ike. Exampe Hardware Sharing FIG. 2 is a schematic drawing of the exampe muti-chan ne, muti-stage anaog-to-digita converter (ADC) arrange ment 100 in a second operationa mode, iustrating hardware sharing, according to one impementation. In FIG. 2, the abes for ADC 102 and ADC 104 are not shown for carity. However, in FIG. 2, as shown in FIG. 1,ADC 102 incudes the ADC components associated with channe A (the A abeed components) and ADC 104 incudes the ADC components associated with channe B (the B abeed components). Generay, hardware sharing incudes adjusting an ADC arrangement 100 such that components of one ADC or chan ne are used or shared by another ADC or channe. For exampe, hardware sharing incudes adjusting ADC arrange ment 100 such that ADC 102 uses or shares components from (or associated with) ADC 104 and channe B; and/or ADC 104 uses or shares components from (or associated with) ADC 102 and channe A. In various impementations, an ADC (102, 104) or ADC channe (A, B) can be operativey couped to, and use a component from (or associated with) anotheradc or channe in addition to its own components or instead of its own components whie in a hardware sharing operationa mode. Referring to FIGS. 1 and 2, in an impementation, one or more of the B1, B2, or B3 stages 106 associated with ADC 104 and channe B are con?gurabe to be operativey couped to ADC 104 and channe B whie the ADC arrangement 100 is in a?rst operationa mode (as shown in FIG. 1) and opera tivey couped to ADC 102 and channe A whie the ADC arrangement 100 is in a second operationa mode. The?rst operationa mode is shown in FIG. 1, where stage 3B, for exampe, is operativey couped to ADC 104 and channe B. The second operationa mode is shown in FIG. 2, where stage 3B, for exampe, is operativey couped to ADC 102 and channe A. Whie the ADC arrangement 100 is a 2x arrangement in the?rst operationa mode, the ADC arrangement 100 is a 1x (1A, 2A, 3A, 3B) pus 1>< 1-1 (1B, 2B) arrangement in the second operationa mode. In the second operationa mode, the ADC 102 is a fourth order ADC with the addition of stage 3B, since stage 3B becomes a fourth stage in the signa path of channe A. Thus, in various impementations, channe A is abe to provide a higher resoution, a greater bandwidth, a greater SNR or SNDR, and the ike, to an input signa appied to channe A, whie in the second operationa mode. Consequenty, in the second operationa mode, ADC 104 becomes a second-order ADC without stage 3B, and channe B has a ower resoution, SNR, etc. than channe A, or than whie in the?rst operationa mode. In one impementation, as shown with the dashed ine in FIG. 2, the stage 3B may be bypassed by channe B in the second operationa mode. For exampe, whie stage 3B is working for channe A in the second operationa mode, the signa path of channe B may bypass stage 3B. Conversey, whie stage 3B is working for channe B in the?rst opera tiona mode, the signa path of channe B incudes stage 3B. In an impementation, the ADC arrangement 100 may incude a number of mutipexors (MUX) 202. The MUXs 202 may faciitate the hardware sharing between ADC chan nes, at east whie in the second operationa mode. For exampe, as iustrated in FIG. 2, there is a MUX 202 in the channe B signa path just prior to stage 3B. This MUX 202 provides mutipexing of the channe A signa and the channe B signa through the stage 3B, aowing channe A and ADC

8 5 102 to share stage 3B. In some impementations, the ADC arrangement 100 may be adjusted such that ADC 102 (and channe A) and ADC 104 (and channe B) aternatey share stage 3B, for exampe. Stage 3B may be aternatey opera tivey couped to ADC 102 (and channe A) in the second operationa mode and operativey couped to ADC 104 (and channe B) in the?rst operationa mode. In an impementa tion, being operativey couped incudes turning on the signa path, and the ike, such that a signa passes through the operativey couped component(s). In an impementation, as shown in FIG. 2, each of the ADCs 102 and 104 have a MUX 202 added to the respective signa paths, just prior to the DCNs 108. A MUX 202 just prior to the DCN A 108 of channe A aows signas from stages 3A and 3B to be mutipexed to DCNA 108 during the?rst and second operationa modes respectivey. The signa from stage 3B is used during the second operationa mode, whie stage 3B is being used by ADC 102 (channe A). A MUX 202 just prior to the DCN B 108 of channe B aows signas from stages 2B and 3B to be mutipexed to DCN B 108 during the second and?rst operationa modes respec tivey. The signa from stage 3B is used during the?rst opera tiona mode, whie stage 3B is being used by ADC 104 (chan ne B). The signa from stage 2B is used during the second operationa mode, whie stage 3B is being used by ADC 102 (channe A). In an impementation, whie the ADC arrangement 100 is in the second operationa mode, DCN B is partitioned such that a portion of DCN B that is associated with stage 3B, for exampe, (i.e., the shared component(s)) is mutipexed to DCN A. In FIG. 2, the partitioned portion of DCN B that is associated with stage 3B is represented by the shaded area 204. The partitioned area 204 is mutipexed to DCN A for digita processing at channe A during the second operationa mode. This interna mutipexing is represented by the dashed arrow from the partitioned area 204 to DCN A. In various impementations, controing or adjusting the ADC arrangement 100 between operationa modes may be performed by contro ogic, microcontroer,?rmware, soft ware, and the ike. In one impementation, an end user may adjust the ADC arrangement 100 to an operationa mode suitabe for an appication. In another impementation, the end user may adjust the ADC arrangement 100 to determine the arrangement of the mutipe ADCs (e.g., 102, 104), incuding the stages incuded by each ADC (102, 104) during each operationa mode. In various impementations, signa paths for mutipe operationa modes andadc arrangements are avaiabe on an ADC arrangement 100. For exampe, a chip design or com ponent containing an ADC arrangement 100 may incude or provide the signa paths for mutipe operationa modes, incuding mutipe hardware sharing scenarios. Signa paths may incude one or more of hardware,?rmware, or software paths, and may be impemented in wired, wireess, optica, inductive, magnetic, and/or other transmission technoogies. Exampe Impementation FIG. 3 is schematic diagram of the exampe muti-channe, muti-stage anaog-to-digita converter (ADC) arrangement 100 in a?rst operating mode and a second operating mode, according to another exampe impementation. Some compo nents of the ADC arrangement 100 are not shown in FIG. 3 for carity. In one impementation, the ADC arrangement 100 is a mass-producibe singe design that is adjustabe to form vary ing, mutipe channes, ADCs, and arrangements. For exampe, in one instance, the ADC arrangement 100 com prises a matrix of ADC stages with con?gurabe signa paths In one impementation, the matrix of ADC stages is arranged into mutipe ADCs by con?guring the signa paths into a desired arrangement, representing a?rst operating mode. Further, the matrix of ADC stages is arranged into mutipe other ADCs by adjusting the signa paths into a different arrangement, representing a second operating mode. In an impementation, the ADC arrangement 100 may be aternated between the?rst and second operating modes. In another impementation, the ADC arrangement 100 may be further adjusted to a third or fourth operating mode, and the ike. Accordingy, a hardware device (such as a sigma-deta stage 106, for exampe) may be appied to work for more than one channe in a singe impementation. The ADC arrangement 100 is shown and described in FIG. 3 as having three ADC channes: ADC 102 at channe A, ADC 104 at channe B, and ADC 302 at channe C. In aternate impementations, the ADC arrangement 100 may have fewer channes or a greater quantity of channes. In an impemen tation, each of the ADC channes (A, B, C) incudes mutipe sigma-deta stages 106. In one impementation, the ADC arrangement 100 is adjustabe from a?rst operating mode to at east a second operating mode. In one exampe, the ADC arrangement 100 has feweradc channes in the second operating mode than in the?rst operating mode. Further, one or more of the ADC channes (A, B, C) incudes a greater quantity of sigma-deta stages 106 in the second operating mode and has a higher resoution in the second operating mode than in the?rst operating mode. For exampe, in the?rst operating mode, as shown in FIG. 3, each of the ADCs (102, 104, 302) in each of the channes (A, B, C) is shown with three stages 106 (e.g., a 3>< arrangement). However, in the second operating mode, the?rst stage 106 of ADC 104 (channe B) is operativey couped to ADC 102 of channe A. With the addition of the stage 106, ADC 102 becomes a fourth-orderadc, having four stages in the second operating mode. Aso in the second operating mode, the second and third stages 106 of ADC 104 (channe B) are operativey couped to ADC 302 of channe C. With the addition of the stages 106, ADC 302 becomes a?fth-order ADC, having?ve stages in the second operating mode. As shown in FIG. 3, the ADC arrangement 100 in the second operating mode is 1>< pus 1>< In this exampe, the ADC arrangement 100 has fewer ADC channes (two) in the second operating mode than in the?rst operating mode (three). With the stages 106 of ADC 104 operativey couped to ADCs 102 and 302, channe B is effectivey eiminated during the second operating mode. Further, both of the ADC channes A and C incude a greater quantity of sigma-deta stages 106 in the second operating mode than in the?rst operating mode. Finay, in this exampe, both of the ADC channes A and C have a higher resoution in the second operating mode than in the?rst operating mode, based on the additiona stages couped to each of the ADCs (A, C). As discussed above, the ADC arrangement 100 may use mutipexors (such as MUX 202) or the ike to faciitate hardware sharing between the ADCs. Further, If the ADCs use DCNs, one or more of the DCNs may be partitioned (aso hardware sharing) as discussed above, for exampe, to direct a signa to the correct output path (e.g., for digita?tering, processing, etc.) during hardware sharing of a stage 106. In aternate impementations, the ADCs (102, 104, 302) of ADC arrangement 100 may be couped in a different manner, with different resuts. For exampe, channe B may not be eiminated in an impementation if some of the stages of ADC

9 7 104 are not couped to another ADC in the second operating mode. Further, the manner in which the stages 106 are couped (order, path, etc.) as iustrated in FIGS. 1-3 is not intended to be imiting, and stages 106 may be couped in various other manners and remain within the scope of the discosure. In various impementations, the ADCs of an ADC arrange ment 100 may have fewer or a greater quantity of stages 106, and remain within the scope of the discosure. Aso, addi tiona or aternate components may be incuded in an ADC arrangement 100. Representative Process FIG. 4 iustrates a representative process 400 for adjusting a muti-channe ADC arrangement (such as ADC arrange ment 100), according to an impementation. An exampe pro cess 400 incudes sharing ADC stages (such as stages 106) and/ or other components between ADCs (such as ADCs 102, 104, and 302). In various impementations, an ADC stage may be operativey couped to one ADC in a?rst operationa mode and operativey couped to another ADC in a second operationa mode. The process 400 is described with refer ence to FIGS The order in which the process is described is not intended to be construed as a imitation, and any number of the described process bocks can be combined in any order to impement the process, or aternate processes. Additionay, individua bocks may be deeted from the process without departing from the spirit and scope of the subject matter described herein. Furthermore, the process can be impe mented in any suitabe hardware, software,?rmware, or a combination thereof, without departing from the scope of the subject matter described herein. At bock 402, the process incudes arranging, in a?rst operationa mode, a?rst puraity of sigma-deta stages to provide a?rst anaog-to-digita converter (ADC) channe. At bock 404, the process incudes arranging, in the?rst operationa mode, a second puraity of sigma-deta stages to provide a second ADC channe. In one impementation, the?rst and second ADC channes are arranged as muti-stage noise shaping (MASH), non time-intereaved, sigma-deta ADC channes. In another impementation, the process incudes arranging the?rst and second puraities of sigma-deta stages to provide the?rst and second ADC channes on a singe integrated circuit (IC). At bock 406, the process incudes adjusting, in a second operationa mode, the second puraity of sigma-deta stages to operativey coupe one or more of the second puraity of sigma-deta stages to the?rst ADC channe. In one instance, the adjusting incudes adjusting a signa path of the?rst ADC channe to incude eements of the second ADC channe. In one impementation, the process incudes adjusting, in the second operationa mode, the second ADC channe to bypass the one or more sigma-deta stages. In an aternate impementation, the process incudes adjusting the?rst and second ADC channes to share the one or more sigma-deta stages. For exampe, the one or more sigma-deta stages are aternatey operativey couped to the?rst ADC channe in the second operationa mode and opera tivey couped to the second ADC channe in the?rst opera tiona mode. In one impementation, the process 400 incudes muti pexing signas from the?rst and second ADC channes through the one or more sigma-deta stages. In another impementation, the process 400 incudes par titioning, in the second operationa mode, a digita correction network (such as DCN B) couped to the secondadc channe such that a portion of the second digita correction network associated with the one or more sigma-deta stages is muti pexed to another digita correction network (such as DCN A) couped to the?rst ADC channe. In one impementation, the process 400 incudes adjusting, in the second operationa mode, the performance of at east one of the?rst and second ADC channes for at east one of signa-to-noise ratio, signa-to-noise pus distortion ratio, and resoution. For exampe, adding an additiona sigma-deta stage to the signa path of anadc, through hardware sharing, for exampe, can improve performance of the ADC. On the other hand, osing a sigma-deta stage from a signa path of an ADC during an operationa mode can decrease performance of the ADC. In one impementation, the performance of the?rst and second ADC channes is adjusted such that the?rst ADC channe has a higher resoution in the second operationa mode than in the?rst operationa mode, and the second ADC channe has a ower resoution in the second operationa mode than in the?rst operationa mode. In one exampe, operativey couping a sigma-deta stage associated with the secondadc to the?rst ADC, in the second operationa mode, increases the resoution of the?rst ADC in the second operationa mode compared to the?rst operationa mode. Additionay, opera tivey couping the sigma-deta stage associated with the sec ond ADC to the?rst ADC reduces the resoution of the second ADC in the second operationa mode. In aternate impementations, other techniques may be incuded in the process 400 in various combinations, and remain within the scope of the discosure. Concusion Athough the impementations of the discosure have been described in anguage speci?c to structura features and/or methodoogica acts, it is to be understood that the impemen tations are not necessariy imited to the speci?c features or acts described. Rather, the speci?c features and acts are dis cosed as representative forrns of impementing exampe devices and techniques. What is caimed is: 1. An apparatus comprising: a?rst anaog-to-digita converter (ADC) comprising a?rst puraity of stages; and a second ADC comprising a second puraity of stages, one or more stages of the second puraity of stages con?g urabe to be operativey couped to the second ADC whie the apparatus is in a?rst operationa mode and operativey couped to the?rst ADC whie the apparatus is in a second operationa mode, wherein at east one of the?rst ADC and the second ADC are muti-stage noise shaping (MASH) ADCs. 2. The apparatus of caim 1, the?rst ADC and the second ADC further comprising a?rst mutipexor and a second mutipexor respectivey, and further comprising a third mu tipexor operativey couped to the one or more stages and to the?rst ADC whie the apparatus is in the second operationa mode. 3. The apparatus of caim 1, further comprising a?rst channe incuding the?rst ADC and a second channe incud ing the second ADC. 4. The apparatus of caim 3, wherein the?rst and second channes are non-time-intereaved or time-intereaved chan nes operating in parae. 5. The apparatus of caim 1, the?rst ADC and the second ADC further comprising a?rst digita correction network and a second digita correction network respectivey. 6. The apparatus of caim 5, wherein the second digita correction network is partitioned whie the apparatus is in the second operationa mode, a portion of the second digita

10 9 correction network associated with the one or more stages being mutipexed to the?rst digita correction network. 7. The apparatus of caim 1, wherein one or more stages of the?rst puraity of stages and the second puraity of stages comprise sigma-deta ADC stages. 8. The apparatus of caim 1, wherein the?rst ADC has a higher resoution than the second ADC whie the apparatus is in the second operationa mode. 9. A muti-channe system comprising: a puraity of con?gurabe anaog-to-digita converters (ADCs), each ADC incuding mutipe stages; and a puraity of sigma-deta devices arranged to compose the mutipe stages, one of the puraity of sigma-deta devices composing a stage of one of the puraity of ADCs in a?rst arrangement and composing a stage of another of the puraity of ADCs in another arrangement, wherein one or more ADCs of the puraity of ADCs com prises a muti-stage noise shaping (MASH) ADC. 10. The system of caim 9, further comprising one or more mutipexors operativey couped to the one of the puraity of sigma-deta devices in the other arrangement. 11. The system of caim 9, wherein each of the puraity of ADCs comprises a non-time-intereaved or a time-inter eaved channe of the muti-channe system. 12. The system of caim 9, wherein the system is impe mented at east in part in hardware using at east one of accumuators, adders, and?ip-?ops. 13. A method comprising: arranging, in a?rst operationa mode, a?rst puraity of sigma-deta stages to provide a?rst anaog-to-digita converter (ADC) channe and a second puraity of sigma-deta stages to provide a second ADC channe; and adjusting, in a second operationa mode, the second pu raity of sigma-deta stages to operativey coupe one or more of the second puraity of sigma-deta stages to the?rst ADC channe. 14. The method of caim 13, further comprising arranging the?rst and second ADC channes as muti-stage noise shap ing (MASH), non-time-intereaved or a time-intereaved, sigma-deta ADC channes. 15. The method of caim 13, further comprising arranging the?rst and second puraities of sigma-deta stages to pro vide the?rst and second ADC channes on a singe integrated circuit (1C). 16. The method of caim 13, further comprising adjusting, in the second operationa mode, the second ADC channe to bypass the one or more sigma-deta stages The method of caim 13, further comprising adjusting the?rst and second ADC channes to share the one or more sigma-deta stages, the one or more sigma-deta stages being aternatey operativey couped to the?rst and second ADC channes in the second and?rst operationa modes, respec tivey. 18. The method of caim 13, further comprising adjusting, in the second operationa mode, a signa path of the?rst ADC channe to incude eements of the second ADC channe. 19. The method of caim 13, further comprising mutipex ing signas from the?rst and second ADC channes through the one or more sigma-deta stages. 20. The method of caim 13, further comprising partition ing, in the second operationa mode, a digita correction net work couped to the second ADC channe such that a portion of the second digita correction network associated with the one or more sigma-deta stages is mutipexed to another digita correction network couped to the?rst ADC channe. 21. The method of caim 13, further comprising adjusting, in the second operationa mode, the performance of at east one of the?rst and second ADC channes for at east one of signa-to-noise ratio, signa-to-noise pus distortion ratio, or resoution. 22. The method of caim 21, further comprising adjusting the performance of the?rst and second ADC channes, wherein the?rst ADC channe has a higher resoution in the second operationa mode than in the?rst operationa mode, and the second ADC channe has a ower resoution in the second operationa mode than in the?rst operationa mode. 23. A muti-channe anaog-to-digita converter (ADC) device comprising: a puraity of ADC channes, each ADC channe compris ing mutipe sigma-deta stages, wherein the device is adjustabe from a?rst operating mode to a second operating mode, the second operating mode having fewer ADC channes than the?rst operat ing mode and one or more of the puraity of ADC channes comprising a greater quantity of sigma-deta stages and having a higher resoution in the second oper ating mode than in the?rst operating mode. 24. The muti-channe ADC device of caim 23, wherein one or more of the sigma-deta stages is arranged to be opera tivey couped to one of the puraity of ADC channes in the second operating mode and is arranged to be operativey couped to another of the puraity of ADC channes in the?rst operating mode.