Off-Chip Interconnects in Wireless Hardware a tutorial : technologies and trends

Transcription

1 Off-Chip Interconnects in Wireless Hardware a tutorial : technologies and trends by Jan Hesselbarth, University of Stuttgart FP7 ARTISAN training, Belfast, October 27, 2014 Outline: Introduction Solder contacts Wire bonds Flip chip bonds On-chip antennas and radiation coupling <1 >

2 Why Off-Chip Interconnects? Required. Multi-disciplinary. Not following Moore s law. Expensive Antenna(s) Sensors Actuators Data I/O Power supply Thermal / cooling Interconnects. Issues: - performance. RF. thermal. mechanical - flexibility - testabilty - form factor - weight - cost cost cost Integrated circuit: - mostly for signal processing - low voltage, low power - cheap <2>

3 A bit of history: The first transistor contacted the first bipolar transistor by Bardeen, Brattain, Shockley, 1947 [ wikipedia ] <3>

4 A bit of history: The first russian color TV 1970: semiconductors were mostly tubes and passives had wire contacts [ youtuve ] <4>

5 Integrated circuits Two levels of packaging in the majority of cases, to reduce overall cost, integrated circuits are 1st placed into a package ( first level packaging), eg, by wire bonds; 2nd soldered onto a circuit board ( second level packaging), eg, SMT this basic concept has not much changed since the early 1970s wire bond die DIL package [ wikipedia ] leadframe die attach mold <5>

6 Outline: Introduction Solder contacts Wire bonds Flip chip bonds On-chip antennas and radiation coupling

7 Second level packaging Soldering (1/2) makes a solid connection between metals at not-so-high temperatures the solder is a mixture of (two) metals, to reduce the melting temperature the phase diagram of the metal mixture shows the temperatures where one part or the other is solid or liquid the mixture is eutectic when there is a complete transition between liquid and solid at a single temperature in reality, solder is often noneutectic as parts of the to-besoldered metals go into solution phase diagram of PbSn: eutectic solder examples: Sn48In52: 117 C; Sn63Pb37: 183 C; Sn95Ag4Cu: 217 C; Au80Sn20: 280 C [ wikipedia ] <6 >

8 Second level packaging Soldering (2/2) lead-less solder (i.e., Sn95Ag4Cu) needs higher soldering temperatures the liquid solder takes contact metal into solution thin traces disappear (never use Sn-solder on Au thin-/ thick-film), thick contacts may change solder joint metallurgy causing bad connections (use Ni barrier) different solders for different temperatures allow for multilevel soldering. Example: 1) AuSn (~300 C) to solder metal baseplate on ceramic backside 2) SnAg (~220 C) to solder SMT components & flex connections 3) glueing & wire-/flipchip-bonding chips 4) SnAg (~220 C) flux-less to solder cover using locally embedded heaters [ Huber+Suhner ] <7 >

9 Outline: Introduction Solder contacts Wire bonds Flip chip bonds On-chip antennas and radiation coupling

10 First level packaging Wire bonds (1/3) in the vast majority of cases, chips are bonded into a plastic package wire bond die pro: protected: easy handling, marking, shipping, mounting, soldering, con: heatsinking (higher thermal resistance), RF performance deteriorated leadframe die attach mold Intel 8742 [ microwaves&rf, June 20, 2013 ] <8>

11 First level packaging Wire bonds (2/3) for modern chips with many contacts, wire bonds may become very dense, or chips even may be stacked this is typically not (yet?) the case for RF chips [ Fraunhofer IZM ] [ wikipedia ] <9>

12 First level packaging Wire bonds (3/3) a bond wire is placed between two landing pads - bond wire diameter μm or ribbon of width μm - Au or Al - wire and pad are connected by pressure, friction (eg. ultra-sonic vibration) and heat (eg. pre-heated board to 120 C for Au bonds) wire bond technology for RF is black magic with many parameters but is astonishingly reproducible < 10 >

13 Wire bonds ball-stitch bonds ball-stitch bonding technique: - cheap/standard tools - long bonds not good for RF capillary tool [ SPT ] flash forms ball 2x pressure + ultra-sonic clamp + up <11 >

14 Wire bonds wedge-wedge bonds wedge-wedge bonding technique - rather specific tools - short RF bonds feasible wedge tool 2x pressure + ultra-sonic clamp + up [ SPT ] short vs. very-short RF bond : [ Fraunhofer IZM ] < 12 >

15 Wire bond frequency behaviour (1/4) the chip-to-board bondwire can be seen as series inductance series inductance of a thin wire parallel over ground: bondwire 2ln 4 nh cm H distance wire to planar ground D wire diameter a very rough estimate: a 1mm long bond wire gives -10 db reflection already at approx. 5 GHz! the chip-to-board bondwire shows low-pass behaviour: bond ground chip board heatsink S 11 / db frequency / GHz better performance at higher frequency by lowering the bond inductance: shorter bonds, thicker bonds (or two parallel bonds or ribbon) < 13 >

16 Wire bond frequency behaviour (2/4) a shorter bond will push the lowpass edge frequency upwards: ground board bond chip S 11 / db heatsink frequency / GHz compensation of bondwire inductance by shunt capacitance will push the lowpass edge frequency upwards: S 11 / db frequency / GHz L C L LCLCL! < 14 >

17 Wire bond frequency behaviour (3/4) bond length cannot be shortened infinitely. For narrowband systems, half-wavelength bondwires could be a solution - λ/2 GSG bondwires for 122 GHz: [S. Beer, KIT Karlsruhe] < 15 >

18 Wire bond frequency behaviour (4/4) perhaps new wirebond technology could lead to shorter bonds: - three-turn coil made of inkjet-printed sintered colloidal suspensions; wire diameter here: < 2 μm [N. Schirmer, J. Hesselbarth et al., Appl. Phys. Lett., 2010] < 16 >

19 Outline: Introduction Solder contacts Wire bonds Flip chip bonds On-chip antennas and radiation coupling

20 Flip chip bonds much shorter and thicker than a wire lower inductance can be - directly glued, - soldered, not really a process for series production bumps made by plating of solder plus reflow - thermosonic-bonded, tricky but highest contact density - glued stud bumps balls can be made from studs with coining low-temperature process [ FH Buchs ] < 17 >

21 Flip chip bonds Related RF problems the chip-to-board transition (in particular, CPW) has lowest inductance : on-chip top metal and board top metal create a parallel-plate transmission line which causes coupling, resonance effects and possibly a strong excitation of surface waves : on-chip transmission-line structures are de-tuned by the proximity of board dielectric or board top metal or worst underfill : thermal expansion mismatch between chip and board is difficult to accomodate if underfill is not an option : heat removal needs special attention (problems can be alleviated by additional bumps or thermally conductive underfill or backside heat pads) : inspection, test, repair is rather difficult < 18 >

22 Outline: Introduction Solder contacts Wire bonds Flip chip bonds On-chip antennas and radiation coupling

23 Radiation coupling from chips into guided waves (1/3) insertion loss of both bond wires and compensation structures becomes prohibitive beyond ~ 200 GHz off-chip transmission media beyond few hundred GHz are rectangular waveguide or some dielectric waveguide (not: microstrip, CPW), therefore coupling from chip to microstrip/cpw makes no sense example 1 : on-chip dipole couples directly to E-field of rectangular waveguide TE 10 mode - bandwidth 20 30% ok - expensive mount - chip test? InP 480 GHz LNA: waveguide bias [W.R. Deal et al., Demonstration of a 0.48 THz Amplifier Module Using InP HEMT Transistors, IEEE Microw. Wireless Comp. Lett., May 2010] < 19 >

24 Radiation coupling from chips into guided waves (2/3) example 2 : on-chip dipole couples to E-field of dielectric image guide Ex11 mode - narrowband ~10% - compatible with PCB technology except for image guide dielectric layer - chip test possible using dielectric probes (research) 25 mm [N. Dolatsha, J. Hesselbarth, Millimeter-wave chipto-chip transmission using an insulated image guide excited by an on-chip dipole antenna at 90 GHz, IEEE Microw. Wireless Comp. Lett., May 2012] < 20 >

25 Radiation coupling from chips into guided waves (3/3) example 3 : spherical dielectric resonator placed on-chip couples to waveguide (research): - placement of sphere in a small on-chip ditch which is made in the back-endof-line chip process - can be placed anywhere on the chip (not at the edge) - lowest transmission loss from transistor to waveguide - narrowband ~10% - standard chip test with probes before sphere is mounted? air-filled metal waveguide dielectric resonator sphere line hole chip board < 21 >

26 Radiation from chips on-chip antennas (1/4) on-chip antennas for wireless transceivers are the dream of system engineers: - baseband-only chip interface - small cheap and scales with Moore s law -? in reality, design of on-chip antennas has many specific problems: - size: a length dimension of half a freespace wavelength is required. Smaller structures are much worse. An usage area of (λ/2) 2 will show a directivity of approx. 5 7 dbi. Chip area of that size can be very expensive! 15 GHz on-chip meander dipole of 2mm length [K.K. O et al., On-chip antennas in silicon ICs and their application, IEEE Trans. Electron Dev., July 2005] < 22 >

27 Radiation from chips on-chip antennas (2/4) - substrate modes: due to the high ε rel of the chip substrate, the on-chip antenna tends to radiate into the chip (dipole: 5% into air and 95% into silicon) a hemispherical lens helps to avoid reflections from chip backside chip silicon lens undoped silicon wafer silicon chip - packaging: any packaging in the reactive near-field will de-tune the antenna, whereas further away it will act as a radome [A. Babakhani et al., A 77 GHz 4-element phased array receiver with on-chip dipole antennas in silicon, ISSCC 2006] < 23 >

28 Radiation from chips on-chip antennas (3/4) - loss / efficiency / gain: silicon normally used for CMOS, BiCMOS etc. is conductive to an extend that it acts like a RF absorber. GaAs and InP are much better in that regard. Use of the back-end layers only (and shielding the lossy silicon) leads to very thin and lossy / narrowband antennas. 24 GHz on-chip meander dipole with 10% efficiency [K.K. O et al., On-chip antennas in silicon ICs and their application, IEEE Trans. Electron Dev., July 2005] 90 GHz on-chip slot ring in CMOS with 7% efficiency - testing: the chip needs to be tested in radiation mode or with probes before additional antenna structures are mounted. This is non-standard. [J.M. Edwards, G.M. Rebeiz, High-efficiency silicon RFIC millimeter-wave elliptical slotantenna with a quartz lens, IEEE AP-S 2011] < 24 >

29 Radiation from chips on-chip antennas (4/4) best compromise on all (?) mentioned issues is to place the excitation strucure in the back-end layers on top of the chip (shielding the substrate) and to excitate some resonating structure above the chip. Additional requirements like small footprint and testability need to be met (to be shown), then the dielectric resonating sphere is best. patch on quartz [J. Hasch, U. Wostradowski, S. Gaier, T. Hansen, 77 GHz radar transceiver with dual integrated antenna elements, GeMiC, 2010] frequency-scaled prototype of a dielectric resonating sphere antenna fed by microstrip line resonators on very thin substrate metal horn ring slot on quartz microstrip feed on chip [Y.-C. Ou, G.M. Rebeiz, On-chip slot-ring and high-gain horn antennas for millimeter-wave waferscale silicon systems, IEEE Trans. MTT, 2011] < 25 >