Digital Sub-System. Dorothy Gordon. Cosmic RAy Telescope for the Effects of Radiation

Transcription

1 Digital Sub-System Dorothy Gordon

2 Overview Digital Subsystem Overview/Block Diagram Developments Since PDR Design/Implementation Status Next Digital Engineering 2

3 Digital Sub-System Data Flow 1553 XCVR Side A Analog Board FPGA RT SX72SU 1553 XCVR Side B 1 Hz S/C RT D Test Pulse Amplitude 8 bit DAC Test Pulse Trigger (x2) Digital Engineering 3

4 Digital Sub-System Block Diagram P-LEVEL ECAL-DC 0-5 V. 8 bit ECALPWM PWM to DC TP-PCK[1:0] SngCnt[5:0] AE I/F PCKOUT[1:0] PCK[1:0] Buffer Test Pulse I/F ~0-1.4V. LLDTHIN-DC 8 bit LLDTHINPWM PWM to DC ~0-1.4V. LLDTHCK-DC 8 bit LLDTHKPWM PWM to DC LLD Threshold PDReset[5:0] ECALPWM ECAL-PCK[1:0] LLDTHNPWM LLDTHKPWM SRAM PDReset[5:0] ADC-CntlDat[5:0] 1553Dat[15:0] 1553AdrCntl[22:0] DetTrig[5:0] SngCnt[5:0] CLK16M HWReset CDM-FPGA HADRSEL[4:0] CLK1HZ HADC-CntllDat[1:0] Power-On Reset OSC BiasClk[1:0] BiasVEnb[1:0] Crater Data Control 75VP 225VP 5VN 5VP VCC 1553Dat[15:0] 1553AdrCntl[22:0] CLK16M Reset CLK1HZ SCLK RESET 1553 Bus Protocol Controller - Transceiver + - Diff.Rcvr Spacecraft Data Interface DC to DC Conversion A+ A- B+ B- 1PPS_+ 1PPS_- 1553_A 1553_B S/C 1HZ CLOCK S/C I/F DetSig[5:0] DetSigIn[5:0] x6 x6 ADC-CntlDat[5:0] 5V Peak Detect/Hold ADC 28VDC_- 5V_+ 5V_- EMI Filter 28VDC_+ 28VDC + RETURN ThrThin ThrThick x6 DetTrig[5:0] Vthreshold Comparator Analog Signal Processing Housekeeping ADC x2 ADC-CntlDat[1:0] 225V_+ ThickDetBiasEnb 75V_+ ThinDetBiasEnb AETemp[1:0] 5VP 5VN ThinDetBias ThickDetBias SigGnd to Analog Housekeeping Crater Analog Housekeeping 5VP 5VN 75VN 225VN Also sent to AE Subystem: Vref (2.5 V.), Vcc (5V) and Digital Ground HSKPIN[23:0] MADRSEL[4:0] Precondition Filter/Scale Analog Mux x2 BCLK[1:0] GND RTD t RT_P RT_N

5 Developments since PDR Requirements no significant changes Parts Selection DDC BU for 1553 Bus, Actel SX72, DC-DC Converter Modules (International Rectifier) Peak Stretcher (): Performance Verified via Breadboard Functional Description/Specification Details of FPGA operation (Drawing # ) Schematics Board Schematics: released (Drawing # ) Chassis Schematics: released (Drawing # ) High Voltage Power Supply (Drawing # ) (subcontracted) design complete prototype in house Digital Engineering 5

6 Since PDR (continued) Peer Review (GSFC, May 22, 2006) Received/Answered 15 RFAs (for both analog and digital subsystems) No change to fundamental design of either subsystem Part type modification (to insure edge-rate compatibility) Actel Programming Socket exchanged (for ESD Friendly replacement) Actel Static Timing analysis to include asynchronous clocked path analysis Signal Integrity and Ground bounce concerns (especially relative to the SX72 FPGA) Analysis Parts Stress Analysis: released (Drawing # ) Worst Case Analysis: released (Drawing # )

7 Design/Implementation Status FPGA Design VHDL Coding Complete (Drawing # ) Top Level functional simulation complete Timing Verified (Static Timer and Dynamic Simulation) Engineering Board (ETU) Layout and Fabrication completed Engineering layout is flight part footprint compatible High Voltage Supply, implemented on hand-wired breadboard, will be integrated during the second layout stage ETU Population Completion expected by last week of June Digital Engineering 7

8 Board Layout 8

9 Digital Engineering 9

10 Next Design Complete ready for board level check-out Next Test with GSE Verify basic functionality/operation Develop/run marathon diagnostics Integrate with analog board Flight Version Incorporate any modifications resulting from ETU debug Add Bias (High Voltage) Supply Digital Engineering 10