SD2017 Low Power HART TM Modem

Transcription

1 NC OCBIAS TEST10 VSSA A NC NC TEST4 TEST3 TEST2 TEST1 TEST12 OCD ORXD Low Power HART TM Modem Feature Meets HART physical layer requirements Single chip, half duplex 1200 bps FSK modem Bell 202 shift frequencies of 1.2kHz and 2.2kHz Buffered HART output for drive capability External MHz crystal or clock source 2.7V to 5.5V power supply 90μA maximum supply current in transmit mode -55 C to +125 C operation range 32 pin LQFP packages RoHS compliant General Description The is a CMOS single chip modem IC used in Highway Addressable Remote Transducer (HART) field instruments and masters. This IC together with a few external passive components provide all functions needed to satisfy HART physical layer requirements including modulation, demodulation, receive filtering, carrier detect, and transmit signal wave shaping. The uses phase continuous Frequency Shift Keying (FSK) at 1200 bps, and operates in half duplex mode per HART protocol. The maximum supply current consumption in transmit mode is 90μA while using MHz external Clock source input and 5.5V power supply. The is pin compatible with SD2015, HT2015 and A5191HRT. There is no need to change PCB when replacing any of the above ICs with. Some components on the original PCB are no longer needed, while others are changed to different types or different values. Refer to Replacing SD2015 with section for details. Ordering Information Package Part Number LQFP32 (7mm х 7mm) B Pin Diagram and Descriptions TEST5 INRESET _ENb TEST8 TEST9 VSS SDIC XXXXXXX B TEST11 ITXD 22 INRTS VSS 19 VSSA 18 IXTL 17 OXTL Figure 1. LQFP32 Pin diagram SDIC Microelectronics Rev. 0.1b June Page 1 of 8

2 Table 1. Pin Descriptions Pin Name Attribute LQFP Description TEST1-28 No Connect or connect to VSS. TEST2-29 No Connect or connect to VSS. TEST3-31 No Connect or connect to VSS. TEST4-32 No Connect or connect to VSS. TEST5-1 Connect to VSS. INRESET Digital input 2 Reset all digital logic, active low. _ENb Digital input 3 Reference enable. A low state enables the internal 1.5V reference and buffer. A high stage disables the internal reference and input buffer, and a buffered external 2.5V reference source must be applied at. TEST8-4 Connect to VSS. TEST9-5 Connect to VSS. Analog output 7 HART FSK signal output. Connect to 4-20mA loop interface circuit. Analog output 8 Internal 1.5V reference voltage output. Connect a 1μF capacitor to VSSA. NC - 9 No Connect or connect to VSS. OCBIAS Analog output 10 Circuit bias current setting. TEST10-11 No Connect or connect to VSS. A Analog power 13 Analog supply voltage, same voltage level with. Analog input 14 FSK modulated HART signal received from 4-20mA loop interface circuit. NC - 15 No Connect or connect to VSS. NC - 16 No Connect or connect to VSS. OXTL Analog output 17 Crystal oscillator output. IXTL Analog input 18 Crystal oscillator input. VSS Digital gnd 6,20 Digital ground, same voltage level with VSSA. Digital power 21,30 Digital supply voltage, same voltage level with A. INRTS Digital input 22 Request to sent, active low. ITXD Digital input 23 Data to be transmitted. After modulation, data goes out at. TEST11-24 No Connect or connect to VSS. ORXD Digital output 25 Demodulated HART data, output to external UART. OCD Digital output 26 Carrier detect, high when data valid at. TEST12-27 No Connect or connect to VSS. VSSA Analog gnd 12,19 Analog ground, same voltage level with VSS. SDIC Microelectronics Rev. 0.1b June Page 2 of 8

3 Circuit Description NC A ITXD INRTS ORXD Control Logic Modulator and Transmit Wave Shaping INRESET OCD TEST1~12 Carrier Detect Demodulator ADC IXTL OXTL Oscillator Voltage Reference Current Reference _ENb VSS VSSA OCBIAS Figure 2. Function block diagram Figure 2 is the function block diagram of. It is a low power HART FSK half duplex single chip modem that compiles with HART physical layer requirements. includes the modulator and wave shaper for transmitting data; and includes the ADC, demodulator, and carrier detect circuitry for receiving data. Other functional blocks include reference voltage, crystal oscillator, current reference. and The transmits or receives 1200Hz and 2200Hz FSK signals. 1200Hz represents digital 1, whereas 2200Hz represents digital 0. The bit rate is 1200bits/second. The oscillator provides time base for the modem using either MHz external crystal or MHz external clock source. Modulator and Wave Shaping When INRTS is set to low, the operates in transmit mode. The modulator converts the NRZ digital signals at ITXD into a sequence of phase continuous 1200Hz and 2200Hz HART compliant trapezoidal signals through the wave shaping block. The signals are then output to as shown in Figure 3 and Figure 4. The DC level is 0.75V with 0.5V~1.0V voltage swing. Figure 3. at logic 1 (1200Hz) Figure 4. at logic 0 (2200Hz) can drive capacitive load directly. The load should be 4.7nF to 68nF. consumes more current as the capacitive load increases. The supply current specifications shown in Table 3 are based on a 4.7nF capacitive load at. If driving a load with resistive element, it SDIC Microelectronics Rev. 0.1b June Page 3 of 8

4 should be coupled with a 2.2µF serial capacitor as shown in Figure 5. The RLOAD range is typically 200Ω to 600Ω. A 22nF capacitor should be connected between and ground. 22nF 2.2µF RLOAD Figure 5. with resistive load Demodulator and Carrier Detect When INRTS is set to high, the operates in receive mode. HART signal goes into through an external anti-aliasing band-pass filter. A high on OCD indicates a valid carrier is detected. The demodulator accepts the FSK signal at and restores to digital signal at ORXD, which is then output to external UART. The nominal bit rate is 1200 bps. Figure 6 illustrates the demodulation process. Figure 6. Demodulator signal timing The carrier detect circuit determines whether the carrier s amplitude at meets the HART protocol requirement, and outputs the result at OCD. When OCD output is high, the modulator outputs the demodulated digital data at ORXD. The demodulated digital data will appear at ORXD only after the carrier detect circuit decided that signals at are large enough to be detected (105mVp-p typically). According to HART specification, at MHz (±1.0%) clock frequency and zero input () asymmetry, the maximum demodulator jitter is less than 12% of one ORXD output bit. The carrier detect set the carrier detect output pin OCD to logic 1 if INRTS is logic 1 and four consecutive pulses out of the comparator have arrived. OCD stays logic 1 as long as INRTS is logic 1 and the next comparator pulse is received in less than 2.5ms. Once OCD goes inactive (logic 0), it takes another four consecutive pulses out of the comparator to assert OCD again. Receiving Filter for Demodulator The external band-pass filter is shown in Figure 7. A 200kΩ resistor at the filter input limits current to a sufficiently low level resulting in very high transient voltage protection capability. Therefore, no additional protection circuitry at the input terminal is needed even in the most demanding industrial environments. Using 1% accuracy resistor and 10% accuracy capacitor, effect of the filter on the carrier detection is still negligible. R1 C1 HART 200k 300pF signal 16(14) C2 R3 R2 180pF 1.2M 1.2M 11(8) C3 1µF NC 12(9) NC NC 17(15) 18(16) SDIC Microelectronics Rev. 0.1b June Page 4 of 8 Figure 7. external filter connection

5 R6 422K R7 215K C4 220pF HART signal C3 470pF C2 1nF R5 215K C1 1nF R4 215K R1 499K R3 787K R2 3M 16(14) ORXAF 17(15) C 18(16) V+ SD2015 Z V/2.5V R8 R9 14.7K/6.98K R10 215K 11(8) ICDREF 12(9) Figure 8. SD2015 external filter connection Replacing SD2015 with can replace SD2015 directly because their pins are compatible. There is no need to modify the PCB. Some external components are removed, and some resistance and capacitance values and types are changed. Referring to Figure 8, the following list includes all external component modifications needed on the PCB when replacing SD2015 with. Remove C4, R7, R6, R5, R8 and Z1 Change R1, R10 and C3 to 0Ω resistor Modify R2 and R3 to 1.2MΩ resistor Change C2 to 200kΩ resistor Modify C1 to 300pF capacitor Change R4 to 180pF capacitor Change R9 to 1μF capacitor In addition, replace the 460.8kHz clock source with a MHz clock source. Refer to Clock Configuration section for more details. Bias Current Resistor A resistor RBIAS is needed between OCBIAS and VSSA in order to create the bias current IOCB (IOCB=V/RBIAS). This bias current controls the operating point of internal functional blocks. It should be set to approximately 4.5μA. Since typical V is 1.5V, the recommended RBIAS value is 330KΩ. Clock Configuration The provides two clocking options: external crystal and CMOS clock input. The typical connection for the external MHz crystal is shown in Figure 9. The crystal and capacitor should be as close to as possible. C1 8pF MHz 8pF C2 OXTL IXTL Figure 9. Crystal oscillator connection The typical connection of CMOS clock input is shown in Figure 10 where an external MHz clock source is connected to OXTL. IXTL should connect to ground MHz OXTL IXTL Figure 10. CMOS clock connection SDIC Microelectronics Rev. 0.1b June Page 5 of 8

6 VSSA A Using the Typical Application Diagram Figure 11 is a typical smart transducer with HART capability using and SD2421 (4-20mA loop-powered DAC). Decouple the power supplies with 1μF and 0.1μF capacitors in parallel to ground, and decouple the REF pin with a 1μF capacitor to ground. HART signal comes in from the current loop s LOOP+ terminal, and goes into s pin through the external band-pass filter. demodulates the signal and passes the digital data to the MCU through the ORXD pin. To send HART signal out to the current loop, the MCU sends digital data to s ITXD pin. performs modulation and wave shaping, and send the HART signal out through its pin and the Cc capacitor to SD2421 s C3 pin. SD2421 then passes the signal to the current loop. 10k 0.1µF INRESET VSS _ENb TEST5 TEST8 TEST9 OCBIAS HART modem OCD ORXD ITXD INRTS VSS VSSA IXTL 1µF VCC 3.3V 0.1µF OXTL 1.2M 300pF 200k 330k 1µF 0.1µF 1µF 1.2M 180pF VCC depletion NFET LOOP+ Physical Quantity transducer Temperature sensor 16 bit ADC GND VREF MCU GND 4.7µF 4.7µF 100k 10nF VREF1 VREF2 VREF IN LATCH CLOCK DATA C1 10nF 0.47µF LV C2 VCC SD2421 current DAC C3 0.15µF BOOST COMP DRIVE COM LOOPRTN 2.2µF 10nF 1k 1nF 4-20mA Loop voltage source LOOP- C C 6.8nF Figure 11. Typical 4-20mA smart transducer with HART digital communication capability SDIC Microelectronics Rev. 0.1b June Page 6 of 8

7 Electrical Specifications Table 2. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit T A Operating temperature T S Storage temperature A, Supply voltage V VIN,VOUT Input/output voltage or +7 (whichever is less) V TL Reflow temperature profile Per IPC/JEDECJ-STD-020C ESD Human body model 4000 V Machine model 400 V Remarks: 1. CMOS device can easily be damaged by electrostatics. It must be stored in conductive foam, and with care taken to not exceed the operating voltage range. 2. Turn off power before inserting or removing the device. Table 3. Electrical Specifications (A==+2.7V~+5.5V, T A =-55 ~+125, VSSA=VSS=0V, external crystal, 8pF at IXTL/OXTL, OXTA with 4.7nF load, unless otherwise noted) Symbol Parameter Minimum Typical Maximum Unit Conditions/Remarks A IDD V Supply voltage V A+ Demodulator mode A+ Modulator mode Initial accuracy V μa External clock, -55 to μa External clock, -55 to External crystal, -55 to External crystal, -55 to μa External clock, -55 to μa External clock, -55 to External crystal, -55 to External crystal, -55 to +125 Load regulation 1.5 ppm/μa Tested with 500μA load Line regulation 60 μv/v IOCB Bias current 4.5 μa OCD assert Carrier amplitude mvp-p Input voltage V range Output amplitude 500 mvp-p 1 frequency 1200 Hz 0 frequency 2200 Hz Phase error 0 Maximum resistive load 160 Ω RLOAD shown in Figure5 External Frequency clock accuracy MHz Digital I/O parameter V IH Input high voltage 0.7* V V IL Input low voltage 0.3* V I IH Input high current ±0.1 μa I IL Input low current ±0.1 μa SDIC Microelectronics Rev. 0.1b June Page 7 of 8

8 A1 A A2 c D/2 + e Packaging Information E E/2 E/2 E min 1 Pin 1 Mark 24 0 min D D1 0.08R min 0.08/0.20R D/ L b Detail A Top View See Detail A Side View 1.00 Dimension: mm Symbol Min. Nom. Max. A 1.6 A A D 9.00 D/ D E 9.00 E/ E L e 0.80 b c Figure 12. LQFP32 mechanical specification SDIC Microelectronics Rev. 0.1b June Page 8 of 8