DSP Design in Wireless Communication LIANG LIU AND FREDRIK EDMAN,

Transcription

1 DSP Design in Wireless Communication LIANG LIU AND FREDRIK EDMAN,

2 Data Rate The Evolving Wireless Scene More bit/($ nj) More bit/sec 100Mb 10Mb 1Mb 100Kb 10Kb 1Kb 802.1a (LAN) Bluetooth (PAN) Sensor networks 3G Cellular 2.5 G Cellular Cellular (WAN) 1m 10m 100m 1km 10km Range Courtesy: Prof. Jan Rabaey, BWRC

3 Mbit/s Evolution of High-Speed Wireless WLAN Cellular 9.6Kb/s GSM 11Mb/s b 2Mb/s Kb/s GPRS 474Kb/s EDGE 54Mb/s ag 2Mb/s HSDPA 600Mb/s n 3.39Gb/s ac 7Gb/s ad 1Gb/s LTE-A 150Mb/s LTE 84Mb/s HSPA+ Wideband CDMA OFDM MIMO HighMod Massive MIMO G?

4 Same in other communication systems Wider road More passengers Wider bands Frequency More bits Multiple dimensions Multiple antennas

5 Algorithms beats Moore beats Chemists Algorithmic Complexity 3G Processor Performance (~Moore s Law) G G Battery Capacity Courtesy: Ravi Subramanian (Morphics)

6 Design Considerations Small area Low power Low price Reliable High speed Flexible Time to market

7 Optimizing DSP Implementation Functionality Circuit Module Architecture Algorithm Performance Implement ation Cost Optimization

8 Optimizing DSP Implementation

9 CDMA

10 CDMA: Code Division Multiple Access A UMTS Baseband Receiver Chip for Infrastructure Applications, Texas Instruments, S. Sriram et al.

11 Accumulator

12 ant UMTS filter in receiver system 33dB RF ADC Reconfig. UMTS filter De-scramble & despread demod Inband Outband desired signal Architectural Optimization for Low Power in a Reconfigurable UMTS Filter, in Proceedings of Wireless Personal Multimedia Communications Symposium (WPMC), Deepak Dasalukunte et al. San Diego, USA data

13 Adaptive UMTS Filter (Algorithm level) minimum 33dB stop band attenuation (3GPP specification) required filter length of 65 taps In a Bad Channel D D D D...but ONLY 5 is needed in a Good one!

14 Constant Multiplier (Module level) Coe[127] + Shift & Add Coe[127] MUX + Coe[126] D + Coe[126] MUX D + Coe[1] + Coe[1] MUX + Coe[0] D + Coe[0] MUX D + 14

15 Symmetric Coefficient (Architecture level) Shift & Add + D + Coe[1] MUX Coe[0] MUX + D + 15

16 OFDM

17 N-point IDFT Parallel to serial OFDM: Orthogonal Frequency Division Multiplexing x 0,k x 1,k s 0,k s 1,k CP x N 1, k s N 1, k OFDM

18 FFT/IFFT in OFDM Systems Large number of subcarriers a large FFT, O(Nlog 2 N) OFDM: DVB-2/4/8k FFT WLAN IEEE802.11a/g-64 FFT (48+4 subcarriers) LTE Long Term Evolution: 2k FFT

19 FFT: VLSI Architecture X 1 (k) X 2 (k) W N k -1 X 1 (k)+w N k X 2 (k) X 1 (k)-w N k X 2 (k) + Folding Pipeline Parallel

20 FFT: VLSI Architecture Multi-path delay commutator Signle-path delay feedback Buttfly FIFO Mult 50% 50% 50% 50% 100% 50%

21 FFT: Multi-path delay feedback Feature number Technology 0.13-μm Area 1.44mm 2 Throughput 1GS/s Power 39.6mW@4 09MS/s High-throughput

22 MIMO

23 Multiple Antenna System, MIMO Transmit Antennas The Radio Channel SISO Receive Antennas Transmit Antennas The Radio Channel SIMO Receive Antennas Single Input Single Output Single Input Multiple Output (Receive diversity) MISO MIMO Multiple Input Single Output (Transmit diversity) Multiple Input Multiple Output (Multiple data streams)

24 Understanding MIMO via Audio A SISO Interference MIMO! MISO At least as many receivers as transmitted streams Spatial separation at both transmit and receive antennas Improve transmission throughput or reliability Interference!

25 MIMO System Model Tx Rx Data S/P Tx Rx r = Hs + n Tx Rx Tx Rx s Transmitted vector N r Received vector H = M h 11 h 12.. h 1N h 21 h 22.. h 2N..... h ij models fading gain between the j th transmit and i th receive antenna h M1 h M2.. h MN

26 MIMO Signal Processing - Receiver Interference Cancellation! Tx Rx Data S/P Tx Tx Rx Rx r = Hs + n high-complexity Signal processing s^ Tx Rx Recover the transmitted signal s from the received signal r, which contains interference and noise.

27 MIMO Signal Processing - Receiver Tx Rx Receiver Signal Processing Data S/P Tx Tx Tx Rx Rx Rx r = Hs + n Channel Estimation H^ Symbol Detection H ^ -1 Matrix Manipulation s ^ = H ^ -1 r Channel estimation: obtain the channel status by training signals Matrix manipulation: matrix inversion or decomposition depending on detection algorithm Symbol detection: estimate transmitted signal s given channel matrix H and received signal r

28 MIMO Signal Detection r = Hs + n Linear Detection: zero-forcing detection s zf = H 1 r = s + H 1 n Maximum Likelihood (ML) Detection: exhaustive search s ml = arg max p(s r, H) s Q N = arg min r Hs 2 s Q N points per vector detection for 64-QAM, 4 4 MIMO

29 High Complexity ML Detection Tx Rx Receiver Signal Processing Data S/P Tx Tx Rx Rx ML Detection ^s WLAN n Example Modulation 256QAM; 4 Tx antennas; 108 sub-channels, 4ms per OFDM symbol ML detection x points/sec Current DSP technology is 1G inst/sec 10 8 processors! OR ( Moores Law... processor capability doubles every 18 months) Today Tx MUST WAIT 40years! Intel i7 CPU: inst/sec Rx Channel Estimation Matrix Manipulation Mike Faulkner 2005, Victoria Univ. H^

30 Sphere Decoding: Algorithm level optimization Simplified 2D-case ML Detection Sphere Detection Limited search space a reduced complexity

31 Sphere Decoding: complexity reduced Near optimal ML performance with significantly reduced computational complexity (# search points) BER Detection Performance ML Tree-Pruning Tree-Pruning+Reording 4 4 array 16-QAM SNR (db) Chia-Hsiang Yang, University of California, Los Angeles, 2007 Average # of Search Points Computational Complexity Total # search points=65536 ML Tree-Pruning Tree-Pruning+Reording SNR (db) Near ML detection with 0.1% computational complexity

32 Sphere Decoding: tree-search QR-Decomposition: H = QR R upper triangular matrix ˆ ML s argmin y Rs 2 with y Q H r leaf 2nd layer 3rd layer 4th layer P i -1 1 inc i -1 1 y1 R11 R12 R13 R14 s1 y 2 0 R22 R23 R 24 s 2 y3 0 0 R33 R34 s3 y R44 s4 Root K-Best Detection, e.g., K=2

33 Sphere Decoding: VLSI Design [1] Design [2] Design [3] Gate Counter 50K 91K 491K Throuput 136Mbps 269Mbps 1100Mbps

34 Systolic Array Systolic array A homogeneous network of tightly coupled Processing Elements (PEs) called cells or nodes The wave-like propagation of data through a systolic array resembles the pulse of the human circulatory system, the name systolic was coined from medical terminology

35 Systolic Array (example)

36 Systolic Array (T1)

37 Systolic Array (T2)

38 Systolic Array (T3)

39 Systolic Array (T4)

40 Systolic Array (T5)

41 Systolic Array (T6)

42 Systolic Array (T7)

43 Anything we can do at the transmitter?

44 MIMO Precoder: understanding via audio L + N L, 0.5 R + N L + N L, R 2(0.5 R + R N+ R N R ) If the receiver is not positioned directly between the speakers the received streams will be at different levels Equalizing at the receiver side? Like ZF, noise enhancement Balance at the transmitter side Require accurate channel information at the transmitter! Pre-code

45 pre-coding MIMO Precoder Tx Rx Data S/P Data S/P Tx Tx Rx Rx Low-Complexity Receiver s Tx Zero-forcing pre-coder x r = Hx Hs + n Rx r = Hx + n = HH 1 s + n r s 1 n 1 r 2 = s 2 + n 2 r s 3 n 3

46 The corresponding processor for MIMO?

47 Flexibility Digital Hardware Platforms GPP DSP GPU FPGA ASIP ASIC Efficiency

48 Digital Signal Processors for MIMO Flynn s Taxonomy Single instruction stream, single data stream (SISD) Single instruction stream, multiple data streams (SIMD) Multiple instruction streams, single data stream (MISD) Multiple instruction streams, multiple data streams (MIMD)

49 VLIW+SIMD VLIW (very long instruction word) Instruction-level parallelism, e.g., streaming of data SIMD (single instruction multiple data) Data-level parallelism, e.g., vectors

50 MIMO Processor Examples: Phillips EVP Vector Processor for LTE (2007)

51 Massive MIMO

52 64 5G wireless communication

53 Goes to LARGE Dimension?

54 Goes to LARGE Dimension Further Scaling Up? Size limitation in terminals Power consumption in portable devices Cellular Antenna WLAN Antenna HSPA n 4 4 LTE ac 8 4 LTE-A ? 16 16

55 How many antennas can we have? 2 in a phone 16 in a laptop 100X

56 Massive MIMO or Very-Large MIMO A1 UE1 BS UE2... AM UEK We think of very-large MIMO (multi-user) system We mean M>>K>>1 We are looking for M>100 antennas! We serve users concurrently F. Rusek, D. Persson, B. K. Lau, E.G. Larsson, T.L. Marzetta, O. Edfors, and F. Tufvesson, Scaling Up MIMO: Opportunities and Challenges with Very Large Arrays, IEEE Signal Processing Magazine, Jan. 2013

57 Massive MIMO (video)

58 Dream case 4G System 5G System Massive MIMO for 5G: Imagine a highway created just for you, no matter where you are!

59 Dream case

60 DSP for Massive MIMO Channel Encoding Interle aving Symbol Mapping OFDM Modulation Resampling Filtering Channel Encoding Interle aving OFDM Modulation Resampling Filtering 1 K Analog TX Analog TX 1 M Channel Decoding Deinte rleav Symbol Demap Channel Decoding Deinte rleav Symbol Demap OFDM Demod. Digital Front-end 1 K Analog RX... OFDM Demod. Digital Front-end Analog RX Symbol Mapping 1 M 1 M MIMO Precoding Channel Estimation + MIMO Detection Reciprocity Calibration Memory Memory Data Transfer Network Data Transfer Network Central Processing Per-antenna Processing Per-user Processing

61 Design challenges massive MIMO system with 20MHz High computation count: multiplication/s for ZF-based MIMO processing Low processing latency: 285μs RX-TX turnaround time for moderate mobility Large data storage: 9.8MB memory for channel matrix Complicated data shuffling: 11GB/s information exchange for 16-bit wordlength 74

62 Memory subsystem in Massive MIMO High capacity and throughput Channel matrix in massive MIMO v.s. 4 4 in LTE-A Multiple access patterns Column wise:h H H Row wise: Hy Diagonal wise: H H H+αI Adjustable operand matrix size H H H/H H H+αI/(H H H+αI) -1 (K K) 75

63 Flexible memory access Multi-bank memory

64 Conflict-free parallel memory scheme column 77 Permutation Pattern Generate Unit Address Generate Unit Control Logic write read row v 0 v 1 v Memory Bank0 v 2 Permutation Network Inverse-Permutation Network x32 index of target memory module diagonal

65 Conclusions Digital signal processing is evolving at fast pace with new wireless technologies and applications Optimal DSP implementation is crucial to bring new DSP algorithm into practice Best design achieves balanced trade-offs depending on application requirements Optimization at earlier stages and do cross-layer (or co-) optimization Keep tracking new technologies for both algorithm and implementation

66 Thanks