Introduction and DSP Basics. Viktor Öwall

Transcription

1 DSP Design Introduction and DSP Basics Viktor Öwall it lth

2 Where do we find it? The first pacemaker 1958 Karolinska Institutet, Stockholm

3 What is a Digital Signal Processor? Works on time discrete sampled data of a continous signal Real time requirement Data driven Programmable or Custom DSPs What to use depends on requirements Sample rate Throughputh t Power - energy Area Wordlength precision Flexibility Time to market Volume

4 Where do we find it? Very Low Power Sample Rate: 8/16kHz Extremely Low Power Sample Rate: <1kHz Low Power Ex. Sample Rate UMTS filter: 15MHz

5 Example of DSP Applications Speech & Audio coding, MP3 recognition echo cancellation Image coding, MPEG4 Filtering Wireless Communication Channel coding/decoding g Equalization Channel estimation Smart antennas Beam forming MIMO, Multiple Input Multiple Output Etc, Etc, Etc...

6 Example of DSP Primitives Convolutions Filters FIR IIR Wave digital Correlation FFT DCT LMS Least Mean Square etc...

7 Two Basic DSP Structures x(n) h0 D D D h1 h2 h3 x(n) D y(n) y(n) D FIR Finite it Impulse Response IIR Infinite it Impulse Response 4-tap FIR filter No feedback Biquad section Feedback

8 Often comprised of several DSP primitives - Acoustic Echo Cancellation - No delay in signal path Delay in coefficient update Morgan and Thi, 1995 Subband approach Reduces complexity and achieves Faster convergence Anders Berkeman

9 Nr. of Subbands For computational complexity the most important parameter is the number of subbands. FIR 889Mmult/s mult/s 1000 FFT FB LMS 90% FFT FB LMS 43Mmult/s FIR 76% Nr. of Subbands

10 Echo Canceller chip 0.35 m, 5 Metal Layer CMOS, 2002 Data Sample rate = 16kHz Target f clk = 17MHz 128 subbands >2M transistors (46k cells) 10 RAM - 247kbits 2 ROM - 29kbits 120 IO 5.019x5.76mm 2 = 29mm 2

11 Different applications, different demands... a simplified view Flexibilty Complexity Low power Low cost Flexibilty Lower power Lower cost Processors Processors ASICs FPGAs ASICs Processors

12 Standard Processors or Special Purpose Algorithm Standard Processor Programable/Flexible Short design time/ttm Low price? Special Purpose High calculation capacity Low power consumption Low price at volume What is volume? Main focus of this Course

13 Architectural options OTS (Off The Shelf) processors Programmable microprocessors or DSP Based on generic computational units, for DSPs usually MAC Prefabbed or IP cores Time-multiplexed application specific processors Several algorithmic operations performed on same hardware unit Trades reduced HW for longer computation time Hardware mapped architectures One (or more) hardware unit per algorithmic operation High HW cost and high throughput

14 Time multiplexed to save hardware Time-multiplexed MUX c FIR : y N 1 k 00 n h k x n k Hardware mapped x(n) D D D h0 h1 h2 h3 REG y(n) N cc/sample 1 sample/cc 1 generalized e ed multiplier N fixed multipliers 1 adders N-1 adders 1 coefficient memory + control

15 Hardware Implementation Techniques Hardware Solution FPGA Full Custom More on Thursday!

16 This course mainly looks at specialized architectures Could be used for either FPGA or ASIC

17 Energy Efficiency One of the key design issues today! Why energy and not power?

18 Utilizing the computation time? Can we control the clock frequency? MIPS Compute as fast as we can? Compute as slow as we re allowed? Time Max computation time What power down options do we have? clock gating various sleep modes Can we scale the power supply? Dynamic How many levels What cell library can we choose? Low power High speed

19 Energy efficiency (MOPS/mW) 1000 Energ gy and Area Efficiencie es ,1 Microprocessors General Purpose DSP s Dedicated Designs 0, Courtesy: Professor Bob Brodersen, UC Berkeley Chip Number (see next slide)

20 ISSCC Chips (0.18μm 0.25μm)

21 Results in fully parallel solutions Reducing supply voltage saves energy: E = CV 2 Energy Area 64-point FFT Energy per Transform (nj) 16-State Viterbi Decoder Energy per Decoded bit (nj) 64-point FFT Transforms per second per unit area (Trans/ms/mm 2 ) 16-State Viterbi Decoder Decode rate per unit area (kb/s/mm 2 ) Direct-Mapped Hardware , ,000 FPGA Low-Power DSP High-Performance DSP (numbers taken from vendor-published benchmarks) Orders of magnitude lower efficiency even for an optimized processor architecture Courtesy Ning Zhang, Berkeley Wireless Research Center (BWRC)

22 Questions? Which structure gets the job done? Which structure use the least energy? Which structure use the least area? Etc, etc, etc... How do we design architectures to achieve it?

23 ...and now to the course!

24 Scope How to get from a signal processing algorithm to an EFFICIENT implementation using Different numbering systems Pipelining Parallelism li Unfolding and folding Strength reduction, i.e. complexity of operations. etc, etc,... in a structured way! Case studies: FFT, image filtering, acoustic echo cancellation, pacemakers,...

25 Goals Aims: Knowledge After completing the course the student should: have gained an understanding for the relationship between parameters such as calculation capacity, power consumption and silicon area be familiar with transformations that help the designer to develop different solutions for a given signal processing algorithm. understand how different number representations affect the solution. Aims: Skills After completing the course the student should: be able to suggest a processor architecture from a given set of critera. be able to analyze a processor architecture t and suggest alternative ti solutions. Aims: Attitude After completing the course the student should: have gained an overview of the field of implementation aspects of signal processing algorithms. feel well equipped to design an application specific processor given a specification using the methodologies covered in the course.

26 Logistics Web: / / ti180 Lectures Tuesdays, 13-15, 15 in MH:A Thursdays, 15-17, in E:1406 Seminars Wednesdays and No seminar 1 st week Weeks 2 and 3 in E:2349 Weeks 4 to 7 in E:4116 Question hours Fridays and by Reza Meraji, Room E:2336

27 Compulsary Parts 2 labs, planned for weeks 3 and 6 & 7 MATLAB (2 hours) Hardware design in CatapultC (2 + 2 hours) Homework seminars, week 4 and 6 results in grade 3 Written exam for grade 4 & 5 Wednesday, December 16. 2pm-7pm.

28 Litterature Course Litterature Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation Extended Reading Alan V. Oppenheim, Ronald W. Schafer with John R. Buck, Discrete-Time Signal Processing, Prentice Hall, 1999, ISBN John G. Proakis and Dimitris Manolakis, Digital Signal Processing: Principles, Algorithms and Applications, Prentice Hall, 1995, ISBN Sanjit K. Mitra, Digital Signal Processing. A Computer Based Approach, McGRAW-HILL, 2001 ISBN: X Lars Wanhammar, DSP Integrated Circuits, Academic Press, 1999, ISBN Seminar exercises and Lab manual will be available on the web.

29 Map E-building 2 nd floor Reza Viktor, 3 rd floor

30 Digital Complexity some examples from Wireless Systems

31 The Evolving Wireless Scene More bit/($ nj) More bit/sec Data a Rate 100Mb 10Mb 1Mb 100Kb 10Kb 1Kb 802.1a (LAN) Bluetooth (PAN) Sensor networks Metropolitan 3G Cellular 2.5 G Cellular Cellular (WAN) One solution cannot fit all systems! 1m 10m 100m 1km 10km Range Courtesy: Prof. Jan Rabaey, BWRC

32 OFDM s x 0, k 0,k s x 1,k 1,k CP x N 1, k N-poin nt IDFT s N 1, k l to serial Paralle Large number of subcarriers large FFT OFDM: DVB-2/4/8k FFT WLAN IEEE802.11a/g-64 FFT (48+4 subcarriers) LTE Long Term Evolution

33 The Cost of Approaching Shannon s Bound ve Co mplex xity /2 LDPC, N=10 7, 1100 iterations 8/9 Capacity Bound 2/3 Capacity Bound 1/2 Capacity Bound 2/3 Turbo, =4, N=64k 1,2, and 3 iterations 8/9 Turbo, =4, N=4k for BER of 10-5 Relati /2 Turbo, =4, N=64k 1,2, and 3 iterations 1/2 Conv. Code, =4, N=64k 2/3 Conv. Code, =4, N=64k 8/9 LDPC, N=4k 1,3, 8/9 Conv. Code, and 5 iterations =3, N=4k SNR (db) Courtesy Engling Yeo, UCB

34 The Cost of Approaching Shannon s Bound Relativ ve Com mplex xity /2 LDPC, N=10 7, 1100 iterations 1/2 Capacity Bound 1/2 Turbo, =4, N=64k 1,2, and 3 iterations 1/2 Conv. Code, =4, N=64k for BER of SNR (db) Courtesy Engling Yeo, UCB

35 Multiple Antenna Systems e.g. MIMO Tx Rx High complexity receiver Data S/P Tx Tx Tx Rx Rx Rx r = Hs + n Channel Estimation H^ Symbol Detection H ^-1 Matrix Inversion ^s = H^ -1 r Multi-antenna approach exploits multi-path by sending data along several channels Results in large theoretical improvements in bandwidth efficiency for fading channels But computationally hungry PE PE PE PE PE PE PE PE PE QR-factorisation PE PE PE PE PE Inversion of triangular submatrix PE PE PE PE PE PE

36 MIMO Hardware perspective Tx Rx Data S/P Tx Tx Tx Rx Rx Rx r = Hs + n Channel Estimation H^ Symbol Detection H ^ -1 Matrix Inversion ^s = H ^ -1 r WLAN n Example Modulation 256QAM; 4 Tx antennas; 108 sub-channels, 4 s per symbol ML detection x lattice points/sec Current DSP technology is 1G inst/s 10 8 processors! OR ( Moores Law... processor capability doubles every 18 months) MUST WAIT 40years! From Mike Faulkner, Victoria Univ.

37 RTrading Complexity 4x4 antennas B E R Sub-optimal QPSK (square-root) root) 035μm 0.35 Sphere 16QAM 0.35 μm ML-detection #mult/ symbol + Soft Output 0.13 μm

38 ML Detection Sphere Decoding Simplified 2D-case Sphere Detection Limited search space reduced complexity

39 Looking at Complexity

40 The number of transistors per chip will double every year. (1965)... in 1975 changes to every 2 years Isn t Moore Enough? Moores s Law Gordon Moore One of the founders of Intel Technology roadmap:

41 Algorithms beats Moore beats Chemists Algorithmic Complexity G Processor Performance (~Moore s Law) G G Battery Capacity Courtesy: Ravi Subramanian (Morphics)

42 Complexity Complexity of Algorithms are increasing with new systems Number of transistors possible to implement on a die is incresing (Moore s law) Often mature algorithms (systems) go to non-custom solutions. But there is always new algorithms and there is power and price...

43 Evolution Mature systems i.e. low performance compared to state of the art implemented on standard platforms mature technologies ex. GSM New systems i.e. high performance use non-standard architectures and components ex. 3G or new generations...

44 DSP basics

45 Digital signal processing algorithms works on samples of a continous signals. Sampling rate = nr. of samples processed/second Continous signal Analog Digital Sampled signal Digital Signal Processing

46 Two Basic DSP Structures x(n) h0 D D D h1 h2 h3 x(n) D y(n) y(n) D FIR Finite it Impulse Response IIR Infinite it Impulse Response 4-tap FIR filter No feedback Biquad section Feedback

47 N 1 k 0 The FIR filter y y n h k x n k h(.) is the impulse response which defines the filter response, e.g. low- or highpass. x(n) x(n-1) x(n-2) x(n-3) D D D h0 h1 h2 h3 y(0)

48 The FIR filter x(n) D D D h0 h1 h2 h3 y(n) A higher order filter, more taps, will result in a steeper filter function but has higher complexity! The filter order is nr. of taps - 1

49 FIR filter in Matlab x(n) D D D h0 h1 h2 h3 y(n) FIR-filters can be designed with fir1(n,wn) N th order filter with the cut-off frequency Wn must be between 0 < Wn < 1.0, with 1.0 corresponding to half the sample rate taps order

50 FIR-filter frequency response Use fft to transform h(.) to frequency domain and plot taps 8-taps Symmetry when real input to fft.

51 Linear phase FIR filters Linear phase filters has a constant group delay in the passband, i.e. all frequency components are delayed equally no phase distortion. Linear phase filters, e.g. from fir1(), has symmetric coefficients. i This can be used to simplify the filter structure. x(n) D D D D x(n) D D D D h0 h1 h2 h3 h4 y(n) y(n)

52 The FIR filter, hardware mapped y N 1 n h k x n k k 0 y( 0) h0 x(0) h1 x( 1) h2 x( 2) h3 x( 3) clock x(0) R x(-1) R x(-2) R x(-3) E E E G G G h0 h1 h2 h3 y(0)

53 The FIR filter The input samples have been delayed one time unit, i.e. clock cycle! y 1 h x 1 hx 0 h x 1 h x x(1) x(0) x(-1) x(-2) D D D h0 h1 h2 h3 y(1)

54 The FIR filter, next clock cycle y N 1 n h k x n k k 0 y( 1) h0 x(1) h1 x(0) h2 x( 1) h3 x( 2) clock x(1) R x(0) R x(-1) R x(-2) E E E G G G h0 h1 h2 h3 y(1)

55 Time multiplexed l to save hardware x(n) FIR : D D D y N 1 k 00 n h k x n k MUX c h0 h1 h2 h3 REG 1 sample/cc N fixed multipliers li N-1 adders y(n) N cc/sample 1 generalized multiplier 1 adders 1 coefficient memory + control

56 Time multiplexed l to save hardware 0 Sample Mem x(n) How many clock cycles? MUX coeff Why the 0? Why the extra reg? REG REG y(n) x(n) h0 D D D h1 h2 h3 y(n)

57 Time multiplexed l to save hardware Sample cc0: x(0)h(0)+0 0 Mem 0 x(0) MUX coeff h(0) REG REG y(-1) x(n) h0 D D D h1 h2 h3 y(n)

58 Time multiplexed l to save hardware x(0)h(0) Sample cc0: x(0)h(0)+0 0 Mem cc1: x(-1)h(1)+x(0)h(0) x(-1) MUX coeff h(1) REG REG y(-1) x(n) h0 D D D h1 h2 h3 y(n)

59 Time multiplexed l to save hardware x(-1)h(1)+ x(0)h(0) MUX Sample cc0: x(0)h(0)+0 0 Mem cc1: x(-1)h(1)+x(0)h(0) x(-2) cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0) coeff h(2) REG REG y(-1) x(n) h0 D D D h1 h2 h3 y(n)

60 Time multiplexed l to save hardware x(-2)h(2)+ x(-1)h(1)+ x(0)h(0) MUX Sample cc0: x(0)h(0)+0 0 Mem cc1: x(-1)h(1)+x(0)h(0) x(-3) cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0) coeff cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0) h(3) REG REG y(-1) x(n) h0 D D D h1 h2 h3 y(n)

61 Time multiplexed l to save hardware 0 MUX Sample cc0: x(0)h(0)+0 0 Mem cc1: x(-1)h(1)+x(0)h(0) x(1) cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0) coeff cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0) h(0) cc4: x(1)h(0)+0; new iteration REG REG y(0) x(n) h0 D D D h1 h2 h3 y(n)

62 Time multiplexed l to save hardware 0 Sample Mem x(n) sample CONTROL MUX coeff reset address FSM Finite State Machine REG REG load x(n) D D D y(n) h0 h1 h2 h3 y(n)

63 The IIR filter, direct form I The impulse response also includes feedback terms. m i j yn bxn i ayn j i 0 j 1 x(n) b 0 y(n) + + Z -1 Z b a 1 Z -1 n Z -1 b m-1 + Z 1 + a n-1 Z -1 Z b -1 m a n Steeper impulse response but possibility for unstability

64 The IIR filter, direct form II m n i j i 0 j 1 y n bx n i a y n j Each part is a linear time-invariant system and dthe order can be reversed. x(n) + a 1 + Z -1 Z -1 b 0 + Z -1 b 1 + Z -1 y(n) + a n-1 a n Z -1 b m-1 + Z -1 b m

65 The IIR filter, direct form II m n i j i 0 j 1 y n bx n i a y n j The two parts can be collapsed into one with a minimum number of delay elements. x(n) b Z -1 b 1 a Z -1 y(n) + a n-1 a n Z -1 b m-1 b m +

66 The IIR filter, cascade form N s b b z b z H z ; Ns N 1 /2 s 1 2 0k 1k 2k 1 2 k 1 1 a 1 kz a 2 kz x(n) y(n) D D D D D D Often cascaded with shorter sections which are combined, easier to design when fixed-point arithmetic. The above is often referred to as biquad sections.

67 DFT - FFT The DFT/FFT is one of the most common digital signal processing algorithms. Used to determine frequency content of a discrete signal sequence. Transform between time and frequency domains. The FFT is a low complexity way of computing the DFT.

68 N-point DFT X ( k ) N 1 n 0 x ( n ) W kn N, k 0,1,..., N 1 W N filters of length N O(N 2 ) kn N e j2 kn/ N Complex x(n) () N N X(0) X(1) Only every N th sample N X(N-1) The DFT determines spectral content at N equally spaced frequency points, i.e. coorelates with different frequencies, N samples are needed. f analysis ( m) mf sample N

69 FFT is low complexity DFT x(0) X(0) x(1) X(8) x(2) W 0 X(4) x(3) W 4 X(12) log 2 ( N) stages x(4) x(5) x(6) W 0 W 2 W 6 W 0 X(2) X(10) X(6) DFT O( N 2 ) x(7) x(8) W 0 W 8 W 4 X(14) X(1) x(9) W 1 X(9) FFT N 2 log2( N) x(10) x(11) x(12) W 2 W 0 W 3 W 4 W 4 W 0 X(5) X(13) X(3) x(13) W 5 W 2 X(11) x(14) W 6 W 4 W 0 X(7) x(15) W 7 W 6 W 4 X(15)