A Low Power and Low Latency Inter Carrier Interference Cancellation Architecture in Multi User OFDM System

Transcription

1 Journal of Scientific & Industrial Research Vol. 75, July 2016, pp A Low Power and Low Latency Inter Carrier Interference Cancellation Architecture in Multi User OFDM System M N Kumar 1 * and G T Arasu 2 *1 Department of Electronics and Communication Engineering, Vivekanandha College of Technology for Women, Elayampalayam AVS Engineering College, Salem Received 3 October 2015; revised 24 April 2016; accepted 5 May 2016 The Inter carrier interference (ICI) and inter block interference (IBI) are the two signal degradations on multi user orthogonal frequency division multiplexing (OFDM) communication system. In this paper, a noval methodology is proposed for the detection and reduction of ICI in received OFDM symbols. The vector precoding technique is proposed to reduce the ICI and more bandwidth efficient than other precoding techniques to eliminate ICI. The precoding architecture is used to determine the level of interference in the received OFDM symbols. The proposed interference cancellation architecture is designed and implemented in VLSI for analyzing its low power, bit error rate and energy consumption with conventional methods. Keywords: Inter Carrier Interference, Low power, VLSI, Bit Error Rate, OFDM. Introduction Spectral efficiency transmission and reception of data is important for wireless communications. Orthogonal frequency division multiplexing (OFDM) is one of the techniques for spectrally efficient data transmission and reception in Multi-input Multioutput scheme over the time varying channel. This technique splits the wideband signal into number of orthogonal subcarriers and then includes the symbol period between the orthogonal subcarriers. This OFDM symbol period between the subcarriers is corrupted when the OFDM signal passes through the time varying channel. The inter carrier interference (ICI) occurs due to this symbol period corruption in high mobility environment 1. Cyclic prefix (CP) is generally added between the orthogonal subcarriers in OFDM to maintain the orthogonality between the subcarriers. Let x be the transmitted OFDM symbols without including CP and the signal is represented as, x = [x (1) x (2), x (N)] T (1) where, x(1), x(2), x(n) represents the orthogonal subcarriers and N is the length of the OFDM signal.the CP is included between the orthogonal subcarriers and the OFDM transmitted signal is represented as, Author for correspondence nareshece84@gmail.com x = [x (1) CP (1) x (2), CP (M-1) x (N)] T... (2) where, CP(1), CP(2)..CP(M-1) represents the cyclic prefix and M signifies the length of the cyclic prefix.this OFDM signal with CP is transmitted through the time varying wireless channel and the channel response is represented as L 1 g ( t) l 0Tl ( t). ( T Tl ) (3) where, T l is the path delay, T l (t) is the gain of the time varying l-th path and L is the total number of paths.a Channel Estimation for OFDM System using Polynomial Fitting employed two training symbols in combination with polynomial fitting 2. The total leastsquares (TLS) scheme was used to eliminate the ICI, ISI and noise 3.The Tomlinson Harashima precoder and Dirty paper coding algorithms were applied on the OFDM subcarriers to eliminate interference between the adjacent subcarriers 4. Proposed Method A convoluational encoder is used to encode the binary input data prior to a baseband adaptive modulator which adaptively changes the digital modulation formats such as BPSK, QPSK and QAM based on the condition of the channel. The lower order modulation (BPSK and QPSK) is preferred when the channel is worst in condition and the higher

2 428 J SCI IND RES VOL 75 JULY 2016 order modulation (QAM) is preferred when the channel is good in condition. The condition of the channel is determined by measuring the bit-error rate (BER). The pilot symbols are inserted before the symbols are converted to parallel form to transmit the signals through the channel. Subsequently, the inverse fast Fourier transform (IFFT) process converts the symbols from the frequency domain into time domain and then they are once again converted into serial format. The resulting sequence is converted to an analog signal using a Digital to analog converter (DAC), and then the resulting RF modulated signal is transmitted to the receiver using transmit antenna.the proposed OFDM receiver section is illustrated in Fig. 1. The serial data received from the channel is converted into parallel form and then it is translated from time to frequency domain signal using FFT.The pilot symbols are detected and removed using cyclic prefix detector. The presence of Inter Carrier Interference (ICI) is determined using interference Estimator as shown in Fig. 2. Let c1 be the number Fig. 1 Proposed OFDM receiver system Fig. 2 Interference Estimator

3 KUMAR & ARASU: A LOW POWER AND LOW LATENCY INTER CARRIER INTERFERENCE CANCELLATION 429 of 1 s in the received sequence and c2 be the number of 0 s in the received sequence. If c1>c2, then 1 is assigned for s0-s6, 0 is assigned for c0-c7 and f0-f1. If c1<c2, then 0 is assigned for s0-s6, 1 is assigned for c0-c7 and f0-f1. Devised novel Algorithm and Architecture for OFDM receiver have been developed 5.The right singular vector matrix derived from the SVD results of the channel matrix gives the optimal pre-coding matrix for linear detectors such as zero-forcing (ZF) and minimum mean square error (MMSE) detectors 6.The data received from the channel is split and applied to the input of the interference estimator module. The split sequences are transmitted through the one bit shifter and then the directly split data and data passed through the one bit shifter is summed up and then applied to the multiplexer. The multiplexer produces the output based on the select lines c0-c7. The output from each multiplexer is summed/subtracted based on the select lines s0-s5. The outputs from these are one bit shifted and applied to the saturate adder which will produce the sequence to the multiplexer. The output responses such as block1 and block2 are based on the select lines f0 and f1. The interference is occurred if the value of block1 is greater than or equal to the value of block2. The signals thus received are unaffected by the interference, if the value of block2 is greater than the value of block1. A hardwareefficient SVD algorithm VLSI architecture for steering matrix computation was proposed. It utilizes bidiagonalization, diagonalization, and Givens rotation to achieve high processing throughput 7. The problem of reducing pre-processing complexity in linear MIMO-OFDM receivers on an algorithmic level by formulating efficient interpolation based algorithms for matrix inversion that take the polynomial nature of the MIMO channel transfer function explicitly into account 8.If the interference is occurred in the received sequence, then it applied to the Inter Carrier Interference (ICI) cancellation architecture as shown in Fig. 3. This architecture produces the output final1 and final2 by passing the received sequence through the circuit as depicted in Fig. 3. The output response final1 is produced by subtracting the values from the output of MUX 1 from the output of MUX 2. The output response final1 is produced by subtracting the values from the output of MUX 3 from the output of MUX 4. The control bit Mode is set to 1 for the time varying channel. The sign bit is 1 under the condition when LL(00) is less than the value of LL(01) otherwise it is set to 0. The concatenation of the final1 and final2 signals gives the final interference suppressed signal. Fig. 3 Interference Cancellation Architecture

4 430 J SCI IND RES VOL 75 JULY 2016 Results and Discussion The proposed OFDM system is designed with the integration of inter-carrier interference cancellation algorithm and the same is simulated using MATLAB software (version R2014b) and the parameters used for this simulation are given as: 127 subchannels size of the IFFT/FFT is 256 length of the cyclic prefix is 32 upsampling factor is 4 The proposed design of inter-carrier interference (ICI) cancellation algorithm uses Verilog HDL and is simulated using Modelsim software. The performance analysis of the proposed ICI architecture is done by simulation over various Virtex devices. The input for proposed ICI architecture is obtained from the real time mobile environment with noises. For the initial simulation setup, the clock frequency is set to 200MHz with onoff clock period of The proposed architecture consumes 1680 gates for its design. The power and current consumptions are observed for different devices of the Virtex family and tabulated in Table 3. The proposed ICI architecture has been analyzed in terms of decoding latency, gate counts (GC), Power Consumption (PC), and Current Consumption (CC) for its performance estimation. Table 2 explains the performance evaluation of the proposed decoder in terms of decoding latency. Unitary precoding matrices for transmit beamforming can be computed efficiently through inexact interpolation under unitarity constraints in MIMO-OFDM systems with limited feedback 9.The proposed code is simulated and then it is downloaded into the Virtex device for its performance measurement. The amount of power consumed by the proposed ICI architecture is measured using X-primer or power analyzer tool available in the Xilinx tool. The input to the Virtex unit is obtained from the real time mobile signals received through the channel with noise signals. The ICI architecture proposed in this paper has been compared with other devices in terms of power utilizations by evaluating it over different Virtex devices. The ICI architecture, proposed in this work has been mainly designed with the aim of reducing the power levels during its operation. Table 1 already discussed the power utilizations of various Virtex devices and has shown that the power consumption levels of such devices are at Table 1 Constraints for select lines Condition S0-S5 C0-C7 F0-F1 C1>C2 All bits Set 1 All bits Set 0 All bits Set 0 C2>C1 All bits Set 0 All bits Set 1 All bits Set 1 Methodology Table 2 Analysis of decoding latency Decoding latency(ns) CMOS technology Frequency (MHz) Proposed nm 200 Shaik Rahimunnisha et al. (2014) [10] Konguvel et al. (2013) [13] nm nm 450 Table 3 Comparison of power consumptions of conventional methods Methodology Power Consumption (mw)** CMOS technology Energy Consumption (nj)* Proposed method 32 45nm Shaik Rahimunnisha et al. (2014) [10] Raja et al. (2012) [11] Shingo Yoshizawa et al. (2006) [12] nm nm nm *Energy consumption of one clock period. This comparison is only for the energy in one clock cycle, which maps to the power consumption. **Code rate is 0.96 and word length is 7 bits with 8 iterations. lower levels. Numerous performance assessment parameters and resource utilization parameters were determined for the proposed OFDM system. The current research mainly focuses on low power applications and therefore OFDM is being designed and developed for this purpose. The proposed OFDM-ICI architecture is synthesized using Xilinx project navigator version 9.2i tool. The decoding latency is about ns in the proposed architecture; whereas the decoding latencies obtained about ns and ns, respectively 10, 13. Hence, the proposed ICI architecture design performs better than most other conventional decoding methods and is proved in Table 3 with performance comparisons. Power consumption is about 32mW in the proposed architecture; whereas the Power consumption obtained about ns and ns, respectively 11, 12.

5 KUMAR & ARASU: A LOW POWER AND LOW LATENCY INTER CARRIER INTERFERENCE CANCELLATION 431 Conclusion The inter carrier interference affects the performance of the OFDM system. The vector precoding is employed with OFDM system to reduce the ICI from the received symbols. The performance of the OFDM system integrated with vector precoding is analyzed in terms of SNR and BER by varying the channel conditions and modulation formats. The level of interference is estimated from the data received from the time varying channel and then interference cancellation algorithm is applied to reduce the interference level in the OFDM symbols. The proposed design of inter-carrier interference (ICI) cancellation algorithm is designed using Verilog HDL and synthesized using Xilinx project navigator tool. The proposed interference cancellation algorithm and its architecture consumes nj of energy consumption tested on 45nm technology. References 1 Ye L & Cimini L J, Bounds on the interchannel interference of OFDM in time varying impairments, IEEE Trans Comm,49(3) (2001) Huang C, Chao-W C & Shyue-W, Channel Estimation for OFDM System with Two Training Symbols Aided and Polynomial Fitting, IEEE Trans Comm, 58(3) (2010) Tongliang F, Haowei W & Hongcheng H, Channel Estimation and Interference Cancellation for OFDM Systems Based on Total Least Squares Solution, Int J of Comm, 6(8) (2011) Gowshameed, Chanemougapriya, IBI and ICI cancellation for MIMO OFDM based on Tomlinson Harashima precoder and dirty paper coding, Int J of Sci Engg & Tech Res, 4(2) (2015) Troya A, Maharatna K, Milo s K, Grass E, Jagdhold U & Kraemer R, Efficient Inner Receiver Design for OFDM- Based WLAN Systems Algorithm and Architecture, IEEE Tran on Wirel Comm, 6(4) (2007) Love D J & Heath R W, Limited feedback unitary precoding for spatial multiplexing systems, IEEE Trans Inf Theory, 51(8) (2005) Senning C, Studer C, Luethi P, & Fichtner W, Hardwareefficient steering matrix computation architecture for MIMO communication systems, IEEE Int Symp Circuits Syst, (2008) Borgmann M & Bölcskei H, Interpolation-based efficient matrix inversion for MIMO-OFDM receivers, Asilomar Conf Signals Syst Compu Pacific Grove CA, (2004) Choi J & Heath R W, Jr, Interpolation-based transmit beamforming for MIMO-OFDM with limited feedback, IEEE Int Conf Commun (ICC), Paris, France, (2004) Shaik R, Lakshmi S & Aparna D, Low Power VLSI Design of MIMO-OFDM Detection for Wireless LAN Networks, Int J of Elec & Comm Tech, 5(3) (2014) Raja J & Kannan M, VLSI implementation of high throughput MIMO-OFDM transceiver for 4th generation systems, Ind J of Engg & Mat Sci, 19 (2012) Yoshizawa S & Miyanaga Y, VLSI implementation of SISO-OFDM and MIMO-OFDM transceivers, IEEE Inter conf on Comm & Info Tech, 4 (2006) Konguvel E, Raja J & Kannan M, A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme, Int J of Comp Appl, 77(5) (2013) 9-15.