KH207 Low Distortion Wideband Op Amp
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1 Low Distortion Wideband Op Amp Features 80/85dBc 2nd/3rd HD at 20MHz 3dB bandwidth of 70MHz 0.% settling in 22ns Complete overdrive protection 2400V/µs slew rate 3MΩ input resistance Output may be current limited Direct replacement for CLC207 Applications Fast, precision A/D conversion Automatic test equipment Input/output amplifiers Photodiode, CCD preamps Highspeed modems, radios Line drivers NonInverting Input Inverting Input Not Connected Case ground GND R f Ω V V 5 NC 4 Case and bias ground Bottom View 3 GND Internal Feedback 2 NC V CC 9 V CC Not Connected V CC 2 V CC Voltage Voltage Collector Output Collector Pin 8 provides access to a 2000Ω feedback resistor which can be connected to the output or left open if an external feedback resistor is desired. General Description The is a wideband, low distortion operational amplifier designed specifically for applications requiring both high speed and wide dynamic range. Utilizing a proprietary current feedback architecture, the offers performance far superior to that of conventional voltage feedback op amps. The most attractive feature of the is its extremely low distortion: 80/85dBc 2nd/3rd harmonics at 20MHz (2V pp, R L = 200Ω). The also provides 3dB bandwidth of 70MHz at a gain of 20, settles to 0.% in 22ns and slews at a rate of 2400V/µs. The combination of these features positions the as the right choice for high speed applications requiring exceptional signal purity. High speed, high resolution A/D and D/A converter systems requiring low distortion operation will find the an excellent choice. Wide dynamic range systems such as radar and communication receivers will find that the s low harmonic distortion and low noise make it an attractive high speed solution. The addition of the to the KH205/20 Series of high speed operational amplifiers broadens the selection of features available from which to choose. The KH205 offers low power operation, the KH20 offers higher drive operation, and the offers operation with extremely low distortion, all of which are pin compatible and overdrive protected. The is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: AI 25 C to 85 C 2pin TO8 can AK 55 C to 25 C 2pin TO8 can, features burnin & hermetic testing AM 55 C to 25 C 2pin TO8 can, environmentally screened and electrically tested to MILSTD883 HXC 55 C to 25 C SMD#: HXC HXA 55 C to 25 C SMD#: HXA Typical Performance Setting Parameter Units 3dB bandwidth MHz rise time ns slew rate V/ns settling time (to 0.%) ns REV. A January 2004
2 Electrical Characteristics (A v = 20V, V CC = ±5V, R L = 200Ω, R f = 2kΩ; unless specified) PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM Ambient Temperature AI 25 C 25 C 25 C 85 C Ambient Temperature AK/AM/HXC/HXA 25 C 55 C 25 C 25 C FREQUENCY DOMAIN RESPONSE 3dB bandwidth <2V pp 70 >40 >40 >25 MHz SSBW largesignal bandwidth <V pp 0 >72 >80 >80 MHz FPBW gain flatness <2V pp peaking 0. to 35MHz 0 <0.3 <0.3 <0.5 db GFPL peaking >35MHz 0 <0.8 <0.5 <0.8 db GFPH rolloff at 70MHz <0.8 <0.8 <0.8 db GFR group delay to 70MHz 3.0 ±.2 ns GD linear phase deviation to 50MHz 0.8 <3.0 <2.0 <3.0 LPD TIME DOMAIN RESPONSE rise and fall time 2V step 2.2 <2. <2. <3.0 ns TRS V step 4.8 <5.5 <5.5 <5.5 ns TRL settling time to 0.% V step, note 2 22 <27 <27 <27 ns TS to 0.05% V step, note 2 24 <30 <30 <30 ns TSP overshoot 5V step 7 <4 <4 <4 % OS slew rate 20V pp at 50MHz 2.4 >.8 >2.0 >2.0 V/ns SR NOISE AND DISTORTION RESPONSE 2nd harmonic distortion 2V pp, 20MHz, R L = 200Ω 80 <8 <7 <7 dbc HD2 2V pp, 20MHz, R L = 0Ω 9 <4 <4 <4 dbc HD2 3rd harmonic distortion 2V pp, 20MHz, R L = 200Ω 85 <7 <7 <7 dbc HD3 2V pp, 20MHz, R L = 0Ω 9 <4 <4 <4 dbc HD3 equivalent input noise voltage >0kHz. <.8 <.8 <.8 nv/ Hz VN inverting current >0kHz 20 <23 <23 <23 pa/ Hz ICN noninverting current >0kHz 2.2 <2.5 <2.5 <2.5 pa/ Hz NCN noise floor >0kHz 58 <57 <57 <57 dbm(hz) SNF integrated noise khz to 50MHz 33 <38 <38 <38 µv INV integrated noise 5MHz to 50MHz 33 <38 <38 <38 µv INV STATIC, DC PERFORMANCE * input offset voltage 3.5 <8.0 <8.0 <.0 mv VIO average temperature coefficient <25 <25 <25 µv/ C DVIO * input bias current noninverting 3.0 <25 <5 <5 µa IBN average temperature coefficient 5 <0 <0 <0 na/ C DIBN * input bias current inverting 2.0 <22 < <25 µa IBI average temperature coefficient 20 <50 <50 <50 na/ C DIBI * power supply rejection ratio 9 >55 >55 >55 db PSRR common mode rejection ratio 0 >50 >50 >50 db CMRR * supply current no load 25 <27 <27 <29 ma ICC MISCELLANEOUS PERFORMANCE noninverting input resistance DC 3.0 >.0 >.0 >.0 MΩ RIN noninverting input capacitance 70MHz 5.0 <7.0 <7.0 <7.0 pf CIN output impedance DC <0. <0. <0. Ω RO output voltage range no load ±2 >± >± >± V VO internal feedback resistor 2.0 kω RF absolute tolerance <0.2 % RFA temperature coefficient 0 ±40 ppm/ C RFTC inverting input current self limit 2.2 <3.0 <3.0 <3.2 ma ICL Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings Recommended Operating Conditions V CC ±20V V CC ±5V to ±5V I o ±50mA I o ±0mA common mode input voltage, V CC > 5V ±(29 V CC )V common mode input voltage ±( V CC 5)V V CC 5V ±( V CC )V gain range 7 to 50, to 50 differential input voltage ±3V note : * AI/AK/AM/HXC/HXA 0% tested at 25 C thermal resistance (see thermal model) AK/AM/HXC/HXA 0% tested at 25 C and sample junction temperature 75 C tested at 55 C and 25 C operating temperature AI: 25 C to 85 C AI sample tested at 25 C AK/AM/HXC/HXA: 55 C to 25 C note 2: Settling time specifications require the use of an external storage temperature 5 C to 50 C feedback resistor (2kΩ). lead temperature (soldering s) 300 C 2 REV. A January 2004
3 DATA SHEET Typical Performance Characteristics (T A = 25 C,A v = 20,V CC = ±5V, R f = 20Ω,R L = 200Ω; unless specified) NonInverting Frequency Response Inverting Frequency Response Frequency Response vs. External R f Normalized Magnitude (db/div) A v = 7 A v = 20 Av = 50 A v = 7 Av = 50 A v = 20 Normalized Magnitude (db/div) A v = 50 A v = 20 A v = Av = 7 A v = 20 Av = Av = 7 A v = 50 Relative (5dB/div) A v = 50 R f = 3kΩ R f =.5kΩ Av = 20 R f = 3kΩ R f =.5kΩ Av = 7 R f = 3kΩ R f =.5kΩ R f = 2kΩ R f = 2kΩ R f = 2kΩ Magnitude (db/div) Output Voltage (0.4V/div) Large Signal and = V pp Small Signal Pulse Response Av = 20 A v = 20 Time (5ns/div) Relative Bandwidth Relative Bandwidth vs. V CC ±V CC (V) Output Voltage (2V/div) Large Signal Pulse Response Av = 20 A v = 20 Time (5ns/div) Settling Error (%) Magnitude (db/div) and for Various Loads R L = kω RL = 200Ω RL = 0Ω R L = 50Ω R L = 50Ω R L = 0Ω R L = 200Ω R L = kω Settling Time Time (5ns/div) V step R f = 2kΩ (external) Distortion (dbc) PSRR and CMRR (db) 2nd and 3rd Harmonic Distortion rd 2nd 90 0 CMRR and PSRR PSRR CMRR 0 0 k k 0k M M 0M Frequency (Hz) Interdept Point (dbm) Distortion (dbc) 2nd Harmonic Distortion, R L = 0Ω Vpp 8V pp 4V pp 2V pp V pp Tone, 3rd Order Intermod. Intercept 45 50Ω Pout 40 50Ω Noise Voltage (nv Hz) Distortion (dbc) 3rd Harmonic Distortion, R L = 0Ω 20 Vpp V pp 8V pp 2Vpp V pp 90 0 Equivalent Input Noise 0 0 Inverting Current 20pA Hz NonInverting Current 2.2pA Hz Voltage.nV/ Hz Frequency (Hz) Noise Current (pa Hz) REV. A January
4 Current Feedback Amplifiers Some of the key features of current feedback technology are: Independence of AC bandwidth and voltage gain Adjustable frequency response with feedback resistor High slew rate Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a noninverting or inverting current feedback amplifier is approximated by Equation. where: Equation A v is the closed loop DC voltage gain R f is the feedback resistor Z(jω) is the CLC205 s open loop transimpedance gain Zj ( ω) is the loop gain R f The denominator of Equation is approximately equal to at low frequencies. Near the 3dB corner frequency, the interaction between R f and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing R f has the following affects: Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Overdrive Protection Unlike most other highspeed op amps, the is not damaged by saturation caused by overdriving input signals (where V in x gain > max. ). The self limits the current at the inverting input when the output is saturated (see the inverting input current self limit specification); this ensures that the amplifier will not be damaged due to excessive internal currents during overdrive. For protection against input signals which would exceed either the maximum differential or common mode input voltage, the diode clamp circuits below may be used. Vin Vcc common mode protection Vo = Vin Vcc Av Rf Zj ω ( ) differential protection Figure : Diode Clamp Circuits for Common Mode and Differential Mode Protection R g Short Circuit Protection Damage caused by short circuits at the output may be prevented by limiting the output current to safe levels. The most simple current limit circuit calls for placing resistors between the output stage collector supplies and the output stage collectors (pins 2 and ). The value of this resistor is determined by: V RC = C RI II where I I is the desired limit current and R I is the minimum expected load resistance (0Ω for a short to ground). Bypass capacitors of 0.0µF on should be used on the collectors as in Figures 2 and 3. 5V Capactance in µf V in R i 50Ω 5V ,7 R g 9 200Ω. Figure 2: Recommended NonInverting Circuit Figure 3: Recommended Inverting Circuit A more sophisticated current limit circuit which provides a limit current independent of R I is shown in Figure 4 on page 5. With the component values indicated, current limiting occurs at 50mA. For other values of current limit (I I ), select R C to equal V be /l I. Where V be is the base to emitter voltage drop of Q3 (or Q4) at a current of [2V CC.4] / R x, where R x [(2V CC.4) / I I ] B min. Also, B min is the minimum beta of Q (or Q2) at a current of I I. Since the limit current depends on V be, which is temperature dependent, the limit current is likewise temperature dependent..0 5V Capactance in µf A R f v = Rg R f = 2000Ω (internal) 50Ω 2 8 R g 5 V in 3,7 200Ω R i 9 R Av = f 5V Rg R f = 2000Ω (internal) For Z in = 50Ω, select R g R i = 50Ω 4 REV. A January 2004
5 DATA SHEET Rc 2Ω Q (MJE70) Vcc to pin 2 to pin 0.0ΩF Q3 (2N390) Rx 4.3kΩ Noise Analysis Approximate noise figure can be determined for the using the Equivalent Input Noise plot on page 3 and the equations shown below. kt = 4.00 x 2 Joules at 290 K V n is spot noise voltage (V/ Hz) i n is noninverting spot noise current (A/ Hz) i i is inverting spot noise current (A/ Hz) 0.0ΩF Q2 (MJE80) Rc 2Ω Q4 (2N3904) R s R n R g R f R o Vcc Figure 4: Active Current Limit Circuit (50mA) Controlling Bandwidth and Passband Response In most applications, a feedback resistor value of 2kΩ will provide optimum performance; nonetheless, some applications may require a resistor of some other value. The response versus R f plot on the previous page shows how decreasing R f will increase bandwidth (and frequency response peaking, which may lead to instability). Conversely, large values of feedback resistance tend to roll off the response. The best settling time performance requires the use of an external feedback resistor (use of the internal resistor results in a 0.% to 0.2% settling tail). The settling performance may be improved slightly by adding a capacitance of 0.4pF in parallel with the feedback resistor (settling time specifications reflect performance with an external feedback resistor but with no external capacitance). Thermal Model T case R R V R i s s n f i F = 2 log i n R n 4 kt R p Rp A v Rs Rn R f where R p = ; A v = Rs Rn R g Figure 5: Noise Figure Diagram and Equations (Noise Figure is for the Network Inside this Box.) Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the will improve stability and settling performance. Transmission Line Matching One method for matching the characteristic impedance (Z o ) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure shows typical inverting and noninverting circuit configurations for matching transmission lines. 0 C/W T j(pnp) P pnp 0 C/W T j(npn) P npn 7.5 C/W T j(circuit) P circuit θ ca T ambient V R R4 Z 0 Z 0 C R 3 Z 0 R 2 R R g R f R 7 P circuit = [(V CC ) (V CC )] 2 /.77kΩ P xxx = [(±V CC ) ut (I col ) (R col )] (I col ) (% duty cycle) (For positive and V CC, this is the power in the npn output stage.) (For negative and V CC, this is the power in the pnp output stage.) θ ca = 5 C/W in still air without a heatsink. 35 C/W in still air without a Thermalloy C/W in 300ft/min air with a Thermalloy 228 (Thermalloy 2240 works equally well.) I col = ut /R load or 3mA, whichever is greater. (Include feedback R in R load.) R col is a resistor ( recommended) between the xxx collector and ±V CC. T j (pnp) = P pnp (0 θ ca ) (P cir P npn )θ ca T a, similar for T j (npn). T j (cir) = P cir (7.5 θ ca ) (P pnp P npn )θ ca T a. V 2 R 5 Figure : Transmission Line Matching Noninverting gain applications: Connect R g directly to ground. Make R, R 2, R, and R 7 equal to Z o. Use R 3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. REV. A January
6 Inverting gain applications: Connect R 3 directly to ground. Make the resistors R 4, R, and R 7 equal to Z o. Make R 5 II R g = Z o. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C to match the output transmission line over a greater frequency range. C compensates for the increase of the amplifier s output impedance with frequency. Dynamic Range (Intermods) For RF applications, the specifies a third order intercept of 2dBm at 0MHz and P o = dbm. A 2Tone, 3rd Order IMD Intercept plot is found in the Typical Performance Characteristics section. The output power level is taken at the load. Thirdorder harmonic distortion is calculated with the formula: HD 3 rd = 2 (IP3 o P o ) where: IP3 o = thirdorder output intercept, dbm at the load. P o = output power level, dbm at the load. HD 3 rd = thirdorder distortion from the fundamental, dbc. dbm is the power in mw, at the load, expressed in db. Realized thirdorder output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that improve 3 rd order distortion are: short and equal return paths from the load to the supplies. decoupling capacitors of the correct value. higher load resistance. a lower ratio of the output swing to the power supply voltage. Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance the performance of the. Good ground plane construction and power supply bypassing close to the package are critical to achieving full performance. In the noninverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal stray capacitance to the ground plane or other nodes. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: Include.8µF tantalum and 0.µF ceramic capacitors on both supplies. Place the.8µf capacitors within 0.75 inches of the power pins. Place the 0.µF capacitors less than 0. inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flushmount printed circuit board pins for prototyping, never use high profile DIP sockets. An evaluation PC board (part number ) for the is available to aid in device testing. REV. A January 2004
7 Package Dimensions A L e e φd D e F φb 3 2 k α k TO8 INCHES MILIMETERS SYMBOL Minimun Maximum Minimum Maximum A φb φd φd e BSC. BSC e BSC 5.08 BSC e BSC 2.54 BSC F k k L α 45 BSC 45 BSC NOTES: Seal: cap weld Lead finish: gold per MILM385 Package composition: Package: metal Lid: Type A per MILM385
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