KH205 Overdrive-Protected Wideband Op Amp

Transcription

1 OverdriveProtected Wideband Op Amp Features 3dB bandwidth of 17MHz.1% settling in 22ns Complete overdrive protection Low power: 57mW (19mW at ±5V) 3MΩ input resistance Output may be current limited Direct replacement for CLC25 Applications Fast, precision A/D conversion Automatic test equipment Input/output amplifiers Photodiode, CCD preamps IF processors Highspeed modems, radios Line drivers Output Voltage (2V/div) Large Signal Pulse Response NonInverting Input Inverting Input Not Connected Case ground A v = 2 Av = 2 GND R f 7 8 2Ω V V 5 NC Case and bias ground Bottom View 4 3 GND Internal Feedback 2 NC V CC 9 1 V CC Not Connected V CC V CC Voltage Voltage Collector Output Collector Pin 8 provides access to a 2Ω feedback resistor which can be connected to the output or left open if an external feedback resistor is desired. General Description The is a wideband overdriveprotected operational amplifier designed for applications needing both speed and low power operation. Utilizing a wellestablished current feedback architecture, the exhibits performance far beyond that of conventional voltage feedback op amps. For example, the has a bandwidth of 17MHz at a gain of 2 and settles to.1% in 22ns. Plus, the has a combination of important features not found in other highspeed op amps. For example, the has been designed to consume little power 57mW at ±15V supplies. The result is lower power supply requirements and less systemlevel heat dissipation. In addition, the device can be operated on supply voltages as low as ±5V for even lower power dissipation. Complete overdrive protection has been designed into the part. This is critical for applications, such as ATE and instrumentation, which require protection from signal levels high enough to cause saturation of the amplifier. This feature allows the output of the op amp to be protected against short circuits using techniques developed for lowspeed op amps. With this capability, even the fastest signal sources can feature effective short circuit protection. The is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: AI 25 C to 85 C 12pin TO8 can AK 55 C to 125 C 12pin TO8 can, features burnin & hermetic testing AM 55 C to 125 C 12pin TO8 can, environmentally screened and electrically tested to MILSTD883 HXC 55 C to 125 C SMD#: HXC HXA 55 C to 125 C SMD#: HXA Typical Performance Setting Parameter Units 3dB bandwidth MHz rise time ns slew rate V/ns settling time (to.1%) ns REV. 1A January 24

2 Electrical Characteristics (A v = 2V, V CC = ±15V, R L = 2Ω, R f = 2kΩ; unless specified) PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM Ambient Temperature AI 25 C 55 C 25 C 125 C Ambient Temperature AK/AM/HXC/HXA 25 C 55 C 25 C 125 C FREQUENCY DOMAIN RESPONSE 3dB bandwidth = <2V pp 17 >14 >14 >125 MHz SSBW largesignal bandwidth = <V pp >72 >8 >8 MHz FPBW gain flatness = <2V pp peaking.1 to 35MHz <.3 <.3 <.5 db GFPL peaking >35MHz <.5 <.5 <.8 db GFPH rolloff at 7MHz <.8 <.8 <.8 db GFR group delay to 7MHz 3. ±.2 ns GD linear phase deviation to 7MHz.8 <3. <2. <3. LPD TIME DOMAIN RESPONSE rise and fall time 2V step 2.2 <2. <2. <3. ns TRS V step 4.8 <5.5 <5.5 <5.5 ns TRL settling time to.1% V step, note 2 22 <27 <27 <27 ns TS to.5% V step, note 2 24 <3 <3 <3 ns TSP overshoot 5V step 7 <14 <14 <14 % OS slew rate 2V pp at 5MHz 2.4 >1.8 >2. >2. V/ns SR NOISE AND DISTORTION RESPONSE 2nd harmonic distortion 2V pp, 2MHz 57 <5 <5 <5 dbc HD2 3rd harmonic distortion 2V pp, 2MHz 8 <55 <55 <55 dbc HD3 equivalent input noise voltage >khz 2.1 <3. <3. <3.5 nv/ Hz VN inverting current >khz 22 <3 <3 <35 pa/ Hz ICN noninverting current >khz 4.8 <.5 <.5 <7.5 pa/ Hz NCN noise floor >khz 157 <154 <154 <153 dbm(1hz) SNF integrated noise 1kHz to 15MHz 39 <55 <55 <1 µv INV noise floor >5MHz 157 <154 <154 <153 dbm(1hz) SNF integrated noise 5MHz to 15MHz 39 <55 <55 <1 µv INV STATIC, DC PERFORMANCE * input offset voltage 3.5 <8. <8. <11. mv VIO average temperature coefficient 11 <25 <25 <25 µv/ C DVIO * input bias current noninverting 3. <25 <15 <15 µα IBN average temperature coefficient 15 < < < na/ C DIBN * input bias current inverting 2. <22 < <25 µa IBI average temperature coefficient 2 <15 <15 <15 na/ C DIBI * power supply rejection ratio 9 >55 >55 >55 db PSRR common mode rejection ratio >5 >5 >5 db CMRR * supply current no load 19 <2 <2 <22 ma ICC MISCELLANEOUS PERFORMANCE noninverting input resistance DC 3. >1. >1. >1. MΩ RIN noninverting input capacitance 7MHz 5. <7. <7. <7. pf CIN output impedance DC <.1 <.1 <.1 Ω RO output voltage range no load ±12 >±11 >±11 >±11 V VO internal feedback resistor absolute tolerance <.2 % RFA temperature coefficient ±4 ppm/ C RFTC inverting input current self limit 2.2 <3. <3. <3.2 ma ICL Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings Recommended Operating Conditions V CC ±2V V CC ±5V to ±15V I o ±75mA I o ±5mA common mode input voltage ±( V CC 1)V common mode input voltage ±( V CC 5)V differential input voltage ±3V gain range 7 to 5, 1 to 5 thermal resistance (see thermal model) operating temperature AI: 25 C to 85 C note 1: * AI/AK/AM/HXC/HXA % tested at 25 C AK/AM/HXC/HXA: 55 C to 125 C AK/AM/HXC/HXA % tested at 25 C and sample tested storage temperature 5 C to 15 C at 55 C and 125 C lead temperature (soldering s) 3 C AI sample tested at 25 C note 2: Settling time specifications require the use of an external feedback resistor (2Ω) 2 REV. 1A January 24

3 DATA SHEET Typical Performance Characteristics (T A = 25 C, A v = 2, V CC = ±15V, R L = 2Ω; unless specified) NonInverting Frequency Response Inverting Frequency Response Frequency Response vs. External R f Normalized Magnitude (1dB/div) A v = 7 A v = 2 A v = 5 Av = 7 A v = 5 Av = 2 (45 /div) Normalized Magnitude (1dB/div) Av = 5 A v = 2 Av = 1 A v = 7 A v = 2 Av = 1 A v = 7 Av = 5 (45 /div) Relative (5dB/div) A v = 5 R f = 3kΩ R f = 1.5kΩ A v = 2 Rf = 3kΩ R f = 1.5kΩ A v = 7 R f = 3kΩ R f = 1.5kΩ R f = 2kΩ R f = 2kΩ Rf = 2kΩ Magnitude (1dB/div) Output Voltage (.4V/div) Large Signal and Vo = Vpp Small Signal Pulse Response A v = 2 Av = 2 (45 /div) Relative Bandwidth Relative Bandwidth vs. V CC ±V CC (V) Output Voltage (2V/div) Large Signal Pulse Response A v = 2 A v = 2 Settling Error (%) Magnitude (1dB/div) and for Various Loads RL = 1kΩ R L = 2Ω R L = Ω R L = 5Ω RL = 5Ω R L = Ω R L = 2Ω RL = 1kΩ Settling Time V step R f = 2kΩ (external) (45 /div) Distortion (dbc) 2nd and 3rd Harmonic Distortion Vo = 2Vpp 2nd rd 8 1 Equivalent Input Noise Intercept (dbm) 2Tone 3rd Order Intermodulation Intercept Thermal Model Tcase PSRR and CMRR (db) CMRR and PSRR PSRR CMRR 1k k k 1M M M Frequency (Hz) Noise Voltage (nv/ Hz) Inverting Current 18.3 pa/ Hz NonInverting Current 2.5 pa/ Hz Voltage 1.8 nv/ Hz 1k k k 1M M Frequency (Hz) Noise Current (pa/ Hz) 2 C/W Tj(pnp) Ppnp 2 C/W Tj(npn) Pnpn 17.5 C/W Tj(circuit) Pcircuit P circuit = [(V CC ) (V CC )] 2 / 1.77kΩ Tambient P xxx = [(±V CC ) ut (I col ) (R col )] (I col ) (% duty cycle) (For positive and V CC, this is the power in the npn output stage.) (For negative and V CC, this is the power in the pnp output stage.) θca I col = ut /R load or 3mA, whichever is greater. (Include feedback R in R load.) R col is a resistor ( recommended) between the xxx collector and ±V CC. T j (pnp) = P pnp (2 θ ca ) (P cir P npn )θ ca T a, similar for T j (npn). T j (cir) = P cir (17.5 θ ca ) (P pnp P npn )θ ca T a. REV. 1A January 24 3

4 Current Feedback Amplifiers Some of the key features of current feedback technology are: Independence of AC bandwidth and voltage gain Adjustable frequency response with feedback resistor High slew rate Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a noninverting or inverting current feedback amplifier is approximated by Equation 1. where: Equation 1 A v is the closed loop DC voltage gain R f is the feedback resistor Z(jω) is the CLC25 s open loop transimpedance gain Zj ( ω) is the loop gain R f The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the 3dB corner frequency, the interaction between R f and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing R f has the following affects: Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Overdrive Protection Unlike most other highspeed op amps, the is not damaged by saturation caused by overdriving input signals (where V in x gain > max. ). The self limits the current at the inverting input when the output is saturated (see the inverting input current self limit specification); this ensures that the amplifier will not be damaged due to excessive internal currents during overdrive. For protection against input signals which would exceed either the maximum differential or common mode input voltage, the diode clamp circuits below may be used. Vin V cc Vo = Vin 1 common mode protection Av Rf Zj ω ( ) Vcc differential protection Figure 1: Diode Clamp Circuits for Common Mode and Differential Mode Protection R g Short Circuit Protection Damage caused by short circuits at the output may be prevented by limiting the output current to safe levels. The most simple current limit circuit calls for placing resistors between the output stage collector supplies and the output stage collectors (pins 12 and ). The value of this resistor is determined by: V RC = C RI II where I I is the desired limit current and R I is the minimum expected load resistance (Ω for a short to ground). Bypass capacitors of.1µf on should be used on the collectors as in Figures 2 and 3. 15V Capactance in µf V in R i 5Ω 15V ,7 R g 9 2Ω.1 Figure 2: Recommended NonInverting Circuit Figure 3: Recommended Inverting Circuit A more sophisticated current limit circuit which provides a limit current independent of R I is shown in Figure 4 on page 5. With the component values indicated, current limiting occurs at 5mA. For other values of current limit (I I ), select R C to equal V be /l I. Where V be is the base to emitter voltage drop of Q3 (or Q4) at a current of [2V CC 1.4] / R x, where R x [(2V CC 1.4) / I I ] B min. Also, B min is the minimum beta of Q1 (or Q2) at a current of I I. Since the limit current depends on V be, which is temperature dependent, the limit current is likewise temperature dependent..1 15V Capactance in µf A 1 R f v = Rg R f = 2Ω (internal) 5Ω R g 5 V in 3,7 2Ω R i 9 R Av = f 15V Rg R f = 2Ω (internal) For Z in = 5Ω, select R g R i = 5Ω 4 REV. 1A January 24

5 DATA SHEET Rc 12Ω Q1 (MJE17) Vcc to pin 12 to pin Q2 (MJE18) Rc 12Ω V cc.1ωf.1ωf Q3 (2N39) Rx 14.3kΩ Q4 (2N394) Figure 4: Active Current Limit Circuit (5mA) Controlling Bandwidth and Passband Response In most applications, a feedback resistor value of 2kΩ will provide optimum performance; nonetheless, some applications may require a resistor of some other value. The response versus R f plot on the previous page shows how decreasing R f will increase bandwidth (and frequency response peaking, which may lead to instability). Conversely, large values of feedback resistance tend to roll off the response. The best settling time performance requires the use of an external feedback resistor (use of the internal resistor results in a.1% to.2% settling tail). The settling performance may be improved slightly by adding a capacitance of.4pf in parallel with the feedback resistor (settling time specifications reflect performance with an external feedback resistor but with no external capacitance). Noise Analysis Approximate noise figure can be determined for the using the Equivalent Input Noise plot on page 3 and the equations shown below. kt = 4. x 21 Joules at 29 K V n is spot noise voltage (V/ Hz) i n is noninverting spot noise current (A/ Hz) i i is inverting spot noise current (A/ Hz) R R V R i s s n f i F = 2 log 1 i n R n 4 kt R p Rp A v Rs Rn R f where R p = ; A v = 1 Rs Rn R g Figure 5: Noise Figure Diagram and Equations (Noise Figure is for the Network Inside this Box.) Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the will improve stability and settling performance. Transmission Line Matching One method for matching the characteristic impedance (Z o ) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure shows typical inverting and noninverting circuit configurations for matching transmission lines. V 1 V 2 R1 R4 Z Z Figure : Transmission Line Matching Noninverting gain applications: Connect R g directly to ground. Make R 1, R 2, R, and R 7 equal to Z o. Use R 3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: C R 3 Z R 2 R R g R f R 5 Connect R 3 directly to ground. Make the resistors R 4, R, and R 7 equal to Z o. Make R 5 II R g = Z o. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C to match the output transmission line over a greater frequency range. C compensates for the increase of the amplifier s output impedance with frequency. R 7 R s R n R g R f R o Dynamic Range (Intermods) For RF applications, the specifies a third order intercept of 3dBm at MHz and P o = dbm. A 2Tone, 3rd Order IMD Intercept plot is found in the Typical Performance Characteristics section. The output power level is taken at the load. Thirdorder harmonic distortion is calculated with the formula: HD3 rd = 2 (IP3 o P o ) REV. 1A January 24 5

6 where: IP3 o = thirdorder output intercept, dbm at the load. P o = output power level, dbm at the load. HD3 rd = thirdorder distortion from the fundamental, dbc. dbm is the power in mw, at the load, expressed in db. Realized thirdorder output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that improve 3 rd order distortion are: short and equal return paths from the load to the supplies. decoupling capacitors of the correct value. higher load resistance. a lower ratio of the output swing to the power supply voltage. Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance the performance of the. Good ground plane construction and power supply bypassing close to the package are critical to achieving full performance. In the noninverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal stray capacitance to the ground plane or other nodes. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: Include.8µF tantalum and.1µf ceramic capacitors on both supplies. Place the.8µf capacitors within.75 inches of the power pins. Place the.1µf capacitors less than.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flushmount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation PC boards (part number 738 for inverting, 739 for noninverting) for the are available to aid in device testing. REV. 1A January 24

7 Package Dimensions A L e 1 e φd D 1 e F φb k α k 1 TO8 INCHES MILIMETERS SYMBOL Minimun Maximum Minimum Maximum A φb φd φd e.4 BSC.1 BSC e 1.2 BSC 5.8 BSC e 2. BSC 2.54 BSC F k k L α 45 BSC 45 BSC NOTES: Seal: cap weld Lead finish: gold per MILM385 Package composition: Package: metal Lid: Type A per MILM385